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arm: socfpga: Allow board specific config values for env

PATCH New Stefan Roese 4 participants 15 messages Oct 23, 2015 – Nov 19, 2015

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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Stefan Roese

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#0 lore raw

PATCH 1/1 arm: socfpga: Allow board specific config values for env

This patch enables the usage of board-specific values for the environment offset and size in SPI NOR flash.

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 include/configs/socfpga_common.h | 4 ++++
 1 file changed, 4 insertions(+)
include/configs/socfpga_common.h +4 -0
index cece095..ebf0c48 100644
@@ -281,7 +281,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#ifndef CONFIG_ENV_SIZE
 #define CONFIG_ENV_SIZE			4096
+#endif
 
 /*
  * SPL

@@ -327,8 +329,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_DM_SEQ_ALIAS		1
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
+#ifndef CONFIG_SYS_SPI_U_BOOT_OFFS
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
 #endif
+#endif
 
 /*
  * Stack setup
Signature · 1 line
2.6.2
author
#1 lore raw

PATCH 1/1 arm: socfpga: Add CONFIG_BUILD_TARGET to socfpga_common.h

By defining this macro, the combined image of SPL and main U-Boot will get built automatically.

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 include/configs/socfpga_common.h | 3 +++
 1 file changed, 3 insertions(+)
include/configs/socfpga_common.h +3 -0
index ebf0c48..f09b37d 100644
@@ -339,4 +339,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
 
+/* Build the combined SPL plus U-Boot image automatically */
+#define CONFIG_BUILD_TARGET		"u-boot-with-spl-dtb.sfp"
+
 #endif	/* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
Signature · 1 line
2.6.2
author
#3 lore raw

PATCH 1/1 arm: socfpga: Add SoCFPGA SR1500 board

In reply to Stefan Roese

The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 arch/arm/dts/Makefile                    |   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
 arch/arm/mach-socfpga/Kconfig            |   6 +
 board/sr1500/MAINTAINERS                 |   6 +
 board/sr1500/Makefile                    |   7 +
 board/sr1500/qts/iocsr_config.h          | 660 +++++++++++++++++++++++++++++++
 board/sr1500/qts/pinmux_config.h         | 219 ++++++++++
 board/sr1500/qts/pll_config.h            |  85 ++++
 board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
 board/sr1500/socfpga.c                   | 144 +++++++
 configs/socfpga_sr1500_defconfig         |  17 +
 include/configs/socfpga_sr1500.h         | 120 ++++++
 12 files changed, 1709 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h
arch/arm/dts/Makefile +3 -1
index ddc6a05..b77aab48 100644
@@ -74,7 +74,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
-	socfpga_cyclone5_socrates.dtb
+	socfpga_cyclone5_socrates.dtb			\
+	socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +101 -0

101 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +6 -0
index a413ea4..aa12df2 100644
@@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -38,6 +42,7 @@ config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "sr1500" if TARGET_SOCFPGA_SR1500
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK

@@ -55,5 +60,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 
 endif
board/sr1500/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..ed013a8
@@ -0,0 +1,6 @@
+SOCFPGA SR1500 BOARD
+M:	Stefan Roese <[email protected]>
+S:	Maintained
+F:	board/sr1500/
+F:	include/configs/socfpga_sr1500.h
+F:	configs/socfpga_sr1500_defconfig
board/sr1500/Makefile new file +7 -0
new file mode 100644
index 0000000..eae7ad0
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
board/sr1500/qts/iocsr_config.h new file +660 -0

660 lines not on this page · raw message

board/sr1500/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/sr1500/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/sr1500/qts/sdram_config.h new file +341 -0

341 lines not on this page · raw message

board/sr1500/socfpga.c new file +144 -0

144 lines not on this page · raw message

configs/socfpga_sr1500_defconfig new file +17 -0
new file mode 100644
index 0000000..11dea35
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
include/configs/socfpga_sr1500.h new file +120 -0

120 lines not on this page · raw message

Signature · 1 line
2.6.2
#4 lore raw

PATCH 1/1 arm: socfpga: Add SoCFPGA SR1500 board

Quoted 1 line · Stefan Roese

The SR1500

Does SR mean Stefan Roese ? :-)

Anyway, shouldn't you place this device under board/vendorname/boardname instead of plain board/boardname/ ?

And one more thing, would it be possible for you to do a short README on adding a new board? That'd be real cool. Obviously, it's not something I demand or that'd block this patch series, it'd be nice though.

Quoted 11 lines

board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

[...]

board/sr1500/socfpga.c line 40

Quoted 12 lines
board/sr1500/socfpga.c new file +12 -0
+int board_early_init_f(void)
+{
+	int ret;
+
+	/* Reset the Marvell PHY 88E1510 */
+	ret = gpio_request(63, "PHY reset");
+	if (ret)
+		return ret;
+
+	gpio_direction_output(63, 0);
+	mdelay(20);
+	gpio_set_value(63, 1);

Does the PHY come out of reset immediatelly after you deassert the nRESET GPIO or not ? You might want to add a small delay here to bullet-proof the code a bit more.

Quoted 7 lines
board/sr1500/socfpga.c new file +6 -0
+	return 0;
+}
+
+#define CONFIG_SYS_IDT_CLK_ADDR		0x6a
+
+static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c line 58

Quoted 10 lines
board/sr1500/socfpga.c new file +10 -0
+	u8 buf[1];
+
+	buf[0] = 0x01;
+	i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
+
+	return 0;
+}
+
+U_BOOT_CMD(clksave, 1, 0, do_clksave,
+	   "IDT 5V49EE702 Progsave command", "");

I am not convinced I should let this slide. Wouldn't it be better to just have an environment script which sends 0x1 to this IDT Versaclock using the i2c command ?

board/sr1500/socfpga.c line 65

Quoted 6 lines
board/sr1500/socfpga.c new file +6 -0
+#define NET_DEV_NAME			"ethernet at ff702000"
+#define MII_MARVELL_PHY_PAGE		22
+#define PHY_DIAG_START			(1 << 15)
+#define PHY_DIAG_BUSY			(1 << 11)
+
+static char str[16];

Please move this static var into do_phytest() and pass it into pair_state() as an argument.

Quoted 7 lines
board/sr1500/socfpga.c new file +7 -0
+static char *pair_state(int val)
+{
+	switch (val) {
+	case 0x00:
+		strcpy(str, "Invalid");
+		break;
+	case 0x01:

board/sr1500/socfpga.c line 83

Quoted 10 lines
board/sr1500/socfpga.c new file +10 -0
+		strcpy(str, "Pair Ok");
+		break;
+	case 0x02:
+		strcpy(str, "Pair Open");
+		break;
+	case 0x03:
+		strcpy(str, "Same Pair Short");
+		break;
+	case 0x04:
+		strcpy(str, "Cross Pair Short");

Do I count correctly that you do strcpy() here on a string which is 16 byte long + one trailing '\0' (total 17 bytes) and you strcpy() it into 16 byte long buffer ? Well that's not good, this will overwrite one byte past the $str buffer with '\0' :-)

Quoted 14 lines
board/sr1500/socfpga.c new file +13 -0
+		break;
+	case 0x09:
+		strcpy(str, "Pair Busy");
+		break;
+	default:
+		strcpy(str, "Reserved");
+		break;
+	};
+
+	return str;
+}
+
+static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c line 98

Quoted 1 line
board/sr1500/socfpga.c new file +1 -0
+	char devname[] = NET_DEV_NAME;

const char * here ?

board/sr1500/socfpga.c line 99

Quoted 1 line
board/sr1500/socfpga.c new file +1 -0
+	int addr = 0;

Looks like unsigned value to me, please make it so.

Quoted 8 lines
board/sr1500/socfpga.c new file +8 -0
+	u16 data;
+	u16 status;
+	u16 oldpage;
+	int i;
+
+	/* Save current page register */
+	miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
+

board/sr1500/socfpga.c line 117

Quoted 10 lines
board/sr1500/socfpga.c new file +10 -0
+	/*
+	 * Run cable disgnostics
+	 */
+	printf("Running cable diagnostic test...");
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
+	miiphy_write(devname, addr, 21, PHY_DIAG_START);
+	miiphy_read(devname, addr, 21, &data);
+	while ((data & PHY_DIAG_BUSY) == PHY_DIAG_BUSY) {
+		miiphy_read(devname, addr, 21, &data);
+		mdelay(1);

Unbounded loop, do I need to say more ? ;-)

Quoted 2 lines
(quoted diff) +2 -0
+	}
+	printf("done!\n");

[...]

include/configs/socfpga_sr1500.h

Quoted 4 lines
include/configs/socfpga_sr1500.h new file +4 -0
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyS0"

__stringify(CONFIG_BAUDRATE)

Quoted 1 line

+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

Do you really need socfpga_vt on your quite certainly physical hardware ?

include/configs/socfpga_sr1500.h

Quoted 7 lines
include/configs/socfpga_sr1500.h new file +7 -0
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR		0x8000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup

*/

include/configs/socfpga_sr1500.h line 56

Quoted 4 lines
include/configs/socfpga_sr1500.h new file +4 -0
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC1_ADDRESS

This EMAC address is certainly not needed now, it should come from OF.

Quoted 33 lines
include/configs/socfpga_sr1500.h new file +33 -0
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+/* The PHY is autodetected, so no MII PHY address is needed here */
+#define CONFIG_PHY_MARVELL
+#define PHY_ANEG_TIMEOUT	8000
+#endif
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME		sr1500
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* Environment */

include/configs/socfpga_sr1500.h line 99

Quoted 10 lines
include/configs/socfpga_sr1500.h new file +10 -0
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* Enable SPI NOR flash reset, needed for SPI booting */
+#define CONFIG_SPI_N25Q256A_RESET
+
+/* Environment setting for SPI flash */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_OFFSET	(0x00040000)

Parenthesis not needed.

Quoted 6 lines

+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET +
CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SPI_BUS 0

include/configs/socfpga_sr1500.h new file +4 -0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_3
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+

include/configs/socfpga_sr1500.h line 115

Quoted 10 lines
include/configs/socfpga_sr1500.h new file +10 -0
+/* U-Boot payload is stored at offset 0x60000 */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x60000
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE

It might be better to use some scratch registers for this, no ? Especially since you can get SRAM corruption if you fiddle with SRAM ECC configuration.

Quoted 4 lines
include/configs/socfpga_sr1500.h new file +4 -0
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_SR1500_H__ */
author
#5 lore raw

PATCH 1/1 arm: socfpga: Add SoCFPGA SR1500 board

Hi Marek,

Quoted 4 lines · Marek Vasut
Quoted 1 line · Stefan Roese

The SR1500

Does SR mean Stefan Roese ? :-)

Not really. I had no influence on this board naming. But I really like it! ;)

Quoted 2 lines

Anyway, shouldn't you place this device under board/vendorname/boardname instead of plain board/boardname/ ?

Placing the board directly in the "board" directory is common practise for boards without a vendor (or where the vendor doesn't want to be listed).

Quoted 3 lines

And one more thing, would it be possible for you to do a short README on adding a new board? That'd be real cool. Obviously, it's not something I demand or that'd block this patch series, it'd be nice though.

Let me see, if I can cook something up here quickly.

Quoted 14 lines
Quoted 11 lines

board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

[...]

Quoted 16 lines

board/sr1500/socfpga.c line 40

Quoted 12 lines
board/sr1500/socfpga.c new file +12 -0
+int board_early_init_f(void)
+{
+	int ret;
+
+	/* Reset the Marvell PHY 88E1510 */
+	ret = gpio_request(63, "PHY reset");
+	if (ret)
+		return ret;
+
+	gpio_direction_output(63, 0);
+	mdelay(20);
+	gpio_set_value(63, 1);

Does the PHY come out of reset immediatelly after you deassert the nRESET GPIO or not ? You might want to add a small delay here to bullet-proof the code a bit more.

Yes, makes sense. I'll re-tune this in v2.

Quoted 13 lines
Quoted 13 lines
board/sr1500/socfpga.c new file +6 -0
+	return 0;
+}
+
+#define CONFIG_SYS_IDT_CLK_ADDR		0x6a
+
+static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c new file +6 -0
+	u8 buf[1];
+
+	buf[0] = 0x01;
+	i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
+
+	return 0;
Quoted 8 lines

board/sr1500/socfpga.c line 58

Quoted 4 lines
board/sr1500/socfpga.c new file +4 -0
+}
+
+U_BOOT_CMD(clksave, 1, 0, do_clksave,
+	   "IDT 5V49EE702 Progsave command", "");

I am not convinced I should let this slide. Wouldn't it be better to just have an environment script which sends 0x1 to this IDT Versaclock using the i2c command ?

This code is already pretty old. And was written in some board bringup session quite hastily. This explains the quite poor quality. Sorry, I should I have spent a bit time on the cleanup here - totally forgot about that.

But this command is now part of the manufacturing process. So I would really like to keep it.

Quoted 24 lines

board/sr1500/socfpga.c line 65

Quoted 6 lines
board/sr1500/socfpga.c new file +6 -0
+#define NET_DEV_NAME			"ethernet at ff702000"
+#define MII_MARVELL_PHY_PAGE		22
+#define PHY_DIAG_START			(1 << 15)
+#define PHY_DIAG_BUSY			(1 << 11)
+
+static char str[16];

Please move this static var into do_phytest() and pass it into pair_state() as an argument.

Quoted 14 lines
board/sr1500/socfpga.c new file +14 -0
+static char *pair_state(int val)
+{
+	switch (val) {
+	case 0x00:
+		strcpy(str, "Invalid");
+		break;
+	case 0x01:
+		strcpy(str, "Pair Ok");
+		break;
+	case 0x02:
+		strcpy(str, "Pair Open");
+		break;
+	case 0x03:
+		strcpy(str, "Same Pair Short");
Quoted 8 lines

board/sr1500/socfpga.c line 83

Quoted 3 lines
board/sr1500/socfpga.c new file +3 -0
+		break;
+	case 0x04:
+		strcpy(str, "Cross Pair Short");

Do I count correctly that you do strcpy() here on a string which is 16 byte long + one trailing '\0' (total 17 bytes) and you strcpy() it into 16 byte long buffer ? Well that's not good, this will overwrite one byte past the $str buffer with '\0' :-)

Good catch. Thx.

Quoted 34 lines
Quoted 14 lines
board/sr1500/socfpga.c new file +13 -0
+		break;
+	case 0x09:
+		strcpy(str, "Pair Busy");
+		break;
+	default:
+		strcpy(str, "Reserved");
+		break;
+	};
+
+	return str;
+}
+
+static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c line 98

Quoted 1 line
board/sr1500/socfpga.c new file +1 -0
+	char devname[] = NET_DEV_NAME;

const char * here ?

board/sr1500/socfpga.c line 99

Quoted 1 line
board/sr1500/socfpga.c new file +1 -0
+	int addr = 0;

Looks like unsigned value to me, please make it so.

Quoted 12 lines
board/sr1500/socfpga.c new file +12 -0
+	u16 data;
+	u16 status;
+	u16 oldpage;
+	int i;
+
+	/* Save current page register */
+	miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
+
+	/*
+	 * Run cable disgnostics
+	 */
+	printf("Running cable diagnostic test...");
Quoted 8 lines

board/sr1500/socfpga.c line 117

Quoted 6 lines
board/sr1500/socfpga.c new file +6 -0
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
+	miiphy_write(devname, addr, 21, PHY_DIAG_START);
+	miiphy_read(devname, addr, 21, &data);
+	while ((data & PHY_DIAG_BUSY) == PHY_DIAG_BUSY) {
+		miiphy_read(devname, addr, 21, &data);
+		mdelay(1);

Unbounded loop, do I need to say more ? ;-)

No.

Quoted 87 lines
Quoted 2 lines
(quoted diff) +2 -0
+	}
+	printf("done!\n");

[...]

include/configs/socfpga_sr1500.h

Quoted 4 lines
include/configs/socfpga_sr1500.h new file +4 -0
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyS0"

__stringify(CONFIG_BAUDRATE)

Quoted 1 line

+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

Do you really need socfpga_vt on your quite certainly physical hardware ?

include/configs/socfpga_sr1500.h

Quoted 7 lines
include/configs/socfpga_sr1500.h new file +7 -0
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR		0x8000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup

*/

include/configs/socfpga_sr1500.h line 56

Quoted 4 lines
include/configs/socfpga_sr1500.h new file +4 -0
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC1_ADDRESS

This EMAC address is certainly not needed now, it should come from OF.

Quoted 33 lines
include/configs/socfpga_sr1500.h new file +33 -0
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+/* The PHY is autodetected, so no MII PHY address is needed here */
+#define CONFIG_PHY_MARVELL
+#define PHY_ANEG_TIMEOUT	8000
+#endif
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME		sr1500
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* Environment */

include/configs/socfpga_sr1500.h line 99

Quoted 10 lines
include/configs/socfpga_sr1500.h new file +10 -0
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* Enable SPI NOR flash reset, needed for SPI booting */
+#define CONFIG_SPI_N25Q256A_RESET
+
+/* Environment setting for SPI flash */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_OFFSET	(0x00040000)

Parenthesis not needed.

Quoted 12 lines

+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET +
CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SPI_BUS 0

include/configs/socfpga_sr1500.h new file +10 -0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_3
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+
+/* U-Boot payload is stored at offset 0x60000 */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x60000
+
+/*
+ * Bootcounter
+ */
Quoted 8 lines

include/configs/socfpga_sr1500.h line 115

Quoted 4 lines
include/configs/socfpga_sr1500.h new file +4 -0
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE

It might be better to use some scratch registers for this, no ? Especially since you can get SRAM corruption if you fiddle with SRAM ECC configuration.

While adding this bootcounter support for this board a few months ago I could not come up with any scratch registers for this quickly. Internal SRAM is often used for this feature, so I used it. And it works just fine. I would really like to keep it this way, especially since the board is already in production and also using this location in the Linux version of this bootcounter driver.

Thanks for the review.

Thanks,
Stefan

#6 lore raw

PATCH 1/1 arm: socfpga: Add SoCFPGA SR1500 board

Quoted 1 line · Stefan Roese

Hi Marek,

Hi,

Quoted 9 lines · Marek Vasut
Quoted 4 lines · Stefan Roese
Quoted 1 line

The SR1500

Does SR mean Stefan Roese ? :-)

Not really. I had no influence on this board naming. But I really like it! ;)

Quoted 6 lines
Quoted 2 lines

Anyway, shouldn't you place this device under board/vendorname/boardname instead of plain board/boardname/ ?

Placing the board directly in the "board" directory is common practise for boards without a vendor (or where the vendor doesn't want to be listed).

Maybe we should place those boards under board/johndoe/ or something then ? There is way too many boards in boards/ I think. But either way, I won't oppose to keeping it just under boards/ either.

Quoted 5 lines
Quoted 3 lines

And one more thing, would it be possible for you to do a short README on adding a new board? That'd be real cool. Obviously, it's not something I demand or that'd block this patch series, it'd be nice though.

Let me see, if I can cook something up here quickly.

Sure, thanks!

Quoted 31 lines
Quoted 14 lines
Quoted 11 lines

board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

[...]

Quoted 16 lines

board/sr1500/socfpga.c line 40

Quoted 12 lines
board/sr1500/socfpga.c new file +12 -0
+int board_early_init_f(void)
+{
+	int ret;
+
+	/* Reset the Marvell PHY 88E1510 */
+	ret = gpio_request(63, "PHY reset");
+	if (ret)
+		return ret;
+
+	gpio_direction_output(63, 0);
+	mdelay(20);
+	gpio_set_value(63, 1);

Does the PHY come out of reset immediatelly after you deassert the nRESET GPIO or not ? You might want to add a small delay here to bullet-proof the code a bit more.

Quoted 1 line

Yes, makes sense. I'll re-tune this in v2.

OK

Quoted 22 lines
Quoted 13 lines
Quoted 13 lines
board/sr1500/socfpga.c new file +6 -0
+	return 0;
+}
+
+#define CONFIG_SYS_IDT_CLK_ADDR		0x6a
+
+static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c new file +6 -0
+	u8 buf[1];
+
+	buf[0] = 0x01;
+	i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
+
+	return 0;
Quoted 8 lines

board/sr1500/socfpga.c line 58

Quoted 4 lines
board/sr1500/socfpga.c new file +4 -0
+}
+
+U_BOOT_CMD(clksave, 1, 0, do_clksave,
+	   "IDT 5V49EE702 Progsave command", "");

I am not convinced I should let this slide. Wouldn't it be better to just have an environment script which sends 0x1 to this IDT Versaclock using the i2c command ?

Quoted 7 lines

This code is already pretty old. And was written in some board bringup session quite hastily. This explains the quite poor quality. Sorry, I should I have spent a bit time on the cleanup here - totally forgot about that.

But this command is now part of the manufacturing process. So I would really like to keep it.

Argh, I absolutelly don't like this. Also, I don't like the reasoning, it looks vaguely similar to certain other "system", where a certain group got a certain feature widely used and then "forced" patches mainline just because that feature is in use by many by now.

Maybe you can at least pull these hacks into some compat.c file with a big warning somewhere in there that this is certainly NOT how things were supposed to be done ?

[...]

Quoted 12 lines
Quoted 11 lines

include/configs/socfpga_sr1500.h line 115

Quoted 7 lines
include/configs/socfpga_sr1500.h new file +7 -0
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE

It might be better to use some scratch registers for this, no ? Especially since you can get SRAM corruption if you fiddle with SRAM ECC configuration.

Quoted 6 lines

While adding this bootcounter support for this board a few months ago I could not come up with any scratch registers for this quickly. Internal SRAM is often used for this feature, so I used it. And it works just fine. I would really like to keep it this way, especially since the board is already in production and also using this location in the Linux version of this bootcounter driver.

OK, no problem with this. Just keep the ECC part in mind.

author
#7 lore raw

PATCH v2 1/1 arm: socfpga: Add SoCFPGA SR1500 board

In reply to Stefan Roese

The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

---
v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile                    |   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
 arch/arm/mach-socfpga/Kconfig            |   6 +
 board/sr1500/MAINTAINERS                 |   6 +
 board/sr1500/Makefile                    |   7 +
 board/sr1500/qts/iocsr_config.h          | 660 +++++++++++++++++++++++++++++++
 board/sr1500/qts/pinmux_config.h         | 219 ++++++++++
 board/sr1500/qts/pll_config.h            |  85 ++++
 board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
 board/sr1500/socfpga.c                   | 151 +++++++
 configs/socfpga_sr1500_defconfig         |  17 +
 doc/README.socfpga                       |  74 +++-
 include/configs/socfpga_sr1500.h         | 113 ++++++
 13 files changed, 1782 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h
arch/arm/dts/Makefile +3 -1
index ddc6a05..b77aab48 100644
@@ -74,7 +74,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
-	socfpga_cyclone5_socrates.dtb
+	socfpga_cyclone5_socrates.dtb			\
+	socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +101 -0

101 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +6 -0
index a413ea4..aa12df2 100644
@@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -38,6 +42,7 @@ config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "sr1500" if TARGET_SOCFPGA_SR1500
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK

@@ -55,5 +60,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 
 endif
board/sr1500/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..ed013a8
@@ -0,0 +1,6 @@
+SOCFPGA SR1500 BOARD
+M:	Stefan Roese <[email protected]>
+S:	Maintained
+F:	board/sr1500/
+F:	include/configs/socfpga_sr1500.h
+F:	configs/socfpga_sr1500_defconfig
board/sr1500/Makefile new file +7 -0
new file mode 100644
index 0000000..eae7ad0
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
board/sr1500/qts/iocsr_config.h new file +660 -0

660 lines not on this page · raw message

board/sr1500/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/sr1500/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/sr1500/qts/sdram_config.h new file +341 -0

341 lines not on this page · raw message

board/sr1500/socfpga.c new file +151 -0

151 lines not on this page · raw message

configs/socfpga_sr1500_defconfig new file +17 -0
new file mode 100644
index 0000000..11dea35
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
doc/README.socfpga +73 -1

83 lines not on this page · raw message

include/configs/socfpga_sr1500.h new file +113 -0

113 lines not on this page · raw message

Signature · 1 line
2.6.2
#8 lore raw

PATCH v2 1/1 arm: socfpga: Add SoCFPGA SR1500 board

Hi Stefan,

Quoted 88 lines · Stefan Roese

The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

---
v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile                    |   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
 arch/arm/mach-socfpga/Kconfig            |   6 +
 board/sr1500/MAINTAINERS                 |   6 +
 board/sr1500/Makefile                    |   7 +
 board/sr1500/qts/iocsr_config.h          | 660 +++++++++++++++++++++++++++++++
 board/sr1500/qts/pinmux_config.h         | 219 ++++++++++
 board/sr1500/qts/pll_config.h            |  85 ++++
 board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
 board/sr1500/socfpga.c                   | 151 +++++++
 configs/socfpga_sr1500_defconfig         |  17 +
 doc/README.socfpga                       |  74 +++-
 include/configs/socfpga_sr1500.h         | 113 ++++++
 13 files changed, 1782 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h
include/configs/socfpga_sr1500.h new file +36 -0
new file mode 100644
index 0000000..def01fb
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_SR1500_H__
+#define __CONFIG_SOCFPGA_SR1500_H__
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+
+#define CONFIG_HW_WATCHDOG
+
+/* U-Boot Commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TIME

include/configs/socfpga_sr1500.h line 46

Quoted 10 lines
include/configs/socfpga_sr1500.h new file +10 -0
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
+#define CONFIG_LOADADDR		0x8000

All of the other boards have switched to use 0x01000000 as the LOADADDR.

Dinh

#9 lore raw

PATCH v2 1/1 arm: socfpga: Add SoCFPGA SR1500 board

In reply to Stefan Roese

On Monday, October 26, 2015 at 09:36:51 AM, Stefan Roese wrote:

Hi!

[...]

Quoted 55 lines
board/sr1500/socfpga.c new file +48 -0
new file mode 100644
index 0000000..35d68a9
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	int ret;
+
+	/* Reset the Marvell PHY 88E1510 */
+	ret = gpio_request(63, "PHY reset");
+	if (ret)
+		return ret;
+
+	gpio_direction_output(63, 0);
+	mdelay(10);
+	gpio_set_value(63, 1);
+	mdelay(10);
+
+	return 0;
+}
+
+#define CONFIG_SYS_IDT_CLK_ADDR		0x6a
+
+static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c line 50

Quoted 1 line
board/sr1500/socfpga.c new file +1 -0
+	u8 buf[1];

u8 buf = 0x1;

i2c_write(....., &buf, 1);

this would work too.

board/sr1500/socfpga.c line 59

Quoted 8 lines
board/sr1500/socfpga.c new file +8 -0
+	buf[0] = 0x01;
+	i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
+
+	return 0;
+}
+
+U_BOOT_CMD(clksave, 1, 0, do_clksave,
+	   "IDT 5V49EE702 Progsave command", "");

Every time you do this in a board file, a kitten dies :-(

[...]

Quoted 14 lines

+static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{

board/sr1500/socfpga.c new file +12 -0
+	const char devname[] = NET_DEV_NAME;
+	unsigned long ts;
+	char str[32];
+	u8 addr = 0;
+	u16 data;
+	u16 status;
+	u16 oldpage;
+	int i;
+
+	/* Save current page register */
+	miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
+

board/sr1500/socfpga.c line 119

Quoted 10 lines
board/sr1500/socfpga.c new file +10 -0
+	/*
+	 * Run cable disgnostics
+	 */
+	printf("Running cable diagnostic test...");
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
+	miiphy_write(devname, addr, 21, PHY_DIAG_START);
+
+	ts = get_timer(0);
+	do {
+		miiphy_read(devname, addr, 21, &data);

miiphy_read() can also return an error code I think, in which case $data would be invalid. Right ?

Quoted 22 lines
board/sr1500/socfpga.c new file +22 -0
+		if ((data & PHY_DIAG_BUSY) != PHY_DIAG_BUSY)
+			break;
+
+		mdelay(1);
+	} while (get_timer(ts) < PHY_DIAG_TIMEOUT);
+	printf("done!\n");
+
+	miiphy_read(devname, addr, 20, &status);
+
+	for (i = 0; i < 4; i++) {
+		int val;
+
+		val = (status >> (i * 4)) & 0x000f;
+		pair_state(val, str);
+		printf("Pair %d: %s", i, str);
+
+		/* Only print fault length if not okay */
+		if (val != 0x01) {
+			miiphy_read(devname, addr, 16 + i, &data);
+			printf(" - Length to fault %d cm", data);
+		}
+		printf("\n");

board/sr1500/socfpga.c line 151

Quoted 10 lines
board/sr1500/socfpga.c new file +10 -0
+	}
+
+	/* Restore original page */
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, oldpage);
+
+	return 0;
+}
+
+U_BOOT_CMD(phytest, 1, 1, do_phytest,
+	   "Marvell PHY test command - dump some values", "");

And yet another kitten down ;-)

[...]

doc/README.socfpga

Quoted 1 line
doc/README.socfpga +0 -0

Please , put this README into a separate patch :-(

Quoted 15 lines

index cfcbbfe..eebf373 100644

doc/README.socfpga +0 -0
@@ -7,7 +7,6 @@ This README is about U-Boot and SPL support for Altera's
 ARM Cortex-A9MPCore based SOCFPGA. To know more about the hardware itself,

please refer to www.altera.com.

doc/README.socfpga +0 -1
-
 --------------------------------------------
 socfpga_dw_mmc
 --------------------------------------------

@@ -51,3 +50,76 @@ the card
 #define CONFIG_SOCFPGA_DWMMC_BUS_HZ	50000000
 -> The clock rate to controller. Do note the controller have a wrapper

which divide the clock from PLL by 4.

doc/README.socfpga the card · line 60

Quoted 8 lines
doc/README.socfpga +8 -0
+
+-------------------------------------------------------------------------
+Generating the header files for SPL intergration as a replacement for the
+Preloader
+-------------------------------------------------------------------------
+This text assumes the use of Quartus 14.0.200
+
+I) Rebuilding the MCVEVK Quartus project

This is not MCV-specific ;-)

doc/README.socfpga

Quoted 10 lines

+----------------------------------------
+ 1) Navigate to DENX_MCV_reference_* directory
+ 2) Run Quartus II
+ 3) Open Project (Ctrl+J), select DENX_MCV_reference.qpf
+ 4) Run QSys [Tools->QSys]

doc/README.socfpga +2 -0
+    4.1) In the Open dialog, select 'mcv_hps.qsys'
+    4.2) In the Open System dialog, wait until completion and press

'Close' + 4.3) In the Qsys window, click on 'Generate HDL...' in bottom
right corner + 4.3.1) In the 'Generation' window, click 'Generate'

doc/README.socfpga +1 -0
+	 4.3.2) In the 'Generate' dialog, wait until completion and click

'Close'

doc/README.socfpga the card · line 81

Quoted 11 lines
doc/README.socfpga +11 -0
+    4.4) In the QSys window, click 'Finish'
+         4.4.1) In the 'Quartus II' pop up window, click 'OK'
+ 5) Back in Quartus II main window, do the following
+    5.1) Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
+    5.2) Use Processing -> Start Compilation (Ctrl+L)
+    ... have lunch, coffee, play games ...
+
+ [
+   NOTE: Steps 2-5 above can be also done using a convenience scripts
+         from the command line:
+	 $ ./qsys.sh && ./anal.sh && ./build.sh

This is definitelly NOT standard . Please drop this NOTE altogether.

You can use something like the following to compile the quartus project, which is standard way to do it (that replaces that anal.sh and build.sh scripts):

$ quartus_sh --flow compile <project>

To generate the qsys system (replacement for qsys.sh), hrm, I guess you should use "ip-generate", but that takes many options. Dinh, is there some magic invocation for ip-generate which takes the qsys file and generates the system ?

doc/README.socfpga the card · line 87

Quoted 6 lines

+ ]

doc/README.socfpga +5 -0
+
+ 6) Launch a separate terminal window
+    6.1) Change directory to 'software/spl_bsp'
+    6.2) Export path to embedded command shell and friends
+         $ export PATH=/work/DENX/Altera/Quartus/14.0/embedded/:$PATH

14.0 should be replaced by 15.0 ;-)

Quoted 25 lines
doc/README.socfpga +25 -0
+    6.3) Start embedded command shell (ECS)
+         $ embedded_command_shell.sh
+    6.4) Prepare BSP by launching the BSP editor from ECS
+         => bsp-editor
+    6.5) In BSP editor
+         6.5.1) Use File -> Open
+	 6.5.2) Select 'settings.bsp' file
+	 6.5.4) Click Generate
+	 6.5.5) Click Exit
+
+Now the necessary files are generated. And U-Boot can be used
+to generate the SPL header files. For this, please use the
+following script:
+
+./arch/arm/mach-socfpga/qts-filter.sh cyclone5 \
+	/path/to/quartus/project /path/to/output/qts/
+
+This will generate the following 4 files:
+
+iocsr_config.h
+pinmux_config.h
+pll_config.h
+sdram_config.h
+
+These files need to be copied into "qts" directory in the board

doc/README.socfpga the card · line 122

Quoted 10 lines
doc/README.socfpga +10 -0
+directory. Here the example for the DENX MCVEVK:
+
+$ ll board/denx/mcvevk/qts/
+total 44
+drwxrwxr-x 2 stefan stefan 4096 Okt 20 07:07 ./
+drwxrwxr-x 3 stefan stefan 4096 Okt 21 13:06 ../
+-rw-rw-r-- 1 stefan stefan 8826 Okt 20 07:07 iocsr_config.h
+-rw-rw-r-- 1 stefan stefan 4398 Okt 20 07:07 pinmux_config.h
+-rw-rw-r-- 1 stefan stefan 3192 Okt 20 07:07 pll_config.h
+-rw-rw-r-- 1 stefan stefan 9031 Okt 20 07:07 sdram_config.h

Oct please ;-)

doc/README.socfpga the card · line 125

Quoted 2 lines
doc/README.socfpga +2 -0
+Now you board is ready for full mainline support including
+U-Boot SPL. The Preloader will not be needed any more.

... is not needed ...

[...]

author
#10 lore raw

PATCH v3 1/1 arm: socfpga: Add SoCFPGA SR1500 board

In reply to Stefan Roese

The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

---
v3:
- Removed README.socfpga changes
- Removed board specific commands
- Change CONFIG_LOADADDR to 0x01000000 as suggested by Dinh

v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile                    |   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
 arch/arm/mach-socfpga/Kconfig            |   6 +
 board/sr1500/MAINTAINERS                 |   6 +
 board/sr1500/Makefile                    |   7 +
 board/sr1500/qts/iocsr_config.h          | 660 +++++++++++++++++++++++++++++++
 board/sr1500/qts/pinmux_config.h         | 219 ++++++++++
 board/sr1500/qts/pll_config.h            |  85 ++++
 board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
 board/sr1500/socfpga.c                   | 151 +++++++
 configs/socfpga_sr1500_defconfig         |  17 +
 include/configs/socfpga_sr1500.h         | 113 ++++++
 12 files changed, 1709 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h
arch/arm/dts/Makefile +3 -1
index ddc6a05..b77aab48 100644
@@ -74,7 +74,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
-	socfpga_cyclone5_socrates.dtb
+	socfpga_cyclone5_socrates.dtb			\
+	socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +101 -0

101 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +6 -0
index a413ea4..aa12df2 100644
@@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -38,6 +42,7 @@ config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "sr1500" if TARGET_SOCFPGA_SR1500
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK

@@ -55,5 +60,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 
 endif
board/sr1500/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..ed013a8
@@ -0,0 +1,6 @@
+SOCFPGA SR1500 BOARD
+M:	Stefan Roese <[email protected]>
+S:	Maintained
+F:	board/sr1500/
+F:	include/configs/socfpga_sr1500.h
+F:	configs/socfpga_sr1500_defconfig
board/sr1500/Makefile new file +7 -0
new file mode 100644
index 0000000..eae7ad0
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
board/sr1500/qts/iocsr_config.h new file +660 -0

660 lines not on this page · raw message

board/sr1500/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/sr1500/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/sr1500/qts/sdram_config.h new file +341 -0

341 lines not on this page · raw message

board/sr1500/socfpga.c new file +151 -0

151 lines not on this page · raw message

configs/socfpga_sr1500_defconfig new file +17 -0
new file mode 100644
index 0000000..11dea35
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
include/configs/socfpga_sr1500.h new file +113 -0

113 lines not on this page · raw message

Signature · 1 line
2.6.2
#11 lore raw

PATCH v3 1/1 arm: socfpga: Add SoCFPGA SR1500 board

Quoted 7 lines · Stefan Roese

The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Quoted 8 lines
Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

---
v3:
- Removed README.socfpga changes
- Removed board specific commands

Really ? ;-)

Quoted 140 lines

- Change CONFIG_LOADADDR to 0x01000000 as suggested by Dinh

v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile                    |   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
 arch/arm/mach-socfpga/Kconfig            |   6 +
 board/sr1500/MAINTAINERS                 |   6 +
 board/sr1500/Makefile                    |   7 +
 board/sr1500/qts/iocsr_config.h          | 660
+++++++++++++++++++++++++++++++ board/sr1500/qts/pinmux_config.h         |
219 ++++++++++
 board/sr1500/qts/pll_config.h            |  85 ++++
 board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
 board/sr1500/socfpga.c                   | 151 +++++++
 configs/socfpga_sr1500_defconfig         |  17 +
 include/configs/socfpga_sr1500.h         | 113 ++++++
 12 files changed, 1709 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h
arch/arm/dts/Makefile +3 -1
index ddc6a05..b77aab48 100644
@@ -74,7 +74,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
-	socfpga_cyclone5_socrates.dtb
+	socfpga_cyclone5_socrates.dtb			\
+	socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_cyclone5_sr1500.dts new file mode 100644 index 0000000..3729ca0

arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +11 -0
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "SoCFPGA Cyclone V SR1500";
+	compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5",

"altr,socfpga"; +

arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +73 -0
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		/*
+		 * This allows the ethaddr uboot environmnet variable
+		 * contents to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
+	memory at 0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	speed-mode = <0>;
+};
+
+&i2c1 {
+	status = "okay";
+	speed-mode = <0>;
+};
+
+&mmc0 {
+	status = "okay";
+	bus-width = <8>;
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	flash0: n25q00 at 0 {

arch/arm/dts/socfpga_cyclone5_sr1500.dts

Quoted 10 lines
arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +10 -0
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00", "spi-flash";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register

*/

Quoted 6 lines
arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +6 -0
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};

[...]

Quoted 157 lines
board/sr1500/socfpga.c new file +48 -0
new file mode 100644
index 0000000..35d68a9
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	int ret;
+
+	/* Reset the Marvell PHY 88E1510 */
+	ret = gpio_request(63, "PHY reset");
+	if (ret)
+		return ret;
+
+	gpio_direction_output(63, 0);
+	mdelay(10);
+	gpio_set_value(63, 1);
+	mdelay(10);
+
+	return 0;
+}
+
+#define CONFIG_SYS_IDT_CLK_ADDR		0x6a
+
+static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c new file +47 -0
+	u8 buf[1];
+
+	buf[0] = 0x01;
+	i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
+
+	return 0;
+}
+
+U_BOOT_CMD(clksave, 1, 0, do_clksave,
+	   "IDT 5V49EE702 Progsave command", "");
+
+#define NET_DEV_NAME			"ethernet at ff702000"
+#define MII_MARVELL_PHY_PAGE		22
+#define PHY_DIAG_START			(1 << 15)
+#define PHY_DIAG_BUSY			(1 << 11)
+#define PHY_DIAG_TIMEOUT		5000	/* 5 seconds */
+
+static char *pair_state(int val, char *str)
+{
+	switch (val) {
+	case 0x00:
+		strcpy(str, "Invalid");
+		break;
+	case 0x01:
+		strcpy(str, "Pair Ok");
+		break;
+	case 0x02:
+		strcpy(str, "Pair Open");
+		break;
+	case 0x03:
+		strcpy(str, "Same Pair Short");
+		break;
+	case 0x04:
+		strcpy(str, "Cross Pair Short");
+		break;
+	case 0x09:
+		strcpy(str, "Pair Busy");
+		break;
+	default:
+		strcpy(str, "Reserved");
+		break;
+	};
+
+	return str;
+}
+
+static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const

argv[]) +{

board/sr1500/socfpga.c new file +54 -0
+	const char devname[] = NET_DEV_NAME;
+	unsigned long ts;
+	char str[32];
+	u8 addr = 0;
+	u16 data;
+	u16 status;
+	u16 oldpage;
+	int i;
+
+	/* Save current page register */
+	miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
+
+	/*
+	 * Run cable disgnostics
+	 */
+	printf("Running cable diagnostic test...");
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
+	miiphy_write(devname, addr, 21, PHY_DIAG_START);
+
+	ts = get_timer(0);
+	do {
+		miiphy_read(devname, addr, 21, &data);
+		if ((data & PHY_DIAG_BUSY) != PHY_DIAG_BUSY)
+			break;
+
+		mdelay(1);
+	} while (get_timer(ts) < PHY_DIAG_TIMEOUT);
+	printf("done!\n");
+
+	miiphy_read(devname, addr, 20, &status);
+
+	for (i = 0; i < 4; i++) {
+		int val;
+
+		val = (status >> (i * 4)) & 0x000f;
+		pair_state(val, str);
+		printf("Pair %d: %s", i, str);
+
+		/* Only print fault length if not okay */
+		if (val != 0x01) {
+			miiphy_read(devname, addr, 16 + i, &data);
+			printf(" - Length to fault %d cm", data);
+		}
+		printf("\n");
+	}
+
+	/* Restore original page */
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, oldpage);
+
+	return 0;
+}
+
+U_BOOT_CMD(phytest, 1, 1, do_phytest,
+	   "Marvell PHY test command - dump some values", "");

[...]

Reviewed-by Marek Vasut <[email protected]>
author
#12 lore raw

PATCH v4 1/1 arm: socfpga: Add SoCFPGA SR1500 board

In reply to Stefan Roese

The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Reviewed-by Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Dinh Nguyen <[email protected]>

---
v4:
- Really remove board specific commands

v3:
- Removed README.socfpga changes
- Removed board specific commands
- Change CONFIG_LOADADDR to 0x01000000 as suggested by Dinh

v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile                    |   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
 arch/arm/mach-socfpga/Kconfig            |   6 +
 board/sr1500/MAINTAINERS                 |   6 +
 board/sr1500/Makefile                    |   7 +
 board/sr1500/qts/iocsr_config.h          | 660 +++++++++++++++++++++++++++++++
 board/sr1500/qts/pinmux_config.h         | 219 ++++++++++
 board/sr1500/qts/pll_config.h            |  85 ++++
 board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
 board/sr1500/socfpga.c                   |  44 +++
 configs/socfpga_sr1500_defconfig         |  17 +
 include/configs/socfpga_sr1500.h         | 113 ++++++
 12 files changed, 1602 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h
arch/arm/dts/Makefile +3 -1
index 9542fff..82d68ce 100644
@@ -80,7 +80,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
-	socfpga_cyclone5_socrates.dtb
+	socfpga_cyclone5_socrates.dtb			\
+	socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
arch/arm/dts/socfpga_cyclone5_sr1500.dts new file +101 -0

101 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +6 -0
index a413ea4..aa12df2 100644
@@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -38,6 +42,7 @@ config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "sr1500" if TARGET_SOCFPGA_SR1500
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK

@@ -55,5 +60,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 
 endif
board/sr1500/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..ed013a8
@@ -0,0 +1,6 @@
+SOCFPGA SR1500 BOARD
+M:	Stefan Roese <[email protected]>
+S:	Maintained
+F:	board/sr1500/
+F:	include/configs/socfpga_sr1500.h
+F:	configs/socfpga_sr1500_defconfig
board/sr1500/Makefile new file +7 -0
new file mode 100644
index 0000000..eae7ad0
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
board/sr1500/qts/iocsr_config.h new file +660 -0

660 lines not on this page · raw message

board/sr1500/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/sr1500/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/sr1500/qts/sdram_config.h new file +341 -0

341 lines not on this page · raw message

board/sr1500/socfpga.c new file +44 -0

44 lines not on this page · raw message

configs/socfpga_sr1500_defconfig new file +17 -0
new file mode 100644
index 0000000..11dea35
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
include/configs/socfpga_sr1500.h new file +113 -0

113 lines not on this page · raw message

Signature · 1 line
2.6.3
#13 lore raw

PATCH v4 1/1 arm: socfpga: Add SoCFPGA SR1500 board

Quoted 9 lines · Stefan Roese

The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by Stefan Roese <[email protected]>
Reviewed-by Marek Vasut <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html