imx6-mmdc: fix automatic power down enable in write level calibration
Subsystems (3)
PATCH 1/1 imx6-mmdc: fix automatic power down enable in write level calibration
Bit 0 of the MAPSR register controls auto power down.
Explicitly clear this bit instead of reserved bit when exiting from mmdc_do_write_level_calibration().
--- arch/arm/mach-imx/imx6-mmdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-imx/imx6-mmdc.c +2 -2
@@ -103,9 +103,9 @@ int mmdc_do_write_level_calibration(void) val |=0x00005500 ;writel (val, (P0_IPS +MDPDC )); -/* enable Adopt power down timer: */ +/* enable auto power down timer: */ val =readl (P0_IPS +MAPSR ); - val &=0xfffffff7 ; + val &= ~1 ;writel (val, (P0_IPS +MAPSR ));/* clear CON_REQ */
Signature · 7 lines
2.6.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Sascha Hauer
maintainerHi Eric,
Quoted 6 lines · Eric Nelson
Bit 0 of the MAPSR register controls auto power down.
Explicitly clear this bit instead of reserved bit when exiting from
mmdc_do_write_level_calibration().Signed-off-by Eric Nelson <[email protected]>
Looks good, applied. Did this bug have any practical impacts?
Sascha
Quoted 24 lines
--- arch/arm/mach-imx/imx6-mmdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm/mach-imx/imx6-mmdc.c +2
-2@@ -103,9 +103,9 @@ int mmdc_do_write_level_calibration(void) val |=0x00005500 ;writel (val, (P0_IPS +MDPDC )); -/* enable Adopt power down timer: */ +/* enable auto power down timer: */ val =readl (P0_IPS +MAPSR ); - val &=0xfffffff7 ; + val &= ~1 ;writel (val, (P0_IPS +MAPSR ));/* clear CON_REQ */ Signature · 1 line
2.6.2
Signature · 9 lines
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Hi Sascha,
Quoted 12 lines · Sascha Hauer
Hi Eric,
Quoted 6 lines · Eric Nelson
Bit 0 of the MAPSR register controls auto power down.
Explicitly clear this bit instead of reserved bit when exiting from
mmdc_do_write_level_calibration().Signed-off-by Eric Nelson <[email protected]>Looks good, applied. Did this bug have any practical impacts?
I found the mistake when reviewing the code and didn't run it. From the manual, bit 3 is listed as reserved with a default value of zero, so that should have no effect.
Not clearing bit zero should only prevent the MMDC from invoking self-refresh.
From the RM:
Automatic Power Saving Disable. When the value of PSD is "0" (i.e automatic power saving is enabled) then the PST is activated and MMDC will enter automatically to self-refresh while the number of idle cycle reached.
I'm reviewing this code for possible inclusion into a U-Boot SPL-based DDR calibration routine and haven't run it.
Quoted 21 lines
Sascha
Quoted 19 lines
--- arch/arm/mach-imx/imx6-mmdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm/mach-imx/imx6-mmdc.c +2
-2@@ -103,9 +103,9 @@ int mmdc_do_write_level_calibration(void) val |=0x00005500 ;writel (val, (P0_IPS +MDPDC )); -/* enable Adopt power down timer: */ +/* enable auto power down timer: */ val =readl (P0_IPS +MAPSR ); - val &=0xfffffff7 ; + val &= ~1 ;writel (val, (P0_IPS +MAPSR ));
Quoted 6 lines
Quoted 5 lines
arch/arm/mach-imx/imx6-mmdc.c +0
-0/* clear CON_REQ */ Signature · 1 line
2.6.2
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