drm/i915: make A0 wa's applied to A1

PATCH In review [email protected] 4 participants 6 messages Oct 26, 2015 – Nov 2, 2015

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DRM drivers Intel i915

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2015-10-26 10:49 UTC #0 lore raw

PATCH 1/1 drm/i915: make A0 wa's applied to A1

From: Tim Gore <[email protected]>

Since A1 chips use the same GPU as A0, they need all the same wa's in the i915 driver. Update some conditionals to do this.

Signed-off-by Tim Gore <[email protected]>

---
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 drivers/gpu/drm/i915/intel_lrc.c        | 8 ++++----
 drivers/gpu/drm/i915/intel_pm.c         | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

drivers/gpu/drm/i915/intel_guc_loader.c +1 -1

index c0281df..6ec7b23 100644
@@ -309,7 +309,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 
 	/* WaDisableMinuteIaClockGating:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 					      ~GUC_ENABLE_MIA_CLOCK_GATING));
 	}

drivers/gpu/drm/i915/intel_lrc.c +4 -4

index 3265427..971d3f2 100644
@@ -285,7 +285,7 @@ static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
 	struct drm_device *dev = ring->dev;
 
 	return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-		IS_BXT_REVID(dev, 0, BXT_REVID_A0)) &&
+		IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
 	       (ring->id == VCS || ring->id == VCS2);
 }

@@ -1315,7 +1315,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
 
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 
 	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */

@@ -1341,7 +1341,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
 	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
 		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
 		wa_ctx_emit(batch, index,

@@ -1351,7 +1351,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
 
 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

drivers/gpu/drm/i915/intel_pm.c +1 -1

index 0fb0459..911f837 100644
@@ -4691,7 +4691,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
 			"on" : "off");
 	/* WaRsUseTimeoutMode */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
 		I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
 			   GEN7_RC_CTL_TO_MODE |

drivers/gpu/drm/i915/intel_ringbuffer.c +2 -2

index 02a5bb0..368d78b 100644
@@ -1099,11 +1099,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 
 	/* WaStoreMultiplePTEenable:bxt */
 	/* This is a requirement according to Hardware specification */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 
 	/* WaSetClckGatingDisableMedia:bxt */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
 					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
 	}

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Arun Siluvery

Reviewed-by on v1 1/1

2015-10-29 12:35 UTC #1 lore raw

Quoted 72 lines · On 26/10/2015 10:48, [email protected] wrote:

From: Tim Gore <[email protected]>

Since A1 chips use the same GPU as A0, they need all the same wa's in the i915 driver. Update some conditionals to do this.

Signed-off-by Tim Gore <[email protected]>

---
  drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
  drivers/gpu/drm/i915/intel_lrc.c        | 8 ++++----
  drivers/gpu/drm/i915/intel_pm.c         | 2 +-
  drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
  4 files changed, 8 insertions(+), 8 deletions(-)

drivers/gpu/drm/i915/intel_guc_loader.c +1 -1

index c0281df..6ec7b23 100644
@@ -309,7 +309,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 
  	/* WaDisableMinuteIaClockGating:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
  					      ~GUC_ENABLE_MIA_CLOCK_GATING));
  	}

drivers/gpu/drm/i915/intel_lrc.c +4 -4

index 3265427..971d3f2 100644
@@ -285,7 +285,7 @@ static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
  	struct drm_device *dev = ring->dev;
 
  	return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-		IS_BXT_REVID(dev, 0, BXT_REVID_A0)) &&
+		IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
  	       (ring->id == VCS || ring->id == VCS2);
  }

@@ -1315,7 +1315,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
 
  	/* WaDisableCtxRestoreArbitration:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
  		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 
  	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */

@@ -1341,7 +1341,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
  	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
  		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
  		wa_ctx_emit(batch, index,

@@ -1351,7 +1351,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
  	/* WaDisableCtxRestoreArbitration:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
  		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
 
  	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 0fb0459..911f837 100644

drivers/gpu/drm/i915/intel_pm.c static void gen9_enable_rc6(struct drm_device *dev) · line 4692

Quoted 2 lines

drivers/gpu/drm/i915/intel_pm.c +0 -0

@@ -4691,7 +4691,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
  			"on" : "off");
  	/* WaRsUseTimeoutMode */

perhaps you can use this opportunity to add platform label to the WA.

Quoted 15 lines

drivers/gpu/drm/i915/intel_pm.c +1 -1

  	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
  		I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
  			   GEN7_RC_CTL_TO_MODE |

drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0

index 02a5bb0..368d78b 100644
@@ -1099,11 +1099,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 
  	/* WaStoreMultiplePTEenable:bxt */
  	/* This is a requirement according to Hardware specification */

drivers/gpu/drm/i915/intel_ringbuffer.c static int bxt_init_workarounds(struct intel_engine_cs *ring) · line 1109

Quoted 10 lines

drivers/gpu/drm/i915/intel_ringbuffer.c +2 -2

-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
  		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 
  	/* WaSetClckGatingDisableMedia:bxt */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
  					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
  	}

I think in this case single patch for all WA is fine but please check with Daniel whether we need one patch for one WA otherwise it looks good to me.

Reviewed-by Arun Siluvery <[email protected]>

regards
Arun

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

maintainer

2015-10-29 13:42 UTC #2 lore raw

Quoted 105 lines · Arun Siluvery

Quoted 72 lines · On 26/10/2015 10:48, [email protected] wrote:

From: Tim Gore <[email protected]>

Since A1 chips use the same GPU as A0, they need all the same wa's in the i915 driver. Update some conditionals to do this.

Signed-off-by Tim Gore <[email protected]>

---
  drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
  drivers/gpu/drm/i915/intel_lrc.c        | 8 ++++----
  drivers/gpu/drm/i915/intel_pm.c         | 2 +-
  drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
  4 files changed, 8 insertions(+), 8 deletions(-)

drivers/gpu/drm/i915/intel_guc_loader.c +1 -1

index c0281df..6ec7b23 100644
@@ -309,7 +309,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 
  	/* WaDisableMinuteIaClockGating:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
  					      ~GUC_ENABLE_MIA_CLOCK_GATING));
  	}

drivers/gpu/drm/i915/intel_lrc.c +4 -4

index 3265427..971d3f2 100644
@@ -285,7 +285,7 @@ static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
  	struct drm_device *dev = ring->dev;
 
  	return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-		IS_BXT_REVID(dev, 0, BXT_REVID_A0)) &&
+		IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
  	       (ring->id == VCS || ring->id == VCS2);
  }

@@ -1315,7 +1315,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
 
  	/* WaDisableCtxRestoreArbitration:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
  		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 
  	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */

@@ -1341,7 +1341,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
  	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
  		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
  		wa_ctx_emit(batch, index,

@@ -1351,7 +1351,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
  	/* WaDisableCtxRestoreArbitration:skl,bxt */
  	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
  		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
 
  	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 0fb0459..911f837 100644

drivers/gpu/drm/i915/intel_pm.c static void gen9_enable_rc6(struct drm_device *dev) · line 4692

Quoted 2 lines

drivers/gpu/drm/i915/intel_pm.c +0 -0

@@ -4691,7 +4691,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
  			"on" : "off");
  	/* WaRsUseTimeoutMode */

perhaps you can use this opportunity to add platform label to the WA.

Quoted 15 lines

drivers/gpu/drm/i915/intel_pm.c +1 -1

  	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
  		I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
  			   GEN7_RC_CTL_TO_MODE |

drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0

index 02a5bb0..368d78b 100644
@@ -1099,11 +1099,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 
  	/* WaStoreMultiplePTEenable:bxt */
  	/* This is a requirement according to Hardware specification */

drivers/gpu/drm/i915/intel_ringbuffer.c static int bxt_init_workarounds(struct intel_engine_cs *ring) · line 1109

Quoted 10 lines

drivers/gpu/drm/i915/intel_ringbuffer.c +2 -2

-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
  		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 
  	/* WaSetClckGatingDisableMedia:bxt */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
  		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
  					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
  	}

I think in this case single patch for all WA is fine but please check with Daniel whether we need one patch for one WA otherwise it looks good to me.

Quoted 1 line

Reviewed-by Arun Siluvery <[email protected]>

Pushed, thanks for the patch and review.

BR,
Jani.

Quoted 8 lines

regards
Arun
_______________________________________________
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[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 5 lines

Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Daniel Vetter

2015-10-30 16:10 UTC #3 lore raw

In reply to [email protected]

Quoted 5 lines · On Mon, Oct 26, 2015 at 10:48:58AM +0000, [email protected] wrote:

From: Tim Gore <[email protected]>
Since A1 chips use the same GPU as A0, they need all the same wa's in the i915 driver. Update some conditionals to do this.

Neither summary nor commit message mentions that this is for bxt. Please fix.
-Daniel

Quoted 100 lines

Signed-off-by Tim Gore <[email protected]>

---
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 drivers/gpu/drm/i915/intel_lrc.c        | 8 ++++----
 drivers/gpu/drm/i915/intel_pm.c         | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

drivers/gpu/drm/i915/intel_guc_loader.c +1 -1

index c0281df..6ec7b23 100644
@@ -309,7 +309,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 
 	/* WaDisableMinuteIaClockGating:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 					      ~GUC_ENABLE_MIA_CLOCK_GATING));
 	}

drivers/gpu/drm/i915/intel_lrc.c +4 -4

index 3265427..971d3f2 100644
@@ -285,7 +285,7 @@ static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
 	struct drm_device *dev = ring->dev;
 
 	return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-		IS_BXT_REVID(dev, 0, BXT_REVID_A0)) &&
+		IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
 	       (ring->id == VCS || ring->id == VCS2);
 }

@@ -1315,7 +1315,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
 
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 
 	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */

@@ -1341,7 +1341,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
 	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
 		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
 		wa_ctx_emit(batch, index,

@@ -1351,7 +1351,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
 
 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

drivers/gpu/drm/i915/intel_pm.c +1 -1

index 0fb0459..911f837 100644
@@ -4691,7 +4691,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
 			"on" : "off");
 	/* WaRsUseTimeoutMode */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
 		I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
 			   GEN7_RC_CTL_TO_MODE |

drivers/gpu/drm/i915/intel_ringbuffer.c +2 -2

index 02a5bb0..368d78b 100644
@@ -1099,11 +1099,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 
 	/* WaStoreMultiplePTEenable:bxt */
 	/* This is a requirement according to Hardware specification */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 
 	/* WaSetClckGatingDisableMedia:bxt */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
 					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
 	}

Signature · 6 lines

1.9.1

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Signature · 7 lines

Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Gore, Tim

author

2015-11-02 09:59 UTC #4 lore raw

Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ

Quoted 9 lines

-----Original Message-----
From: Daniel Vetter [mailto:[email protected]] On Behalf Of Daniel Vetter
Sent: Friday, October 30, 2015 4:11 PM
To: Gore, Tim
Cc: [email protected]
Subject: Re: [Intel-gfx] [PATCH] drm/i915: make A0 wa's applied to A1
On Mon, Oct 26, 2015 at 10:48:58AM +0000, [email protected] wrote:

Quoted 9 lines

Quoted 4 lines
From: Tim Gore <[email protected]>
Since A1 chips use the same GPU as A0, they need all the same wa's in the i915 driver. Update some conditionals to do this.
Neither summary nor commit message mentions that this is for bxt. Please fix.
-Daniel

This seems to have been merged. Is it possible for me to fix the commit message retrospectively (other than in my local repo)?
Tim

Quoted 120 lines

Quoted 15 lines
Signed-off-by Tim Gore <[email protected]>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 drivers/gpu/drm/i915/intel_lrc.c        | 8 ++++----
 drivers/gpu/drm/i915/intel_pm.c         | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)
drivers/gpu/drm/i915/intel_guc_loader.c +0 -0
index c0281df..6ec7b23 100644
drivers/gpu/drm/i915/intel_guc_loader.c static int guc_ucode_xfer(struct drm_i915_private · line 314
Quoted 7 lines
drivers/gpu/drm/i915/intel_guc_loader.c +1 -1
@@ -309,7 +309,7 @@ static int guc_ucode_xfer(struct drm_i915_private
 *dev_priv)
 
 	/* WaDisableMinuteIaClockGating:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GUC_SHIM_CONTROL,
(I915_READ(GUC_SHIM_CONTROL) &
Quoted 1 line
~GUC_ENABLE_MIA_CLOCK_GATING));
drivers/gpu/drm/i915/intel_lrc.c static bool disable_lite_restore_wa(struct
Quoted 7 lines
drivers/gpu/drm/i915/intel_guc_loader.c +0 -0
 	}
drivers/gpu/drm/i915/intel_lrc.c +0 -0
index 3265427..971d3f2 100644
@@ -285,7 +285,7 @@ static bool disable_lite_restore_wa(struct
intel_engine_cs *ring)
Quoted 8 lines
drivers/gpu/drm/i915/intel_lrc.c +1 -1
 	struct drm_device *dev = ring->dev;
 
 	return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-		IS_BXT_REVID(dev, 0, BXT_REVID_A0)) &&
+		IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
 	       (ring->id == VCS || ring->id == VCS2);  }
 
drivers/gpu/drm/i915/intel_lrc.c static int gen9_init_indirectctx_bb(struct · line 1320
Quoted 7 lines
drivers/gpu/drm/i915/intel_lrc.c +1 -1
@@ -1315,7 +1315,7 @@ static int gen9_init_indirectctx_bb(struct
 intel_engine_cs *ring,
 
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF |
MI_ARB_DISABLE);
drivers/gpu/drm/i915/intel_lrc.c static int gen9_init_indirectctx_bb(struct · line 1321
Quoted 2 lines
drivers/gpu/drm/i915/intel_lrc.c +0 -0
 	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ @@ -
1341,7
Quoted 4 lines
+1341,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
/*
WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
drivers/gpu/drm/i915/intel_lrc.c static int gen9_init_perctx_bb(struct intel_engine_cs *ring, · line 1347
Quoted 5 lines
drivers/gpu/drm/i915/intel_lrc.c +1 -1
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
 		wa_ctx_emit(batch, index,
GEN9_SLICE_COMMON_ECO_CHICKEN0);
drivers/gpu/drm/i915/intel_lrc.c static int gen9_init_perctx_bb(struct · line 1356
Quoted 9 lines
drivers/gpu/drm/i915/intel_lrc.c +1 -1
 		wa_ctx_emit(batch, index,
@@ -1351,7 +1351,7 @@ static int gen9_init_perctx_bb(struct
 intel_engine_cs *ring,
 
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF |
MI_ARB_ENABLE);
drivers/gpu/drm/i915/intel_pm.c static void gen9_enable_rc6(struct drm_device
Quoted 7 lines
drivers/gpu/drm/i915/intel_lrc.c +0 -0
 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); diff --git
a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0fb0459..911f837 100644
drivers/gpu/drm/i915/intel_pm.c +0 -0
@@ -4691,7 +4691,7 @@ static void gen9_enable_rc6(struct drm_device
*dev)
drivers/gpu/drm/i915/intel_pm.c static void gen9_enable_rc6(struct drm_device *dev)
Quoted 7 lines
drivers/gpu/drm/i915/intel_pm.c +1 -1
 			"on" : "off");
 	/* WaRsUseTimeoutMode */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
 		I915_WRITE(GEN6_RC_CONTROL,
GEN6_RC_CTL_HW_ENABLE |
Quoted 9 lines
drivers/gpu/drm/i915/intel_pm.c +0 -0
 			   GEN7_RC_CTL_TO_MODE |
drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0
index 02a5bb0..368d78b 100644
@@ -1099,11 +1099,11 @@ static int bxt_init_workarounds(struct
 intel_engine_cs *ring)
 
drivers/gpu/drm/i915/intel_ringbuffer.c static int bxt_init_workarounds(struct · line 1108
Quoted 10 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +2 -2
 	/* WaStoreMultiplePTEenable:bxt */
 	/* This is a requirement according to Hardware specification */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 
 	/* WaSetClckGatingDisableMedia:bxt */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GEN7_MISCCPCTL,
(I915_READ(GEN7_MISCCPCTL) &
Quoted 1 line
~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
Quoted 8 lines
}
--
1.9.1
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Quoted 4 lines

--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

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Jani Nikula

maintainer

2015-11-02 11:50 UTC #5 lore raw

Quoted 14 lines · Tim

Quoted 14 lines
-----Original Message-----
From: Daniel Vetter [mailto:[email protected]] On Behalf Of Daniel Vetter
Sent: Friday, October 30, 2015 4:11 PM
To: Gore, Tim
Cc: [email protected]
Subject: Re: [Intel-gfx] [PATCH] drm/i915: make A0 wa's applied to A1
Quoted 4 lines · On Mon, Oct 26, 2015 at 10:48:58AM +0000, [email protected] wrote:
From: Tim Gore <[email protected]>
Since A1 chips use the same GPU as A0, they need all the same wa's in the i915 driver. Update some conditionals to do this.

Quoted 7 lines

Quoted 4 lines
Neither summary nor commit message mentions that this is for bxt. Please fix.
-Daniel
This seems to have been merged. Is it possible for me to fix the commit message retrospectively (other than in my local repo)?
Tim

No. Daniel has a point but it was too late.

BR,
Jani.

Signature · 5 lines

Jani Nikula, Intel Open Source Technology Center
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