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arm64: cpufeature: declare enable_cpu_capabilities as static

PATCH New Will Deacon 3 participants 4 messages Oct 27, 2015 – Oct 28, 2015 arm64

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Will Deacon

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#0 lore raw

PATCH 1/2 arm64: cpufeature: declare enable_cpu_capabilities as static

enable_cpu_capabilities is only called from within cpufeature.c, so it can be declared static.

Signed-off-by Will Deacon <[email protected]>
---
 arch/arm64/kernel/cpufeature.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/kernel/cpufeature.c +1 -1
index d0d607452e1d..504526fa8129 100644
@@ -732,7 +732,7 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
  * Run through the enabled capabilities and enable() it on all active
  * CPUs
  */
-void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
+static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 {
 	int i;
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH 2/2 arm64: cachetype: fix definitions of ICACHEF_* flags

test_bit and set_bit take the bit number to operate on, rather than a mask. This patch fixes the ICACHEF_* definitions so that they represent the bit index in __icache_flags as opposed to the mask returned by the BIT macro.

Signed-off-by Will Deacon <[email protected]>
---
 arch/arm64/include/asm/cachetype.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/include/asm/cachetype.h +2 -2
index da2fc9e3cedd..f5588692f1d4 100644
@@ -34,8 +34,8 @@
 
 #define CTR_L1IP(ctr)	(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
 
-#define ICACHEF_ALIASING	BIT(0)
-#define ICACHEF_AIVIVT		BIT(1)
+#define ICACHEF_ALIASING	0
+#define ICACHEF_AIVIVT		1
 
 extern unsigned long __icache_flags;
Signature · 1 line
2.1.4
reviewer
#2 lore raw

PATCH 2/2 arm64: cachetype: fix definitions of ICACHEF_* flags

Quoted 6 lines · Will Deacon

test_bit and set_bit take the bit number to operate on, rather than a mask. This patch fixes the ICACHEF_* definitions so that they represent the bit index in __icache_flags as opposed to the mask returned by the BIT macro.

Signed-off-by Will Deacon <[email protected]>

At least they were used consistently, so this is a cleanup rather than a fix.

Reviewed-by Mark Rutland <[email protected]>

Mark.

Quoted 28 lines
---
 arch/arm64/include/asm/cachetype.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/include/asm/cachetype.h +2 -2
index da2fc9e3cedd..f5588692f1d4 100644
@@ -34,8 +34,8 @@
 
 #define CTR_L1IP(ctr)	(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
 
-#define ICACHEF_ALIASING	BIT(0)
-#define ICACHEF_AIVIVT		BIT(1)
+#define ICACHEF_ALIASING	0
+#define ICACHEF_AIVIVT		1
 
 extern unsigned long __icache_flags;
Signature · 7 lines
2.1.4


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