add LS1043AQDS support

drivers/pci/pcie_layerscape.c +3 -7

index 4cee038..8471678 100644
@@ -13,6 +13,7 @@
 #include <malloc.h>
 #ifdef CONFIG_FSL_LAYERSCAPE
 #include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
 #endif
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS

@@ -57,11 +58,6 @@
 #define PCIE_ATU_FUNC(x)             (((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET                0x91C
 
-/* LUT registers */
-#define PCIE_LUT_BASE                0x80000
-#define PCIE_LUT_LCTRL0              0x7F8
-#define PCIE_LUT_DBG         0x7FC
-
 #define PCIE_DBI_RO_WR_EN    0x8bc
 
 #define PCIE_LINK_CAP                0x7c

@@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
 
      return 1;
 }
-#else
+#elif defined(CONFIG_FSL_LAYERSCAPE)
 static int ls_pcie_link_state(struct ls_pcie *pcie)
 {
      u32 state;
 
-     state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
+     state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
              LTSSM_STATE_MASK;
      if (state < LTSSM_PCIE_L0) {
              debug("....PCIe link error. LTSSM=0x%02x.\n", state);

Quoted 40 lines · Gong Qianyu

drivers/pci/pcie_layerscape.c +3 -7

index 4cee038..8471678 100644
@@ -13,6 +13,7 @@
 #include <malloc.h>
 #ifdef CONFIG_FSL_LAYERSCAPE
 #include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
 #endif
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS

@@ -57,11 +58,6 @@
 #define PCIE_ATU_FUNC(x)             (((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET                0x91C
 
-/* LUT registers */
-#define PCIE_LUT_BASE                0x80000
-#define PCIE_LUT_LCTRL0              0x7F8
-#define PCIE_LUT_DBG         0x7FC
-
 #define PCIE_DBI_RO_WR_EN    0x8bc
 
 #define PCIE_LINK_CAP                0x7c

@@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
 
      return 1;
 }
-#else
+#elif defined(CONFIG_FSL_LAYERSCAPE)
 static int ls_pcie_link_state(struct ls_pcie *pcie)
 {
      u32 state;
 
-     state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
+     state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
              LTSSM_STATE_MASK;
      if (state < LTSSM_PCIE_L0) {
              debug("....PCIe link error. LTSSM=0x%02x.\n", state);

drivers/pci/pcie_layerscape.c static void ls_pcie_setup_ep(struct ls_pcie *pcie, · line 470

Quoted 9 lines

drivers/pci/pcie_layerscape.c +2 -0

@@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie,
 struct ls_pcie_info *info)
 
              for (pf = 0; pf < PCIE_PF_NUM; pf++) {
                      for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+#ifdef CONFIG_FSL_LAYERSCAPE
                              writel(PCIE_LCTRL0_VAL(pf, vf),
                                     pcie->dbi + PCIE_LUT_BASE +
                                     PCIE_LUT_LCTRL0);
+#endif

It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file whose name suggests is layerscape-specific. What chips use this file that are not CONFIG_FSL_LAYERSCAPE?

-Scott

+Simon,

Hi,

Quoted 55 lines · Scott Wood

Quoted 40 lines · Gong Qianyu

drivers/pci/pcie_layerscape.c +3 -7

index 4cee038..8471678 100644
@@ -13,6 +13,7 @@
 #include <malloc.h>
 #ifdef CONFIG_FSL_LAYERSCAPE
 #include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
 #endif
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS

@@ -57,11 +58,6 @@
 #define PCIE_ATU_FUNC(x)             (((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET                0x91C
 
-/* LUT registers */
-#define PCIE_LUT_BASE                0x80000
-#define PCIE_LUT_LCTRL0              0x7F8
-#define PCIE_LUT_DBG         0x7FC
-
 #define PCIE_DBI_RO_WR_EN    0x8bc
 
 #define PCIE_LINK_CAP                0x7c

@@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
 
      return 1;
 }
-#else
+#elif defined(CONFIG_FSL_LAYERSCAPE)
 static int ls_pcie_link_state(struct ls_pcie *pcie)
 {
      u32 state;
 
-     state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
+     state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
              LTSSM_STATE_MASK;
      if (state < LTSSM_PCIE_L0) {
              debug("....PCIe link error. LTSSM=0x%02x.\n", state);

drivers/pci/pcie_layerscape.c static void ls_pcie_setup_ep(struct ls_pcie *pcie, · line 470

Quoted 9 lines

drivers/pci/pcie_layerscape.c +2 -0

@@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie,
 struct ls_pcie_info *info)
 
              for (pf = 0; pf < PCIE_PF_NUM; pf++) {
                      for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+#ifdef CONFIG_FSL_LAYERSCAPE
                              writel(PCIE_LCTRL0_VAL(pf, vf),
                                     pcie->dbi + PCIE_LUT_BASE +
                                     PCIE_LUT_LCTRL0);
+#endif

It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file whose name suggests is layerscape-specific. What chips use this file that are not CONFIG_FSL_LAYERSCAPE?

Quoted 1 line

-Scott

Can we start converting the driver to use DM PCI? We should not continue using legacy PCI codes since right now DM PCI is in a good shape. These #ifdef in the driver should really go into device tree as needed.

Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot.

Signed-off-by Gong Qianyu <[email protected]>

---
V2:
- New Patch.

 arch/arm/dts/Makefile            |   1 +
 arch/arm/dts/fsl-ls1043a-rdb.dts | 169 +++++++++++++++++++
 arch/arm/dts/fsl-ls1043a.dtsi    | 346 
+++++++++++++++++++++++++++++++++++++++
 configs/ls1043ardb_defconfig     |   2 +
 4 files changed, 518 insertions(+)

arch/arm/dts/Makefile +1 -0

index ddc6a05..3f3a739 100644
@@ -83,6 +83,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
      ls1021a-twr.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
      fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
      sun4i-a10-a1000.dtb \

arch/arm/dts/fsl-ls1043a- renamed from arch/arm/dts/fsl-ls1043a-rdb.dts +0 -0

rdb.dts
new file mode 100644
index 0000000..51b5e9f

arch/arm/dts/fsl-ls1043a-rdb.dts new file +140 -0

@@ -0,0 +1,169 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+     model = "LS1043A RDB Board";
+};
+
+&i2c0 {
+     status = "okay";
+      ina220 at 40{
+             compatible = "ti,ina220";
+             reg = <0x40>;
+             shunt-resistor = <1000>;
+     };
+      adt7461a at 4c{
+             compatible = "adt7461a";
+             reg = <0x4c>;
+     };
+      eeprom at 56{
+             compatible = "at24,24c512";
+             reg = <0x52>;
+     };
+
+      eeprom at 57{
+             compatible = "at24,24c512";
+             reg = <0x53>;
+     };
+
+      rtc at 68{
+             compatible = "pericom,pt7c4338";
+             reg = <0x68>;
+     };
+};
+
+&ifc {
+     status = "okay";
+     #address-cells = <2>;
+     #size-cells = <1>;
+     /* NOR, NAND Flashes and FPGA on board */
+     ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+               0x2 0x0 0x0 0x7e800000 0x00010000
+               0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+             nor at 0,0 {
+                     compatible = "cfi-flash";
+                     #address-cells = <1>;
+                     #size-cells = <1>;
+                     reg = <0x0 0x0 0x8000000>;
+                     bank-width = <2>;
+                     device-width = <1>;
+
+                      partition at 0{
+                             /* 1MB for RCW and PBI Image */
+                             reg = <0x00000000 0x00100000>;
+                             label = "NOR bank0 RCW Image";
+                     };
+
+                      partition at 100000{
+                             /* 1MB for bank0 u-boot Image */
+                             reg = <0x00100000 0x00100000>;
+                             label = "NOR bank0 U-Boot Image";
+                     };
+
+                      partition at 200000{
+                             /* 1 MB for bank0 u-boot Env */
+                             reg = <0x00200000 0x00100000>;
+                             label = "NOR bank0 U-Boot Env";
+                     };
+
+                      partition at 300000{
+                             /* 1MB for FMan ucode */
+                             reg = <0x00300000 0x00100000>;
+                             label = "NOR bank0 FMan ucode";
+                     };
+
+                      partition at 1100000{
+                             /* 40MB for bank0 FIT Image */
+                             reg = <0x01100000 0x2800000>;
+                             label = "NOR bank0 FIT Image";
+                     };
+
+                      partition at 4000000{
+                             /* 1MB for bank4 RCW and PBI Image */
+                             reg = <0x04000000 0x100000>;
+                             label = "NOR bank4 RCW Image";
+                     };
+
+                      partition at 4100000{
+                             /* 1MB for bank4 u-boot Image */
+                             reg = <0x04100000 0x100000>;
+                             label = "NOR bank4 U-Boot Image";
+                     };
+
+                      partition at 4200000{
+                             /* 1 MB for bank4 u-boot Env */
+                             reg = <0x04200000 0x100000>;
+                             label = "NOR bank4 U-Boot Env";
+                     };
+
+                      partition at 4300000{
+                             /* 1 MB for bank4 FMan ucode */
+                             reg = <0x04300000 0x100000>;
+                             label = "NOR bank4 FMan ucode";
+                     };
+
+                      partition at 5100000{
+                             /* 40MB for bank4 FIT Image */
+                             reg = <0x05100000 0x2800000>;
+                             label = "NOR bank4 FIT Image";
+                     };
+             };
+
+             nand at 1,0 {
+                     compatible = "fsl,ifc-nand";
+                     #address-cells = <1>;
+                     #size-cells = <1>;
+                     reg = <0x2 0x0 0x10000>;
+
+                      partition at 0{
+                             /* This location must not be altered  */
+                             /* 1MB for u-boot Bootloader Image */
+                             reg = <0x0 0x00100000>;
+                             label = "NAND U-Boot Image";
+                             read-only;
+                     };
+
+                      partition at 140000{
+                             /* 1MB for DTB Image */

arch/arm/dts/fsl-ls1043a-rdb.dts new file +39 -0

+     clockgen:  clocking at 1ee1000{
+             ranges = <0x0 0x0 0x1ee1000 0x1000>;
+             #address-cells = <1>;
+             #size-cells = <1>;
+             sysclk: sysclk {
+                     compatible = "fixed-clock";
+                     #clock-cells = <0>;
+                     clock-frequency = <100000000>;
+                     clock-output-names = "sysclk";
+             };
+
+             cga_pll1:  pll1 at 800{
+                     compatible = "fsl,qoriq-core-pll-2.0";
+                     #clock-cells = <1>;
+                     reg = <0x800 0x10>;
+                     clocks = <&sysclk>;
+                     clock-output-names = "cga-pll1", "cga-pll1-div2",
+                                     "cga-pll1-div3", "cga-pll1-div4";
+             };
+
+             cga_pll2:  pll2 at 820{
+                     compatible = "fsl,qoriq-core-pll-2.0";
+                     #clock-cells = <1>;
+                     reg = <0x820 0x10>;
+                     clocks = <&sysclk>;
+                     clock-output-names = "cga-pll2", "cga-pll2-div2",
+                                     "cga-pll2-div3", "cga-pll2-div4";
+             };
+
+             platform_clk:  pll at c00{
+                     compatible = "fsl,qoriq-core-pll-2.0";
+                     #clock-cells = <1>;
+                     reg = <0xc00 0x10>;
+                     clocks = <&sysclk>;
+                     clock-output-names = "platform-clk", "platform-clk-div2";
+             };
+
+             cluster1_clk:  clk0c0 at 0{
+                     compatible = "fsl,qoriq-core-mux-2.0";

-----Original Message-----
From: Wood Scott-B07421
Sent: Thursday, November 05, 2015 7:51 AM
To: Gong Qianyu-B52263
Cc: u-boot at lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-B21989; Song Wenbin-B53747; Wood Scott- B07421; Kushwaha Prabhakar-B32579
Subject: Re: [Patch V2 2/4] armv8/ls1043ardb: dts: add dtb support

Quoted 173 lines · Gong Qianyu

Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot.

Signed-off-by Gong Qianyu <[email protected]>

---
V2:
- New Patch.

 arch/arm/dts/Makefile            |   1 +
 arch/arm/dts/fsl-ls1043a-rdb.dts | 169 +++++++++++++++++++
 arch/arm/dts/fsl-ls1043a.dtsi    | 346
+++++++++++++++++++++++++++++++++++++++
 configs/ls1043ardb_defconfig     |   2 +
 4 files changed, 518 insertions(+)

arch/arm/dts/Makefile index renamed from arch/arm/dts/Makefile +0 -0

ddc6a05..3f3a739 100644

arch/arm/dts/Makefile +1 -0

@@ -83,6 +83,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
      ls1021a-twr.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
      fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
      sun4i-a10-a1000.dtb \

(quoted diff) +0 -0

b/arch/arm/dts/fsl-ls1043a- rdb.dts new file mode 100644 index 0000000..51b5e9f

arch/arm/dts/fsl-ls1043a-rdb.dts new file +140 -0

@@ -0,0 +1,169 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+     model = "LS1043A RDB Board";
+};
+
+&i2c0 {
+     status = "okay";
+      ina220 at 40{
+             compatible = "ti,ina220";
+             reg = <0x40>;
+             shunt-resistor = <1000>;
+     };
+      adt7461a at 4c{
+             compatible = "adt7461a";
+             reg = <0x4c>;
+     };
+      eeprom at 56{
+             compatible = "at24,24c512";
+             reg = <0x52>;
+     };
+
+      eeprom at 57{
+             compatible = "at24,24c512";
+             reg = <0x53>;
+     };
+
+      rtc at 68{
+             compatible = "pericom,pt7c4338";
+             reg = <0x68>;
+     };
+};
+
+&ifc {
+     status = "okay";
+     #address-cells = <2>;
+     #size-cells = <1>;
+     /* NOR, NAND Flashes and FPGA on board */
+     ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+               0x2 0x0 0x0 0x7e800000 0x00010000
+               0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+             nor at 0,0 {
+                     compatible = "cfi-flash";
+                     #address-cells = <1>;
+                     #size-cells = <1>;
+                     reg = <0x0 0x0 0x8000000>;
+                     bank-width = <2>;
+                     device-width = <1>;
+
+                      partition at 0{
+                             /* 1MB for RCW and PBI Image */
+                             reg = <0x00000000 0x00100000>;
+                             label = "NOR bank0 RCW Image";
+                     };
+
+                      partition at 100000{
+                             /* 1MB for bank0 u-boot Image */
+                             reg = <0x00100000 0x00100000>;
+                             label = "NOR bank0 U-Boot Image";
+                     };
+
+                      partition at 200000{
+                             /* 1 MB for bank0 u-boot Env */
+                             reg = <0x00200000 0x00100000>;
+                             label = "NOR bank0 U-Boot Env";
+                     };
+
+                      partition at 300000{
+                             /* 1MB for FMan ucode */
+                             reg = <0x00300000 0x00100000>;
+                             label = "NOR bank0 FMan ucode";
+                     };
+
+                      partition at 1100000{
+                             /* 40MB for bank0 FIT Image */
+                             reg = <0x01100000 0x2800000>;
+                             label = "NOR bank0 FIT Image";
+                     };
+
+                      partition at 4000000{
+                             /* 1MB for bank4 RCW and PBI Image */
+                             reg = <0x04000000 0x100000>;
+                             label = "NOR bank4 RCW Image";
+                     };
+
+                      partition at 4100000{
+                             /* 1MB for bank4 u-boot Image */
+                             reg = <0x04100000 0x100000>;
+                             label = "NOR bank4 U-Boot Image";
+                     };
+
+                      partition at 4200000{
+                             /* 1 MB for bank4 u-boot Env */
+                             reg = <0x04200000 0x100000>;
+                             label = "NOR bank4 U-Boot Env";
+                     };
+
+                      partition at 4300000{
+                             /* 1 MB for bank4 FMan ucode */
+                             reg = <0x04300000 0x100000>;
+                             label = "NOR bank4 FMan ucode";
+                     };
+
+                      partition at 5100000{
+                             /* 40MB for bank4 FIT Image */
+                             reg = <0x05100000 0x2800000>;
+                             label = "NOR bank4 FIT Image";
+                     };
+             };
+
+             nand at 1,0 {
+                     compatible = "fsl,ifc-nand";
+                     #address-cells = <1>;
+                     #size-cells = <1>;
+                     reg = <0x2 0x0 0x10000>;
+
+                      partition at 0{
+                             /* This location must not be altered  */
+                             /* 1MB for u-boot Bootloader Image */
+                             reg = <0x0 0x00100000>;
+                             label = "NAND U-Boot Image";
+                             read-only;
+                     };
+
+                      partition at 140000{
+                             /* 1MB for DTB Image */

arch/arm/dts/fsl-ls1043a-rdb.dts line 150

Quoted 10 lines

arch/arm/dts/fsl-ls1043a-rdb.dts new file +10 -0

+                             reg = <0x00140000 0x002000>;
+                             label = "NAND U-Boot Env";
+                     };
+
+                      partition at 200000{
+                             /* 20MB for FIT Image */
+                             reg = <0x00200000 0x01400000>;
+                             label = "NAND FIT Image";
+                     };
+             };

Why are the partitions defined here rather than in an environment variable?

Quoted 25 lines

arch/arm/dts/fsl-ls1043a-rdb.dts new file +25 -0

+     clockgen:  clocking at 1ee1000{
+             ranges = <0x0 0x0 0x1ee1000 0x1000>;
+             #address-cells = <1>;
+             #size-cells = <1>;
+             sysclk: sysclk {
+                     compatible = "fixed-clock";
+                     #clock-cells = <0>;
+                     clock-frequency = <100000000>;
+                     clock-output-names = "sysclk";
+             };
+
+             cga_pll1:  pll1 at 800{
+                     compatible = "fsl,qoriq-core-pll-2.0";
+                     #clock-cells = <1>;
+                     reg = <0x800 0x10>;
+                     clocks = <&sysclk>;
+                     clock-output-names = "cga-pll1", "cga-pll1-div2",
+                                     "cga-pll1-div3", "cga-pll1-div4";
+             };
+
+             cga_pll2:  pll2 at 820{
+                     compatible = "fsl,qoriq-core-pll-2.0";
+                     #clock-cells = <1>;
+                     reg = <0x820 0x10>;
+                     clocks = <&sysclk>;

arch/arm/dts/fsl-ls1043a-rdb.dts

Quoted 10 lines

arch/arm/dts/fsl-ls1043a-rdb.dts new file +10 -0

+                     clock-output-names = "cga-pll2", "cga-pll2-div2",
+                                     "cga-pll2-div3", "cga-pll2-div4";
+             };
+
+             platform_clk:  pll at c00{
+                     compatible = "fsl,qoriq-core-pll-2.0";
+                     #clock-cells = <1>;
+                     reg = <0xc00 0x10>;
+                     clocks = <&sysclk>;
+                     clock-output-names = "platform-clk", "platform-

clk-div2";

arch/arm/dts/fsl-ls1043a-rdb.dts

Quoted 7 lines

arch/arm/dts/fsl-ls1043a-rdb.dts new file +7 -0

+             };
+
+             cluster1_clk:  clk0c0 at 0{
+                     compatible = "fsl,qoriq-core-mux-2.0";
+                     #clock-cells = <0>;
+                     reg = <0x0 0x10>;
+                     clock-names = "pll1cga", "pll1cga-div2",

"pll1cga-div4",

Quoted 1 line

+ "pll2cga", "pll2cga-div2",

"pll2cga-div4";

Quoted 1 line

+ clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1

2>,

Quoted 1 line

+ <&cga_pll2 0>, <&cga_pll2 1>, <&cga_pll2

2>;

arch/arm/dts/fsl-ls1043a-rdb.dts

Quoted 4 lines

arch/arm/dts/fsl-ls1043a-rdb.dts new file +4 -0

+                     clock-output-names = "cluster1-clk";
+
+             };
+     };

This binding is deprecated. Please don't add any more users of it (especially broken users that lack compatible, reg, etc), and more generally please use the latest version of the Linux ls1043a device tree rather than things that have never been accepted in upstream Linux.

-Scott

arch/arm/include/asm/arch-fsl-layerscape/fdt.h +3 -0

index 4da73ab..e3989a8 100644
@@ -11,4 +11,7 @@ void alloc_stream_ids(int start_id, int count, u32 
 *stream_ids, int max_cnt);
 void append_mmu_masters(void *blob, const char *smmu_path,
                      const char *master_name, u32 *stream_ids, int count);
 void fdt_fixup_smmu_pcie(void *blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+void fdt_fixup_board_enet(void *fdt);
+#endif

#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */