Enable high speed and heavy load for DDR4 for LSCH3

This patch set revises the DDR driver to support higher speed for DDR4 under heavy load (two dual-rank DIMMs) for four-chipselect interleaving. Single quad-rank DIMM is not supported yet.

-----Original Message-----
From: Joakim Tjernlund [mailto:joakim.tjernlund at transmode.se]
Sent: Thursday, November 05, 2015 4:04 PM
To: Sun York-R58495 <[email protected]>; u-boot at lists.denx.de
Cc: curt at cumulusnetworks.com; Sharma Bhupesh-B45370 <[email protected]>; trini at konsulko.com; l.majewski at samsung.com; Tang Yuantian-B29983 <[email protected]>; Kushwaha Prabhakar-B32579 <[email protected]>; Liu Shengzhou-B36685 <[email protected]>; yamada.m at jp.panasonic.com
Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

Quoted 3 lines · York Sun

This patch set revises the DDR driver to support higher speed for DDR4 under heavy load (two dual-rank DIMMs) for four-chipselect interleaving. Single quad-rank DIMM is not supported yet.

Hi York

Seeing these patches reminds me about something I have been mening to ask, Is it possible init the ddr controller/ddr ram (using ECC also) but still retain (parts of) memory contents?

I am looking at keeping data at the end of memory when performing a warm start, but still init the controll/ddr ram (without D_INIT set). This way one could pick up any changes to DDR timing if needed. Before reboot, ddr ram is set to Self Refresh(SR).

Jocke

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Regards,
Yuantian

Quoted 30 lines

-----Original Message-----
From: Joakim Tjernlund [mailto:joakim.tjernlund at transmode.se]
Sent: Thursday, November 05, 2015 4:04 PM
To: Sun York-R58495 <[email protected]>; u-boot at lists.denx.de
Cc: curt at cumulusnetworks.com; Sharma Bhupesh-B45370 <[email protected]>; trini at konsulko.com; l.majewski at samsung.com; Tang Yuantian-B29983 <[email protected]>; Kushwaha Prabhakar-B32579 <[email protected]>; Liu Shengzhou-B36685 <[email protected]>; yamada.m at jp.panasonic.com
Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

Quoted 3 lines · York Sun

This patch set revises the DDR driver to support higher speed for DDR4 under heavy load (two dual-rank DIMMs) for four-chipselect interleaving. Single quad-rank DIMM is not supported yet.

Hi York

Seeing these patches reminds me about something I have been mening to ask, Is it possible init the ddr controller/ddr ram (using ECC also) but still retain (parts of) memory contents?

I am looking at keeping data at the end of memory when performing a warm start, but still init the controll/ddr ram (without D_INIT set). This way one could pick up any changes to DDR timing if needed. Before reboot, ddr ram is set to Self Refresh(SR).

Jocke

Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

Quoted 15 lines · Joakim Tjernlund

Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Quoted 3 lines

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

Quoted 9 lines

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Quoted 2 lines

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

Quoted 17 lines · York Sun

Quoted 15 lines · Joakim Tjernlund

Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Quoted 7 lines

Quoted 3 lines

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

OK

Quoted 9 lines

Quoted 9 lines

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Quoted 6 lines

Quoted 2 lines

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

yes, but what about SDRAM_CFG_BI? Why do you need to set that here?
I much rather just skip D_INIT and reconfigure DDR RAM, just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust.

Our systems cannot be coldstarted just because you upgrade SW on them.

Quoted 49 lines · Joakim Tjernlund

Quoted 18 lines · York Sun

Quoted 16 lines · Joakim Tjernlund

Quoted 7 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents
untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Quoted 7 lines

Quoted 3 lines

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

OK

Quoted 9 lines

Quoted 9 lines

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Quoted 6 lines

Quoted 2 lines

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

yes, but what about SDRAM_CFG_BI? Why do you need to set that here?
I much rather just skip D_INIT and reconfigure DDR RAM, just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust.

Quoted 1 line

Our systems cannot be coldstarted just because you upgrade SW on them.

Jocke,

If your memory has been intialized, you can set [BI] bit to bypass re-initialization. It does different things than D_INIT. In short, D_INIT initialize the data, i.e. the content of DDR, while BI bypassing initializing DDR memory (or "chip" if that is easier to understand).

Quoted 55 lines · York Sun

Quoted 45 lines · Joakim Tjernlund

Quoted 18 lines · York Sun

Quoted 16 lines · Joakim Tjernlund

Quoted 7 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents
untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Quoted 7 lines

Quoted 3 lines

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

OK

Quoted 9 lines

Quoted 9 lines

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Quoted 6 lines

Quoted 2 lines

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

Quoted 5 lines

yes, but what about SDRAM_CFG_BI? Why do you need to set that here?
I much rather just skip D_INIT and reconfigure DDR RAM, just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust.

Our systems cannot be coldstarted just because you upgrade SW on them.

Jocke,

Quoted 4 lines

If your memory has been intialized, you can set [BI] bit to bypass re-initialization. It does different things than D_INIT. In short, D_INIT initialize the data, i.e. the content of DDR, while BI bypassing initializing DDR memory (or "chip" if that is easier to understand).

Yes, that is what I want, reinit of chip, but not data contents.
I wrote why:
"just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust"

Quoted 61 lines · Joakim Tjernlund

Quoted 59 lines · York Sun

Quoted 45 lines · Joakim Tjernlund

Quoted 18 lines · York Sun

Quoted 16 lines · Joakim Tjernlund

Quoted 7 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents
untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
?289 if (is_warm_boot()) {
?289?????????????????/* enter self-refresh */ ?290?????????????????temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); ?291?????????????????temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; ?292?????????????????ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Quoted 7 lines

Quoted 3 lines

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

OK

Quoted 9 lines

Quoted 9 lines

?293?????????????????/* do board specific memory setup */ ?294?????????????????board_mem_sleep_setup();
?295
?296?????????????????temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Quoted 6 lines

Quoted 2 lines

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

Quoted 5 lines

yes, but what about SDRAM_CFG_BI? Why do you need to set that here?
I much rather just skip D_INIT and reconfigure DDR RAM, just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust.

Our systems cannot be coldstarted just because you upgrade SW on them.

Jocke,

If your memory has been intialized, you can set [BI] bit to bypass re-initialization. It does different things than D_INIT. In short, D_INIT initialize the data, i.e. the content of DDR, while BI bypassing initializing DDR memory (or "chip" if that is easier to understand).

Quoted 4 lines

Yes, that is what I want, reinit of chip, but not data contents.
I wrote why:
"just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust"

Jocke,

I am not 100% sure. I will take this question to our DDR designer.

Quoted 68 lines · York Sun

Quoted 65 lines · Joakim Tjernlund

Quoted 51 lines · York Sun

Quoted 49 lines · Joakim Tjernlund

Quoted 18 lines · York Sun

Quoted 16 lines · Joakim Tjernlund

Quoted 7 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents
untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Quoted 7 lines

Quoted 3 lines

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

OK

Quoted 9 lines

Quoted 9 lines

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Quoted 6 lines

Quoted 2 lines

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

yes, but what about SDRAM_CFG_BI? Why do you need to set that here?
I much rather just skip D_INIT and reconfigure DDR RAM, just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust.

Quoted 8 lines

Quoted 1 line

Our systems cannot be coldstarted just because you upgrade SW on them.

Jocke,

If your memory has been intialized, you can set [BI] bit to bypass re-initialization. It does different things than D_INIT. In short, D_INIT initialize the data, i.e. the content of DDR, while BI bypassing initializing DDR memory (or "chip" if that is easier to understand).

Yes, that is what I want, reinit of chip, but not data contents.
I wrote why:
"just in case one wants to correct some aspect of DDR config in later releases and feels a lot more robust"

Quoted 3 lines

Jocke,

I am not 100% sure. I will take this question to our DDR designer.

I am really want to know ...

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Friday, November 06, 2015 1:42 AM
To: Joakim Tjernlund <[email protected]>; Tang Yuantian- B29983 <[email protected]>; u-boot at lists.denx.de
Cc: Kushwaha Prabhakar-B32579 <[email protected]>; Sharma Bhupesh-B45370 <[email protected]>; trini at konsulko.com; Liu Shengzhou-B36685 <[email protected]>;
curt at cumulusnetworks.com; l.majewski at samsung.com; yamada.m at jp.panasonic.com
Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

Quoted 7 lines · Joakim Tjernlund

Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for. If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched. Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP

related code.

Quoted 8 lines

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Quoted 1 line

Why do you need to force SR here? The DDR RAM must already be in SR at

this point?

Quoted 2 lines

I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

Quoted 5 lines

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) |

SDRAM_CFG_BI);

Quoted 2 lines

SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have

to force a cold start.

Quoted 3 lines

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

To perform a warm start, the data in DDR is preserved. So you don't need to init the data again for ECC. To preserve data, you cannot run D_INIT again, which will destroy the data for sure.

York

Quoted 38 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Friday, November 06, 2015 1:42 AM
To: Joakim Tjernlund <[email protected]>; Tang Yuantian- B29983 <[email protected]>; u-boot at lists.denx.de
Cc: Kushwaha Prabhakar-B32579 <[email protected]>; Sharma Bhupesh-B45370 <[email protected]>; trini at konsulko.com; Liu Shengzhou-B36685 <[email protected]>;
curt at cumulusnetworks.com; l.majewski at samsung.com; yamada.m at jp.panasonic.com
Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

Quoted 7 lines · Joakim Tjernlund

Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for. If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched. Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP

related code.

Quoted 9 lines

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Why do you need to force SR here? The DDR RAM must already be in SR at

this point?

Quoted 2 lines

I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

Quoted 4 lines

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

This is mandatory. the steps are: re-enter SR mode, enable DDR controller, exit SR mode. We do that to smooth the transition and avoid any glitch caused when controller takes over memory.

This patch set revises the DDR driver to support higher speed for DDR4 under heavy load (two dual-rank DIMMs) for four-chipselect interleaving. Single quad-rank DIMM is not supported yet.

York Sun (7):
driver/ddr/fsl: Update DDR4 RTT values driver/ddr/fsl: Update DDR4 MR6 for Vref range driver/ddr/fsl: Update MR5 RTT park
driver/ddr/fsl: Update workaround for A008511 for vref range driver/ddr/fsl: Update timing config for heavy load armv8/ls2085aqds: Update DDR settings for four chip-select case armv8/ls2085ardb: Update DDR settings for four chip-select case

 board/freescale/ls2085aqds/ddr.c |   16 ++-
 board/freescale/ls2085ardb/ddr.c |   16 ++-
 drivers/ddr/fsl/ctrl_regs.c      |   48 +++++++-
 drivers/ddr/fsl/fsl_ddr_gen4.c   |   22 ++--
 drivers/ddr/fsl/options.c        |  237 +++++++++++++++++++++++++++++++++++++-
 include/fsl_ddr_sdram.h          |    9 ++
 6 files changed, 325 insertions(+), 23 deletions(-)