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clk: xgene: Fix divider with non-zero shift value

PATCH New Loc Ho 2 participants 2 messages Nov 19, 2015 – Nov 20, 2015 Common clk

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Loc Ho

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#0 lore raw

PATCH 1/1 clk: xgene: Fix divider with non-zero shift value

The X-Gene clock driver missed the divider shift operation when set the divider value.

Signed-off-by Loc Ho <[email protected]>
---
 drivers/clk/clk-xgene.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
drivers/clk/clk-xgene.c +2 -1
index 27c0da2..10224b0 100644
@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 		/* Set new divider */
 		data = xgene_clk_read(pclk->param.divider_reg +
 				pclk->param.reg_divider_offset);
-		data &= ~((1 << pclk->param.reg_divider_width) - 1);
+		data &= ~((1 << pclk->param.reg_divider_width) - 1)
+				<< pclk->param.reg_divider_shift;
 		data |= divider;
 		xgene_clk_write(data, pclk->param.divider_reg +
 					pclk->param.reg_divider_offset);
Signature · 1 line
1.7.1
Applied
#1 lore raw

PATCH 1/1 clk: xgene: Fix divider with non-zero shift value

Quoted 4 lines · Loc Ho

The X-Gene clock driver missed the divider shift operation when set the divider value.

Signed-off-by Loc Ho <[email protected]>

Applied to clk-next +

Fixes 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signature · 2 lines
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