sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
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PATCH 1/1 sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
--- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ---- 1 file changed, 4 deletions(-)
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +0 -4
@@ -220,11 +220,7 @@ struct sunxi_ccm_reg {#define CCM_PLL11_CTRL_UPD (0x1 << 30)#define CCM_PLL11_CTRL_EN (0x1 << 31) -#if definedCONFIG_MACH_SUN8I_H3 #define AHB1_ABP1_DIV_DEFAULT 0x00003180/* AHB1=PLL6/3,APB1=AHB1/2 */ -#else -#define AHB1_ABP1_DIV_DEFAULT 0x00002020/* AHB1=AXI/4, APB1=AHB1/2 */ -#endif #define AXI_GATE_OFFSET_DRAM 0
Signature · 1 line
2.5.0
PATCH 1/1 sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
Quoted 6 lines · Hans de Goede
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by Chen-Yu Tsai <[email protected]>Signed-off-by Hans de Goede <[email protected]>
I suppose you've tested this on at least one such board? In that case:
Quoted 23 lines
--- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ---- 1 file changed, 4 deletions(-)arch/arm/include/asm/arch-sunxi/clock_sun6i.h +0
-1@@ -220,11 +220,7 @@ struct sunxi_ccm_reg {#define CCM_PLL11_CTRL_UPD (0x1 << 30)#define CCM_PLL11_CTRL_EN (0x1 << 31) -#if definedCONFIG_MACH_SUN8I_H3 #define AHB1_ABP1_DIV_DEFAULT 0x00003180/* AHB1=PLL6/3,APB1=AHB1/2 */
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +0
-2-#else -#define AHB1_ABP1_DIV_DEFAULT 0x00002020/* AHB1=AXI/4, APB1=AHB1/2 */
-#endif#define
AXI_GATE_OFFSET_DRAM0
PATCH 1/1 sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
Quoted 10 lines · Ian Campbell
Quoted 6 lines · Hans de Goede
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by Chen-Yu Tsai <[email protected]>Signed-off-by Hans de Goede <[email protected]>I suppose you've tested this on at least one such board? In that case:
Acked-by Ian Campbell <[email protected]>
I've tested this on some of my boards. It works fine on my Hummingbird A31 and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which I haven't looked into yet.
ChenYu
PATCH 1/1 sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
Hi,
Quoted 9 lines · Chen-Yu Tsai
Quoted 8 lines · Ian Campbell
Quoted 6 lines · Hans de Goede
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by Chen-Yu Tsai <[email protected]>Signed-off-by Hans de Goede <[email protected]>
Quoted 6 lines
Quoted 2 lines
I suppose you've tested this on at least one such board? In that case:
Acked-by Ian Campbell <[email protected]>I've tested this on some of my boards. It works fine on my Hummingbird A31 and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which I haven't looked into yet.
Works for me on a q8 A33 tablet. But lets investigate your oops before including this in the next pull-req. Thanks for the testing!
Regards,
Hans
PATCH 1/1 sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
Hi,
Quoted 27 lines · Hans de Goede
Hi,
Quoted 14 lines · Chen-Yu Tsai
Quoted 11 lines · Ian Campbell
Quoted 7 lines · Hans de Goede
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by Chen-Yu Tsai <[email protected]>Signed-off-by Hans de Goede <[email protected]>Quoted 8 lines
Quoted 2 lines
I suppose you've tested this on at least one such board? In that case:
Acked-by Ian Campbell <[email protected]>I've tested this on some of my boards. It works fine on my Hummingbird A31 and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which
I haven't looked into yet.
Quoted 3 lines
Works for me on a q8 A33 tablet. But lets investigate your oops before including
this in the next pull-req. Thanks for the testing!
I retested it with a proper clean build, and it works now. No idea what the oops was about.
Also tested on my Sinlinx SinA31s. So it now works on all my sun6i generation boards.
PATCH 1/1 sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
Quoted 44 lines · Chen-Yu Tsai
Hi,
Quoted 5 lines · Hans de Goede
Hi,
Quoted 2 lines · Chen-Yu Tsai
On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <
ijc+uboot at hellion.org.uk>
Quoted 8 lines
Quoted 8 lines
Quoted 7 lines · wrote:
Quoted 5 lines · Hans de Goede
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
Quoted 2 lines
Suggested-by Chen-Yu Tsai <[email protected]>Signed-off-by Hans de Goede <[email protected]>I suppose you've tested this on at least one such board? In that
case:
Quoted 4 lines
Quoted 4 lines
Quoted 1 line
Acked-by Ian Campbell <[email protected]>I've tested this on some of my boards. It works fine on my
Hummingbird A31
Quoted 1 line
Quoted 1 line
and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel
Oops
Quoted 5 lines
Quoted 2 lines
which
I haven't looked into yet.Works for me on a q8 A33 tablet. But lets investigate your oops
before
Quoted 2 lines
including
this in the next pull-req. Thanks for the testing!I retested it with a proper clean build, and it works now. No idea what
the oops was about.
Quoted 5 lines
Also tested on my Sinlinx SinA31s. So it now works on all my sun6i generation
boards.Tested-by Chen-Yu Tsai <[email protected]>
Good enough for me, my original Ack stands...