ARM: socfpga: arria10: add base address map for Arria10

PATCH Superseded dinguyen at opensource.altera.com 3 participants 5 messages Nov 23, 2015 – Nov 24, 2015

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/socfpga architecture

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dinguyen at opensource.altera.com

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2015-11-23 23:27 UTC #0 lore raw

PATCH v2 1/2 ARM: socfpga: arria10: add base address map for Arria10

From: Dinh Nguyen <[email protected]>

Add the base address map for Arria10.

Signed-off-by Dinh Nguyen <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v2: renamed to base_addr_a10.h

---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 45 ++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_a10.h

arch/arm/mach-socfpga/include/mach/base_addr_a10.h new file +45 -0

new file mode 100644
index 0000000..a7056d4
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
+#define _SOCFPGA_A10_BASE_HARDWARE_H_
+
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS		0xff809000
+#define SOCFPGA_QSPIDATA_ADDRESS		0xffa00000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xffcfa000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400
+#define SOCFPGA_FPGAMGRREGS_ADDRESS		0xffd03000
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd06000
+#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS	0xffd07000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd07200
+#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS	0xffd07300
+#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS	0xffd07400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_MPUSCU_ADDRESS			0xffffc000
+#define SOCFPGA_MPUL2_ADDRESS			0xfffff000
+#define SOCFPGA_I2C0_ADDRESS			0xffc02200
+#define SOCFPGA_I2C1_ADDRESS			0xffc02300
+
+#define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
+
+#define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
+#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
+
+#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */

Signature · 1 line

2.6.2

dinguyen at opensource.altera.com

author

2015-11-23 23:27 UTC #1 lore raw

PATCH v2 2/2 ARM: socfpga: rename the cyclone5 and arria5 base address file

From: Dinh Nguyen <[email protected]>

When adding support for the Arria10 platform, we're going to name the file base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.

Signed-off-by Dinh Nguyen <[email protected]>

---
 .../mach-socfpga/include/mach/{socfpga_base_addrs.h => base_addr_ac5.h} | 0
 include/configs/socfpga_arria5_socdk.h                                  | 2 +-
 include/configs/socfpga_cyclone5_socdk.h                                | 2 +-
 include/configs/socfpga_de0_nano_soc.h                                  | 2 +-
 include/configs/socfpga_mcvevk.h                                        | 2 +-
 include/configs/socfpga_sockit.h                                        | 2 +-
 6 files changed, 5 insertions(+), 5 deletions(-)
 rename arch/arm/mach-socfpga/include/mach/{socfpga_base_addrs.h => base_addr_ac5.h} (100%)

arch/arm/mach-socfpga/include/mach/base_addr_ac5.h renamed from arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h +0 -0

similarity index 100%
rename from arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_ac5.h

include/configs/socfpga_arria5_socdk.h +1 -1

index 8364c66..91ecbf7 100644
@@ -6,7 +6,7 @@
 #ifndef __CONFIG_SOCFPGA_ARRIA5_H__
 #define __CONFIG_SOCFPGA_ARRIA5_H__
 
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

include/configs/socfpga_cyclone5_socdk.h +1 -1

index 86b53e2..b5cf393 100644
@@ -6,7 +6,7 @@
 #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
 #define __CONFIG_SOCFPGA_CYCLONE5_H__
 
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

include/configs/socfpga_de0_nano_soc.h +1 -1

index 3ae9b3e..b371a9b 100644
@@ -6,7 +6,7 @@
 #ifndef __CONFIG_TERASIC_DE0_H__
 #define __CONFIG_TERASIC_DE0_H__
 
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

include/configs/socfpga_mcvevk.h +1 -1

index 4b270ce..d051eec 100644
@@ -6,7 +6,7 @@
 #ifndef __CONFIG_DENX_MCVEVK_H__
 #define __CONFIG_DENX_MCVEVK_H__
 
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

include/configs/socfpga_sockit.h +1 -1

index 742c5ae..d26f53d 100644
@@ -6,7 +6,7 @@
 #ifndef __CONFIG_TERASIC_SOCKIT_H__
 #define __CONFIG_TERASIC_SOCKIT_H__
 
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

Signature · 1 line

2.6.2

Chin Liang See

2015-11-24 08:51 UTC #2 lore raw

PATCH v2 2/2 ARM: socfpga: rename the cyclone5 and arria5 base address file

Quoted 11 lines · dinguyen at opensource.altera.com

From: Dinh Nguyen <[email protected]>
When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by Marek Vasut <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
---

Acked-by Chin Liang See <[email protected]>

Thanks
Chin Liang

Chin Liang See

2015-11-24 08:49 UTC #3 lore raw

PATCH v2 1/2 ARM: socfpga: arria10: add base address map for Arria10

In reply to dinguyen at opensource.altera.com

Quoted 10 lines · dinguyen at opensource.altera.com

From: Dinh Nguyen <[email protected]>
Add the base address map for Arria10.
Signed-off-by Dinh Nguyen <[email protected]>
Reviewed-by Marek Vasut <[email protected]>
---
v2: renamed to base_addr_a10.h
---

Acked-by Chin Liang See <[email protected]>

Thanks
Chin Liang

Marek Vasut

Applied

2015-11-24 15:43 UTC #4 lore raw

PATCH v2 1/2 ARM: socfpga: arria10: add base address map for Arria10

In reply to dinguyen at opensource.altera.com

Quoted 8 lines · dinguyen at opensource.altera.com

From: Dinh Nguyen <[email protected]>
Add the base address map for Arria10.
Signed-off-by Dinh Nguyen <[email protected]>
Reviewed-by Marek Vasut <[email protected]>
---
v2: renamed to base_addr_a10.h

Applied both, thanks!

Best regards,
Marek Vasut