drm/i915: Add DPI FIFO empty status check
Subsystems (2)
PATCH 1/3 drm/i915: Add DPI FIFO empty status check
From: Gaurav K Singh <[email protected]>
After sending SHUTDOWN or TURN ON packet,check the DPI FIFO empty status.
--- drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/gpu/drm/i915/intel_dsi.c +6 -0
@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,else cmd |=DPI_LP_MODE ; + mask =DPI_FIFO_EMPTY ; + +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) & mask) + == mask,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +/* clear bit */ I915_WRITE (MIPI_INTR_STAT (port),SPL_PKT_SENT_INTERRUPT );
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PATCH 2/3 drm/i915: Correct the Ref clock value for BXT
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the correct value here.
--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/i915/i915_reg.h +1 -1
@@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {#define BXT_DSI_PLL_RATIO_MAX 0x7D#define BXT_DSI_PLL_RATIO_MIN 0x22#define BXT_DSI_PLL_RATIO_MASK 0xFF -#define BXT_REF_CLOCK_KHZ 19500 +#define BXT_REF_CLOCK_KHZ 19200#define BXT_DSI_PLL_ENABLE 0x46080#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
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Re: [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT
Quoted 13 lines · Deepak M
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the correct value here.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/gpu/drm/i915/i915_reg.h +0
-0
drivers/gpu/drm/i915/i915_reg.h enum skl_disp_power_wells { · line 7679
Quoted 5 lines
drivers/gpu/drm/i915/i915_reg.h +1
-1@@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {#define BXT_DSI_PLL_RATIO_MAX 0x7D#define BXT_DSI_PLL_RATIO_MIN 0x22#define BXT_DSI_PLL_RATIO_MASK 0xFF -#define BXT_REF_CLOCK_KHZ 19500 +#define BXT_REF_CLOCK_KHZ 19200
No idea why we have this define in i915_reg.h. We don't have such defines for other platforms (also my fix CHV refclk to 19.2MHz patch never got reviewed by anyone either. Interedted?)
Quoted 10 lines
drivers/gpu/drm/i915/i915_reg.h +0
-0#define BXT_DSI_PLL_ENABLE 0x46080#define BXT_DSI_PLL_DO_ENABLE (1 << 31)Signature · 6 lines
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Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter
AppliedRe: [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT
Quoted 9 lines · Ville Syrjälä
Quoted 8 lines · Deepak M
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the correct value here.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Quoted 14 lines
drivers/gpu/drm/i915/i915_reg.h enum skl_disp_power_wells { · line 7679
Quoted 10 lines
drivers/gpu/drm/i915/i915_reg.h +1
-1@@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {#define BXT_DSI_PLL_RATIO_MAX 0x7D#define BXT_DSI_PLL_RATIO_MIN 0x22#define BXT_DSI_PLL_RATIO_MASK 0xFF -#define BXT_REF_CLOCK_KHZ 19500 +#define BXT_REF_CLOCK_KHZ 19200No idea why we have this define in
i915_reg.h. We don't have such defines for other platforms (also my fix CHV refclk to 19.2MHz patch never got reviewed by anyone either. Interedted?)
Add link and I think Deepak is volunteered ;-)
Quoted 2 lines
Reviewed-by Ville Syrjälä <[email protected]>
Queued for -next, thanks for the patch.
-Daniel
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drivers/gpu/drm/i915/i915_reg.h +0
-0#define BXT_DSI_PLL_ENABLE 0x46080#define BXT_DSI_PLL_DO_ENABLE (1 << 31)Signature · 6 lines
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Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT
Quoted 36 lines
-----Original Message-----
From: Daniel Vetter [mailto:[email protected]] On Behalf Of Daniel Vetter
Sent: Friday, December 4, 2015 9:52 PM
To: Ville Syrjälä <[email protected]>
Cc: Deepak, M <[email protected]>; [email protected]
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: Correct the Ref clock value for BXTQuoted 9 lines · Ville Syrjälä
Quoted 8 lines · Deepak M
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the correct value here.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)Quoted 14 lines
drivers/gpu/drm/i915/i915_reg.h enum skl_disp_power_wells { · line 7679
Quoted 10 lines
(quoted diff) +0
-0
b/drivers/gpu/drm/i915/i915_reg.hindex 8bd2699..009f474 100644drivers/gpu/drm/i915/i915_reg.h +1
-1@@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {#define BXT_DSI_PLL_RATIO_MAX 0x7D#define BXT_DSI_PLL_RATIO_MIN 0x22#define BXT_DSI_PLL_RATIO_MASK 0xFF -#define BXT_REF_CLOCK_KHZ 19500 +#define BXT_REF_CLOCK_KHZ 19200No idea why we have this define in
i915_reg.h. We don't have such defines for other platforms (also my fix CHV refclk to 19.2MHz patch never got reviewed by anyone either. Interedted?)
Quoted 2 lines
Add link and I think Deepak is volunteered ;-)
Quoted 1 line
[Deepak, M] Please share the link, I can go through the patch :)
Quoted 24 lines
Quoted 1 line
Reviewed-by Ville Syrjälä <[email protected]>Queued for -next, thanks for the patch.
-DanielQuoted 12 lines
Quoted 11 lines
drivers/gpu/drm/i915/i915_reg.h +0
-1#define BXT_DSI_PLL_ENABLE 0x46080#define BXT_DSI_PLL_DO_ENABLE (1 << 31) --1.9.1
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Ville Syrjälä
Intel OTC
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Quoted 4 lines
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Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT
Quoted 36 lines · On Fri, Dec 04, 2015 at 04:25:19PM +0000, Deepak, M wrote:
Quoted 36 lines
-----Original Message-----
From: Daniel Vetter [mailto:[email protected]] On Behalf Of Daniel Vetter
Sent: Friday, December 4, 2015 9:52 PM
To: Ville Syrjälä <[email protected]>
Cc: Deepak, M <[email protected]>; [email protected]
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: Correct the Ref clock value for BXTQuoted 23 lines · Ville Syrjälä
Quoted 13 lines · Deepak M
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the correct value here.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)(quoted diff) +0
-0
b/drivers/gpu/drm/i915/i915_reg.hindex 8bd2699..009f474 100644drivers/gpu/drm/i915/i915_reg.h enum skl_disp_power_wells { · line 7679
Quoted 5 lines
drivers/gpu/drm/i915/i915_reg.h +1
-1@@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {#define BXT_DSI_PLL_RATIO_MAX 0x7D#define BXT_DSI_PLL_RATIO_MIN 0x22#define BXT_DSI_PLL_RATIO_MASK 0xFF -#define BXT_REF_CLOCK_KHZ 19500 +#define BXT_REF_CLOCK_KHZ 19200No idea why we have this define in
i915_reg.h. We don't have such defines for other platforms (also my fix CHV refclk to 19.2MHz patch never got reviewed by anyone either. Interedted?)
Quoted 3 lines
Quoted 2 lines
Add link and I think Deepak is volunteered ;-)
Quoted 1 line
[Deepak, M] Please share the link, I can go through the patch :)
This is the whole series:
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075097.html
Some of it might have bitrotted a bit, but nothing a rebase wouldn't fix I think.
There's also this other patch dealing with dual-link (which I've never tested due to lack of hardware):
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075568.html
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Reviewed-by Ville Syrjälä <[email protected]>Queued for -next, thanks for the patch.
-DanielQuoted 12 lines
Quoted 11 lines
drivers/gpu/drm/i915/i915_reg.h +0
-1#define BXT_DSI_PLL_ENABLE 0x46080#define BXT_DSI_PLL_DO_ENABLE (1 << 31) --1.9.1
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Ville Syrjälä
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PATCH 3/3 drm/i915: Use the ceil value for the additional clk divider
In reply to Deepak MAdditional clock value divider should use the ceil value of the calulation to get the correct divider value.
--- drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_dsi_pll.c +1 -1
@@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) /2 ;/* Max possible output of clock is 39.5 MHz, program value -1 */ - divider = (dsi_rate /BXT_MAX_VAR_OUTPUT_KHZ ) -1 ; + divider =DIV_ROUND_UP (dsi_rate,BXT_MAX_VAR_OUTPUT_KHZ ) -1 ; tmp |=BXT_MIPI_ESCLK_VAR_DIV (port, divider);/*
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Re: [PATCH 3/3] drm/i915: Use the ceil value for the additional clk divider
Quoted 13 lines · Deepak M
Additional clock value divider should use the ceil value of the calulation to get the correct divider value.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dsi_pll.c +0
-0
drivers/gpu/drm/i915/intel_dsi_pll.c static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) · line 457
Quoted 5 lines
drivers/gpu/drm/i915/intel_dsi_pll.c +1
-1@@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) /2 ;/* Max possible output of clock is 39.5 MHz, program value -1 */ - divider = (dsi_rate /BXT_MAX_VAR_OUTPUT_KHZ ) -1 ; + divider =DIV_ROUND_UP (dsi_rate,BXT_MAX_VAR_OUTPUT_KHZ ) -1 ;
I can't find anything to support the 39.5 MHz claim above. I do know the tx escape clock should be <=20Mhz, so with the /2 extra divider it seems we should aim for <=40Mhz here. So yes, round up does make sense, but it seems to me that BXT_MAX_VAR_OUTPUT_KHZ should be 40 MHz.
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi_pll.c +0
-0tmp |=BXT_MIPI_ESCLK_VAR_DIV (port, divider);/* Signature · 6 lines
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Re: [PATCH 3/3] drm/i915: Use the ceil value for the additional clk divider
Quoted 33 lines
-----Original Message-----
From: Ville Syrjälä [mailto:[email protected]]
Sent: Friday, December 4, 2015 5:22 PM
To: Deepak, M <[email protected]>
Cc: [email protected]
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use the ceil value for the additional clk dividerdrivers/gpu/drm/i915/intel_dsi_pll.c static void bxt_dsi_program_clocks(struct
Quoted 14 lines · Deepak M
Additional clock value divider should use the ceil value of the calulation to get the correct divider value.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dsi_pll.c +0
-0@@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct
drm_device*dev, enum port port)drivers/gpu/drm/i915/intel_dsi_pll.c static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
Quoted 5 lines
drivers/gpu/drm/i915/intel_dsi_pll.c +1
-1dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) /2 ;/* Max possible output of clock is 39.5 MHz, program value -1 */ - divider = (dsi_rate /BXT_MAX_VAR_OUTPUT_KHZ ) -1 ; + divider = DIV_ROUND_UP(dsi_rate, BXT_MAX_VAR_OUTPUT_KHZ) -1;
Quoted 5 lines
I can't find anything to support the 39.5 MHz claim above. I do know the tx escape clock should be <=20Mhz, so with the /2 extra divider it seems we should aim for <=40Mhz here. So yes, round up does make sense, but it seems to me that
BXT_MAX_VAR_OUTPUT_KHZshould be 40 MHz.
[Deepak, M] Yes, thought about it and me too feel that it should be 40 MHz. We locally have tried with 2 different MIPI panels with 39.5 Mhz and didn't see any issue. I will confirm with SV teams and will update the patch accordingly. Thanks for pointing it :)
Quoted 6 lines
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drivers/gpu/drm/i915/intel_dsi_pll.c +0
-1tmp |=BXT_MIPI_ESCLK_VAR_DIV (port, divider);/* -- 1.9.1
Quoted 8 lines
Quoted 4 lines
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Quoted 15 lines · Deepak M
From: Gaurav K Singh <[email protected]>
After sending SHUTDOWN or TURN ON packet,check the DPI FIFO empty status.
Signed-off-by Gaurav K Singh <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/gpu/drm/i915/intel_dsi.c +0
-0
drivers/gpu/drm/i915/intel_dsi.c static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, · line 230
Quoted 9 lines
drivers/gpu/drm/i915/intel_dsi.c +6
-0@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,else cmd |=DPI_LP_MODE ; + mask =DPI_FIFO_EMPTY ; + +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) & mask) + == mask,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +
This checks for it _before_ sending the command, but the commit message says "after". Which is it supposed to be?
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi.c +0
-0/* clear bit */ I915_WRITE (MIPI_INTR_STAT (port),SPL_PKT_SENT_INTERRUPT );Signature · 6 lines
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Quoted 32 lines
-----Original Message-----
From: Ville Syrjälä [mailto:[email protected]]
Sent: Friday, December 4, 2015 3:20 PM
To: Deepak, M <[email protected]>
Cc: [email protected]; Gaurav K Singh <[email protected]>
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add DPI FIFO empty status checkdrivers/gpu/drm/i915/intel_dsi.c static int dpi_send_cmd(struct intel_dsi *intel_dsi,
Quoted 16 lines · Deepak M
From: Gaurav K Singh <[email protected]>
After sending SHUTDOWN or TURN ON packet,check the DPI FIFO empty status.
Signed-off-by Gaurav K Singh <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/gpu/drm/i915/intel_dsi.c +0
-0@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi,u32 cmd, bool hs,
Quoted 3 lines
drivers/gpu/drm/i915/intel_dsi.c +0
-0else cmd |=DPI_LP_MODE ;
Quoted 9 lines
drivers/gpu/drm/i915/intel_dsi.c static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, · line 230
Quoted 6 lines
drivers/gpu/drm/i915/intel_dsi.c +6
-0+ mask =DPI_FIFO_EMPTY ; + +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) & mask) + == mask,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +This checks for it _before_ sending the command, but the commit message says "after". Which is it supposed to be?
[Deepak, M] The check should be before, mistake in the commit message.
Quoted 7 lines
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drivers/gpu/drm/i915/intel_dsi.c +0
-1/* clear bit */ I915_WRITE (MIPI_INTR_STAT (port),SPL_PKT_SENT_INTERRUPT ); --1.9.1
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Quoted 4 lines
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PATCH 1/1 drm/i915: Add DPI FIFO empty status check
In reply to Ville SyrjäläFrom: Gaurav K Singh <[email protected]>
Before sending TURN ON packet,check the DPI
FIFO empty status.
v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.
---
Got to know about the patch where they are removing this DPI FIFO empty check while sending the SHUTDOWN packet.
http://lists.freedesktop.org/archives/intel-gfx/2014-July/048401.html
According added the check and waiting for DPI FIFIO empty only when TURN_ON packet is sent.
drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/gpu/drm/i915/intel_dsi.c +6 -0
@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,else cmd |=DPI_LP_MODE ; + mask =DPI_FIFO_EMPTY ; + +if ((cmd &TURN_ON ) &&wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) & + mask) == mask,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +/* clear bit */ I915_WRITE (MIPI_INTR_STAT (port),SPL_PKT_SENT_INTERRUPT );
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Quoted 10 lines · Deepak M
From: Gaurav K Singh <[email protected]>
Before sending TURN ON packet,check the DPI
FIFO empty status.v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.Signed-off-by Gaurav K Singh <[email protected]>Signed-off-by Deepak M <[email protected]>
Quoted 8 lines
---
Got to know about the patch where they are removing this DPI FIFO empty check while sending the SHUTDOWN packet.http://lists.freedesktop.org/archives/intel-gfx/2014-July/048401.html
According added the check and waiting for DPI FIFIO empty only when
TURN_ONpacket is sent.
Would seem cleaner to add a small function to do the wait, and just call that before calling dpi_send_cmd(TURN_ON).
Quoted 28 lines
drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/gpu/drm/i915/intel_dsi.c +6
-0@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,else cmd |=DPI_LP_MODE ; + mask =DPI_FIFO_EMPTY ; + +if ((cmd &TURN_ON ) &&wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) & + mask) == mask,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +/* clear bit */ I915_WRITE (MIPI_INTR_STAT (port),SPL_PKT_SENT_INTERRUPT );Signature · 6 lines
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PATCH 1/1 drm/i915: Add DPI FIFO empty status check
From: Gaurav K Singh <[email protected]>
Before sending TURN ON packet,check the DPI
FIFO empty status.
v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.
v3: Adding a new function for DPI FIFO empty check
--- drivers/gpu/drm/i915/intel_dsi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_dsi.c +14 -1
@@ -60,6 +60,17 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)DRM_ERROR ("DPI FIFOs are not empty\n" ); } +static void wait_for_dpi_fifo_empty (struct intel_dsi *intel_dsi,enum port port) +{ +struct drm_encoder *encoder = &intel_dsi->base.base; +struct drm_device *dev = encoder->dev; +struct drm_i915_private *dev_priv = dev->dev_private; + +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) &DPI_FIFO_EMPTY ) + ==DPI_FIFO_EMPTY ,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +} +static void write_data (struct drm_i915_private *dev_priv,u32 reg,const u8 *data,u32 len) {
@@ -443,8 +454,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder)I915_WRITE (MIPI_MAX_RETURN_PKT_SIZE (port),8 *4 ); }else {msleep (20 );/* XXX */ -for_each_dsi_port (port, intel_dsi->ports) +for_each_dsi_port (port, intel_dsi->ports) { +wait_for_dpi_fifo_empty (intel_dsi, port);dpi_send_cmd (intel_dsi,TURN_ON , false, port); + }msleep (100 );drm_panel_enable (intel_dsi->panel);
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Quoted 20 lines · Deepak M
From: Gaurav K Singh <[email protected]>
Before sending TURN ON packet,check the DPI
FIFO empty status.v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.
v3: Adding a new function for DPI FIFO empty checkSigned-off-by Gaurav K Singh <[email protected]>Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dsi.c +0
-0
drivers/gpu/drm/i915/intel_dsi.c static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) · line 67
Quoted 8 lines
drivers/gpu/drm/i915/intel_dsi.c +5
-0@@ -60,6 +60,17 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)DRM_ERROR ("DPI FIFOs are not empty\n" ); } +static void wait_for_dpi_fifo_empty (struct intel_dsi *intel_dsi,enum port port) +{ +struct drm_encoder *encoder = &intel_dsi->base.base; +struct drm_device *dev = encoder->dev; +struct drm_i915_private *dev_priv = dev->dev_private;
Passing in intel_dsi just to dig out the dev_priv again seems a bit pointless. Could just pass dev_priv directly. But I guess it matches the already existing functions.
BTW for future reference, we would rather see to_i915(<whatever>) instead of <whatever>->dev_private.
Anyway, the patch seems to do what it says. I can't really judge whether it's the right thing to do though.
Quoted 28 lines
drivers/gpu/drm/i915/intel_dsi.c +9
-1+ +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) &DPI_FIFO_EMPTY ) + ==DPI_FIFO_EMPTY ,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +} +static void write_data (struct drm_i915_private *dev_priv,u32 reg,const u8 *data,u32 len) {@@ -443,8 +454,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder)I915_WRITE (MIPI_MAX_RETURN_PKT_SIZE (port),8 *4 ); }else {msleep (20 );/* XXX */ -for_each_dsi_port (port, intel_dsi->ports) +for_each_dsi_port (port, intel_dsi->ports) { +wait_for_dpi_fifo_empty (intel_dsi, port);dpi_send_cmd (intel_dsi,TURN_ON , false, port); + }msleep (100 );drm_panel_enable (intel_dsi->panel);Signature · 6 lines
1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 34 lines · Ville Syrjälä
Quoted 20 lines · Deepak M
From: Gaurav K Singh <[email protected]>
Before sending TURN ON packet,check the DPI
FIFO empty status.v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.
v3: Adding a new function for DPI FIFO empty checkSigned-off-by Gaurav K Singh <[email protected]>Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dsi.c +0
-0drivers/gpu/drm/i915/intel_dsi.c static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) · line 67
Quoted 8 lines
drivers/gpu/drm/i915/intel_dsi.c +5
-0@@ -60,6 +60,17 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)DRM_ERROR ("DPI FIFOs are not empty\n" ); } +static void wait_for_dpi_fifo_empty (struct intel_dsi *intel_dsi,enum port port) +{ +struct drm_encoder *encoder = &intel_dsi->base.base; +struct drm_device *dev = encoder->dev; +struct drm_i915_private *dev_priv = dev->dev_private;Passing in
intel_dsijust to dig out thedev_privagain seems a bit pointless. Could just passdev_privdirectly. But I guess it matches the already existing functions.
Quoted 2 lines
BTW for future reference, we would rather see
to_i915(<whatever>)instead of <whatever>->dev_private.
Yeah I think fixing up the above would be good. We're pretty close to being able to embed our device structure.
-Daniel
Quoted 42 lines
Anyway, the patch seems to do what it says. I can't really judge whether it's the right thing to do though.
Reviewed-by Ville Syrjälä <[email protected]>Quoted 28 lines
drivers/gpu/drm/i915/intel_dsi.c +9
-1+ +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) &DPI_FIFO_EMPTY ) + ==DPI_FIFO_EMPTY ,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +} +static void write_data (struct drm_i915_private *dev_priv,u32 reg,const u8 *data,u32 len) {@@ -443,8 +454,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder)I915_WRITE (MIPI_MAX_RETURN_PKT_SIZE (port),8 *4 ); }else {msleep (20 );/* XXX */ -for_each_dsi_port (port, intel_dsi->ports) +for_each_dsi_port (port, intel_dsi->ports) { +wait_for_dpi_fifo_empty (intel_dsi, port);dpi_send_cmd (intel_dsi,TURN_ON , false, port); + }msleep (100 );drm_panel_enable (intel_dsi->panel);Signature · 6 lines
1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfxSignature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 34 lines · Ville Syrjälä
Quoted 20 lines · Deepak M
From: Gaurav K Singh <[email protected]>
Before sending TURN ON packet,check the DPI
FIFO empty status.v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.
v3: Adding a new function for DPI FIFO empty checkSigned-off-by Gaurav K Singh <[email protected]>Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dsi.c +0
-0drivers/gpu/drm/i915/intel_dsi.c static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) · line 67
Quoted 8 lines
drivers/gpu/drm/i915/intel_dsi.c +5
-0@@ -60,6 +60,17 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)DRM_ERROR ("DPI FIFOs are not empty\n" ); } +static void wait_for_dpi_fifo_empty (struct intel_dsi *intel_dsi,enum port port) +{ +struct drm_encoder *encoder = &intel_dsi->base.base; +struct drm_device *dev = encoder->dev; +struct drm_i915_private *dev_priv = dev->dev_private;Passing in
intel_dsijust to dig out thedev_privagain seems a bit pointless. Could just passdev_privdirectly. But I guess it matches the already existing functions.
Quoted 7 lines
BTW for future reference, we would rather see
to_i915(<whatever>)instead of <whatever>->dev_private.Anyway, the patch seems to do what it says. I can't really judge whether it's the right thing to do though.
Reviewed-by Ville Syrjälä <[email protected]>
OTOH,
commit a799a9780eb5c874d9d7ca0bbee66401ca98c013
Author: Shobhit Kumar <[email protected]> Date: Thu Jul 3 16:35:40 2014 +0530
drm/i915/vlv: DPI FIFO empty check is not needed
While sending DPI SHUTDOWN command, we cannot wait for FIFO empty as pipes are not disabled at that time. In case of MIPI we disable port first and send SHUTDOWN command while pipe is still running and FIFOs will not be empty, causing spurious error log
Quoted 29 lines
Quoted 29 lines
drivers/gpu/drm/i915/intel_dsi.c +9
-1+ +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) &DPI_FIFO_EMPTY ) + ==DPI_FIFO_EMPTY ,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +} +static void write_data (struct drm_i915_private *dev_priv,u32 reg,const u8 *data,u32 len) {@@ -443,8 +454,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder)I915_WRITE (MIPI_MAX_RETURN_PKT_SIZE (port),8 *4 ); }else {msleep (20 );/* XXX */ -for_each_dsi_port (port, intel_dsi->ports) +for_each_dsi_port (port, intel_dsi->ports) { +wait_for_dpi_fifo_empty (intel_dsi, port);dpi_send_cmd (intel_dsi,TURN_ON , false, port); + }msleep (100 );drm_panel_enable (intel_dsi->panel);Signature · 6 lines
1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 5 lines · Deepak M
From: Gaurav K Singh <[email protected]>
After sending SHUTDOWN or TURN ON packet,check the DPI FIFO empty status.
Quoted 12 lines
Signed-off-by Gaurav K Singh <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/gpu/drm/i915/intel_dsi.c +0
-0@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,else cmd |=DPI_LP_MODE ;
drivers/gpu/drm/i915/intel_dsi.c static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, · line 233
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi.c +6
-0+ mask =DPI_FIFO_EMPTY ; + +if (wait_for ((I915_READ (MIPI_GEN_FIFO_STAT (port)) & mask) + == mask,50 )) +DRM_ERROR ("Timeout waiting for DPI FIFO empty\n" ); +/* clear bit */ I915_WRITE (MIPI_INTR_STAT (port),SPL_PKT_SENT_INTERRUPT );
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