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net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF

PATCH Superseded Marek Vasut 2 participants 17 messages Dec 5, 2015 – Dec 7, 2015

Subsystems (3)
Network drivers Arm (32-bit) Ethernet PHY
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Marek Vasut

author
#0 lore raw

PATCH 1/7 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF

Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 drivers/net/phy/micrel.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 126 insertions(+), 1 deletion(-)
drivers/net/phy/micrel.c +126 -1
index 5e49666..a379230 100644
@@ -9,9 +9,14 @@
  */
 #include <config.h>
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
 #include <micrel.h>
 #include <phy.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static struct phy_driver KSZ804_driver = {
 	.name = "Micrel KSZ804",
 	.uid = 0x221510,

@@ -174,6 +179,58 @@ static int ksz90xx_startup(struct phy_device *phydev)
 	return 0;
 }
 
+/* Common OF config bits for KSZ9021 and KSZ9031 */
+#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
+#ifdef CONFIG_DM_ETH
+struct ksz90x1_ofcfg {
+	u16		reg;
+	u16		devad;
+	const char	**grp;
+	u16		grpsz;
+};
+
+static const char *ksz90x1_rxd_grp[] =
+	{ "rxd0-skew-ps", "rxd1-skew-ps", "rxd2-skew-ps", "rxd3-skew-ps" };
+static const char *ksz90x1_txd_grp[] =
+	{ "txd0-skew-ps", "txd1-skew-ps", "txd2-skew-ps", "txd3-skew-ps" };
+
+static int ksz90x1_of_config_group(struct phy_device *phydev,
+				   struct ksz90x1_ofcfg *ofcfg)
+{
+	struct udevice *dev = phydev->dev;
+	struct phy_driver *drv = phydev->drv;
+	const int ps_to_regval = 200;
+	int val[4];
+	int i, changed = 0;
+	u16 regval = 0;
+
+	if (!drv || !drv->writeext)
+		return -EOPNOTSUPP;
+
+	for (i = 0; i < ofcfg->grpsz; i++) {
+		val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+					 ofcfg->grp[i], -1);
+		if (val[i] == -1) {
+			/* Default register value for KSZ9021 */
+			regval |= 0x7 << (4 * i);
+		} else {
+			changed = 1;	/* Value was changed in OF */
+			/* Calculate the register value and fix corner cases */
+			if (val[i] > ps_to_regval * 0xf)
+				regval |= 0xf << (4 * i);
+			else
+				regval |= (val[i] / ps_to_regval) << (4 * i);
+		}
+	}
+
+	if (!changed)
+		return 0;
+
+	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
+}
+#endif
+#endif
+
 #ifdef CONFIG_PHY_MICREL_KSZ9021
 /*
  * KSZ9021

@@ -188,6 +245,33 @@ static int ksz90xx_startup(struct phy_device *phydev)
 #define CTRL1000_CONFIG_MASTER		(1 << 11)
 #define CTRL1000_MANUAL_CONFIG		(1 << 12)
 
+#ifdef CONFIG_DM_ETH
+static const char *ksz9021_clk_grp[] =
+	{ "txen-skew-ps", "txc-skew-ps", "rxdv-skew-ps", "rxc-skew-ps" };
+
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+	struct ksz90x1_ofcfg ofcfg[] = {
+		{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
+		{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
+		{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
+	};
+	int i, ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+		if (ret)
+			return ret;
+
+	return 0;
+}
+#else
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+	return 0;
+}
+#endif
+
 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
 {
 	/* extended registers */

@@ -224,6 +308,11 @@ static int ksz9021_config(struct phy_device *phydev)
 	const unsigned master = CTRL1000_PREFER_MASTER |
 			CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
 	unsigned features = phydev->drv->features;
+	int ret;
+
+	ret = ksz9021_of_config(phydev);
+	if (ret)
+		return ret;
 
 	if (getenv("disable_giga"))
 		features &= ~(SUPPORTED_1000baseT_Half |

@@ -260,6 +349,34 @@ static struct phy_driver ksz9021_driver = {
 #define MII_KSZ9031_MMD_ACCES_CTRL	0x0d
 #define MII_KSZ9031_MMD_REG_DATA	0x0e
 
+#ifdef CONFIG_DM_ETH
+static const char *ksz9031_ctl_grp[] = { "txen-skew-ps", "rxdv-skew-ps" };
+static const char *ksz9031_clk_grp[] = { "txc-skew-ps", "rxc-skew-ps" };
+
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+	struct ksz90x1_ofcfg ofcfg[] = {
+		{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
+		{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
+		{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
+		{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
+	};
+	int i, ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+		if (ret)
+			return ret;
+
+	return 0;
+}
+#else
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+	return 0;
+}
+#endif
+
 /* Accessors to extended registers*/
 int ksz9031_phy_extended_write(struct phy_device *phydev,
 			       int devaddr, int regnum, u16 mode, u16 val)

@@ -304,13 +421,21 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
 					 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
 };
 
+static int ksz9031_config(struct phy_device *phydev)
+{
+	int ret;
+	ret = ksz9031_of_config(phydev);
+	if (ret)
+		return ret;
+	return genphy_config(phydev);
+}
 
 static struct phy_driver ksz9031_driver = {
 	.name = "Micrel ksz9031",
 	.uid  = 0x221620,
 	.mask = 0xfffff0,
 	.features = PHY_GBIT_FEATURES,
-	.config   = &genphy_config,
+	.config   = &ksz9031_config,
 	.startup  = &ksz90xx_startup,
 	.shutdown = &genphy_shutdown,
 	.writeext = &ksz9031_phy_extwrite,
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH 2/7 arm: socfpga: socrates: Add missing PHY skew config

Add missing KSZ9021 PHY skew configuration for the EBV socrates board.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/dts/socfpga_cyclone5_socrates.dts +9 -0
index 05b935d..a18d168 100644
@@ -28,6 +28,15 @@
 &gmac1 {
 	status = "okay";
 	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
 };
 
 &i2c0 {
Signature · 1 line
2.1.4
#2 lore raw

PATCH 2/7 arm: socfpga: socrates: Add missing PHY skew config

Quoted 11 lines · Marek Vasut

Add missing KSZ9021 PHY skew configuration for the EBV socrates board.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
Reviewed-by Chin Liang See <[email protected]>

Thanks
Chin Liang

author
#3 lore raw

PATCH 3/7 arm: socfpga: arria5-socdk: Remove Micrel PHY configuration

In reply to Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 board/altera/arria5-socdk/socfpga.c    | 40 ----------------------------------
 include/configs/socfpga_arria5_socdk.h |  7 ------
 2 files changed, 47 deletions(-)
board/altera/arria5-socdk/socfpga.c +0 -40
index 0fbbc34..ccb1b4b 100644
@@ -12,10 +12,6 @@
 #include <usb/dwc2_udc.h>
 #include <usb_mass_storage.h>
 
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {}

@@ -31,42 +27,6 @@ int board_init(void)
 	return 0;
 }
 
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
include/configs/socfpga_arria5_socdk.h +0 -7
index ebb6ed5..465df54 100644
@@ -47,15 +47,8 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
Signature · 1 line
2.1.4
#4 lore raw

PATCH 3/7 arm: socfpga: arria5-socdk: Remove Micrel PHY configuration

Quoted 7 lines · Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Quoted 6 lines
---
 board/altera/arria5-socdk/socfpga.c    | 40 ------------------------
----------
 include/configs/socfpga_arria5_socdk.h |  7 ------
 2 files changed, 47 deletions(-)
Acked-by Chin Liang See <[email protected]>

Thanks
Chin Liang

author
#5 lore raw

PATCH 4/7 arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration

In reply to Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 board/altera/cyclone5-socdk/socfpga.c    | 40 --------------------------------
 include/configs/socfpga_cyclone5_socdk.h |  7 ------
 2 files changed, 47 deletions(-)
board/altera/cyclone5-socdk/socfpga.c +0 -40
index 0fbbc34..ccb1b4b 100644
@@ -12,10 +12,6 @@
 #include <usb/dwc2_udc.h>
 #include <usb_mass_storage.h>
 
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {}

@@ -31,42 +27,6 @@ int board_init(void)
 	return 0;
 }
 
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
include/configs/socfpga_cyclone5_socdk.h +0 -7
index 67bb35f..5e4a709 100644
@@ -47,15 +47,8 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
Signature · 1 line
2.1.4
#6 lore raw

PATCH 4/7 arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration

Quoted 7 lines · Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Quoted 7 lines
---
 board/altera/cyclone5-socdk/socfpga.c    | 40 ----------------------
----------
 include/configs/socfpga_cyclone5_socdk.h |  7 ------
 2 files changed, 47 deletions(-)
Acked-by Chin Liang See <[email protected]>

Thanks
Chin Liang

author
#7 lore raw

PATCH 5/7 arm: socfpga: de0_nano: Remove Micrel PHY configuration

In reply to Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 board/terasic/de0-nano-soc/socfpga.c   | 50 ----------------------------------
 include/configs/socfpga_de0_nano_soc.h |  3 --
 2 files changed, 53 deletions(-)
board/terasic/de0-nano-soc/socfpga.c +0 -50
index 85700b0..3ccc2a7 100644
@@ -6,10 +6,6 @@
 
 #include <common.h>
 
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {}

@@ -24,49 +20,3 @@ int board_init(void)
 
 	return 0;
 }
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9031
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0x70);
-	if (ret)
-		return ret;
-
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0x7777);
-	if (ret)
-		return ret;
-
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0);
-	if (ret)
-		return ret;
-
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0x03FC);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
include/configs/socfpga_de0_nano_soc.h +0 -3
index 16e146c..870192d 100644
@@ -47,11 +47,8 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
Signature · 1 line
2.1.4
author
#9 lore raw

PATCH 6/7 arm: socfpga: sockit: Remove Micrel PHY configuration

In reply to Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 board/terasic/sockit/socfpga.c   | 40 ----------------------------------------
 include/configs/socfpga_sockit.h |  7 -------
 2 files changed, 47 deletions(-)
board/terasic/sockit/socfpga.c +0 -40
index 0fbbc34..ccb1b4b 100644
@@ -12,10 +12,6 @@
 #include <usb/dwc2_udc.h>
 #include <usb_mass_storage.h>
 
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {}

@@ -31,42 +27,6 @@ int board_init(void)
 	return 0;
 }
 
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
include/configs/socfpga_sockit.h +0 -7
index 5bcee05..c1178ac 100644
@@ -47,15 +47,8 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
Signature · 1 line
2.1.4
#10 lore raw

PATCH 6/7 arm: socfpga: sockit: Remove Micrel PHY configuration

Quoted 7 lines · Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Quoted 7 lines
---
 board/terasic/sockit/socfpga.c   | 40 ------------------------------
----------
 include/configs/socfpga_sockit.h |  7 -------
 2 files changed, 47 deletions(-)
Reviewed-by Chin Liang See <[email protected]>

Thanks
Chin Liang

author
#11 lore raw

PATCH 7/7 arm: socfpga: socrates: Remove Micrel PHY configuration

In reply to Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 board/ebv/socrates/socfpga.c       | 40 --------------------------------------
 include/configs/socfpga_socrates.h |  7 -------
 2 files changed, 47 deletions(-)
board/ebv/socrates/socfpga.c +0 -40
index 0fbbc34..ccb1b4b 100644
@@ -12,10 +12,6 @@
 #include <usb/dwc2_udc.h>
 #include <usb_mass_storage.h>
 
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {}

@@ -31,42 +27,6 @@ int board_init(void)
 	return 0;
 }
 
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
include/configs/socfpga_socrates.h +0 -7
index 16a2a86..de8ced6 100644
@@ -43,15 +43,8 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
Signature · 1 line
2.1.4
#12 lore raw

PATCH 7/7 arm: socfpga: socrates: Remove Micrel PHY configuration

Quoted 7 lines · Marek Vasut

The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Quoted 7 lines
---
 board/ebv/socrates/socfpga.c       | 40 ----------------------------
----------
 include/configs/socfpga_socrates.h |  7 -------
 2 files changed, 47 deletions(-)
Reviewed-by Chin Liang See <[email protected]>

Thanks
Chin Liang

#13 lore raw

PATCH 1/7 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF

In reply to Marek Vasut
Quoted 5 lines · Marek Vasut

Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled.

Nice as I noticed the value in dts was not used previously.

Quoted 61 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 drivers/net/phy/micrel.c | 127
++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 126 insertions(+), 1 deletion(-)
drivers/net/phy/micrel.c +30 -2
index 5e49666..a379230 100644
@@ -9,9 +9,14 @@
  */
 #include <config.h>
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
 #include <micrel.h>
 #include <phy.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static struct phy_driver KSZ804_driver = {
 	.name = "Micrel KSZ804",
 	.uid = 0x221510,

@@ -174,6 +179,58 @@ static int ksz90xx_startup(struct phy_device
 *phydev)
 	return 0;
 }
 
+/* Common OF config bits for KSZ9021 and KSZ9031 */
+#if defined(CONFIG_PHY_MICREL_KSZ9021) ||
 defined(CONFIG_PHY_MICREL_KSZ9031)
+#ifdef CONFIG_DM_ETH
+struct ksz90x1_ofcfg {
+	u16		reg;
+	u16		devad;
+	const char	**grp;
+	u16		grpsz;
+};
+
+static const char *ksz90x1_rxd_grp[] =
+	{ "rxd0-skew-ps", "rxd1-skew-ps", "rxd2-skew-ps", "rxd3-skew
-ps" };
+static const char *ksz90x1_txd_grp[] =
+	{ "txd0-skew-ps", "txd1-skew-ps", "txd2-skew-ps", "txd3-skew
-ps" };
+
+static int ksz90x1_of_config_group(struct phy_device *phydev,
+				   struct ksz90x1_ofcfg *ofcfg)
+{
+	struct udevice *dev = phydev->dev;
+	struct phy_driver *drv = phydev->drv;
+	const int ps_to_regval = 200;
+	int val[4];
+	int i, changed = 0;
+	u16 regval = 0;
+

drivers/net/phy/micrel.c static int ksz90xx_startup(struct phy_device · line 215

Quoted 10 lines
drivers/net/phy/micrel.c +9 -1
+	if (!drv || !drv->writeext)
+		return -EOPNOTSUPP;
+
+	for (i = 0; i < ofcfg->grpsz; i++) {
+		val[i] = fdtdec_get_uint(gd->fdt_blob, dev
->of_offset,
+					 ofcfg->grp[i], -1);
+		if (val[i] == -1) {
+			/* Default register value for KSZ9021 */
+			regval |= 0x7 << (4 * i);

I noticed the KSZ9031 clock skew is having 5 bit with default value 0xF instead 0x7. Probably this default value and bit width should part of structure?

Quoted 10 lines
drivers/net/phy/micrel.c +2 -0
+		} else {
+			changed = 1;	/* Value was changed in

OF */

drivers/net/phy/micrel.c +1 -0
+			/* Calculate the register value and fix

corner cases */

drivers/net/phy/micrel.c +4 -0
+			if (val[i] > ps_to_regval * 0xf)
+				regval |= 0xf << (4 * i);
+			else
+				regval |= (val[i] / ps_to_regval) <<

(4 * i);

Same as above where 9031 clock skew field is 5 bit.

Thanks
Chin Liang

author
#14 lore raw

PATCH 1/7 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF

Quoted 7 lines · Chin Liang See
Quoted 4 lines · Marek Vasut

Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled.

Nice as I noticed the value in dts was not used previously.

The more important thing is that after these patchsets, it's only the DTS that is used, the hard-coded values are gone.

Quoted 4 lines
Quoted 4 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>

[...]

Quoted 11 lines

drivers/net/phy/micrel.c static int ksz90xx_startup(struct phy_device *phydev) · line 215

Quoted 7 lines
drivers/net/phy/micrel.c +6 -1
+	for (i = 0; i < ofcfg->grpsz; i++) {
+		val[i] = fdtdec_get_uint(gd->fdt_blob, dev
->of_offset,
+					 ofcfg->grp[i], -1);
+		if (val[i] == -1) {
+			/* Default register value for KSZ9021 */
+			regval |= 0x7 << (4 * i);

I noticed the KSZ9031 clock skew is having 5 bit with default value 0xF instead 0x7. Probably this default value and bit width should part of structure?

Ew, this might need some more thinking then. Nice catch.

Best regards,
Marek Vasut

author
#15 lore raw

PATCH v2 1/7 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF

In reply to Marek Vasut

Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 drivers/net/phy/micrel.c | 146 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 145 insertions(+), 1 deletion(-)

V2: - Implement struct ksz90x1_reg_field to describe the skew register
fields more accurately.
- Fix RXDV/TXEN skew register default value and offset.

drivers/net/phy/micrel.c +145 -1
index 5e49666..19b6bc7 100644
@@ -9,9 +9,14 @@
  */
 #include <config.h>
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
 #include <micrel.h>
 #include <phy.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static struct phy_driver KSZ804_driver = {
 	.name = "Micrel KSZ804",
 	.uid = 0x221510,

@@ -174,6 +179,73 @@ static int ksz90xx_startup(struct phy_device *phydev)
 	return 0;
 }
 
+/* Common OF config bits for KSZ9021 and KSZ9031 */
+#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
+#ifdef CONFIG_DM_ETH
+struct ksz90x1_reg_field {
+	const char	*name;
+	const u8	size;	/* Size of the bitfield, in bits */
+	const u8	off;	/* Offset from bit 0 */
+	const u8	dflt;	/* Default value */
+};
+
+struct ksz90x1_ofcfg {
+	const u16			reg;
+	const u16			devad;
+	const struct ksz90x1_reg_field	*grp;
+	const u16			grpsz;
+};
+
+static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
+	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
+	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
+};
+
+static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
+	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
+	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz90x1_of_config_group(struct phy_device *phydev,
+				   struct ksz90x1_ofcfg *ofcfg)
+{
+	struct udevice *dev = phydev->dev;
+	struct phy_driver *drv = phydev->drv;
+	const int ps_to_regval = 200;
+	int val[4];
+	int i, changed = 0, offset, max;
+	u16 regval = 0;
+
+	if (!drv || !drv->writeext)
+		return -EOPNOTSUPP;
+
+	for (i = 0; i < ofcfg->grpsz; i++) {
+		val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+					 ofcfg->grp[i].name, -1);
+		offset = ofcfg->grp[i].off;
+		if (val[i] == -1) {
+			/* Default register value for KSZ9021 */
+			regval |= ofcfg->grp[i].dflt << offset;
+		} else {
+			changed = 1;	/* Value was changed in OF */
+			/* Calculate the register value and fix corner cases */
+			if (val[i] > ps_to_regval * 0xf) {
+				max = (1 << ofcfg->grp[i].size) - 1;
+				regval |= max << offset;
+			} else {
+				regval |= (val[i] / ps_to_regval) << offset;
+			}
+		}
+	}
+
+	if (!changed)
+		return 0;
+
+	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
+}
+#endif
+#endif
+
 #ifdef CONFIG_PHY_MICREL_KSZ9021
 /*
  * KSZ9021

@@ -188,6 +260,35 @@ static int ksz90xx_startup(struct phy_device *phydev)
 #define CTRL1000_CONFIG_MASTER		(1 << 11)
 #define CTRL1000_MANUAL_CONFIG		(1 << 12)
 
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
+	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
+	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+	struct ksz90x1_ofcfg ofcfg[] = {
+		{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
+		{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
+		{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
+	};
+	int i, ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+		if (ret)
+			return ret;
+
+	return 0;
+}
+#else
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+	return 0;
+}
+#endif
+
 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
 {
 	/* extended registers */

@@ -224,6 +325,11 @@ static int ksz9021_config(struct phy_device *phydev)
 	const unsigned master = CTRL1000_PREFER_MASTER |
 			CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
 	unsigned features = phydev->drv->features;
+	int ret;
+
+	ret = ksz9021_of_config(phydev);
+	if (ret)
+		return ret;
 
 	if (getenv("disable_giga"))
 		features &= ~(SUPPORTED_1000baseT_Half |

@@ -260,6 +366,36 @@ static struct phy_driver ksz9021_driver = {
 #define MII_KSZ9031_MMD_ACCES_CTRL	0x0d
 #define MII_KSZ9031_MMD_REG_DATA	0x0e
 
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
+	{ { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
+static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
+	{ { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
+
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+	struct ksz90x1_ofcfg ofcfg[] = {
+		{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
+		{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
+		{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
+		{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
+	};
+	int i, ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+		if (ret)
+			return ret;
+
+	return 0;
+}
+#else
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+	return 0;
+}
+#endif
+
 /* Accessors to extended registers*/
 int ksz9031_phy_extended_write(struct phy_device *phydev,
 			       int devaddr, int regnum, u16 mode, u16 val)

@@ -304,13 +440,21 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
 					 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
 };
 
+static int ksz9031_config(struct phy_device *phydev)
+{
+	int ret;
+	ret = ksz9031_of_config(phydev);
+	if (ret)
+		return ret;
+	return genphy_config(phydev);
+}
 
 static struct phy_driver ksz9031_driver = {
 	.name = "Micrel ksz9031",
 	.uid  = 0x221620,
 	.mask = 0xfffff0,
 	.features = PHY_GBIT_FEATURES,
-	.config   = &genphy_config,
+	.config   = &ksz9031_config,
 	.startup  = &ksz90xx_startup,
 	.shutdown = &genphy_shutdown,
 	.writeext = &ksz9031_phy_extwrite,
Signature · 1 line
2.1.4
#16 lore raw

PATCH v2 1/7 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF

Quoted 14 lines · Marek Vasut

Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled.

Signed-off-by Marek Vasut <[email protected]>
Cc Joe Hershberger <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 drivers/net/phy/micrel.c | 146
++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 145 insertions(+), 1 deletion(-)
Quoted 6 lines

V2: - Implement struct ksz90x1_reg_field to describe the skew register
fields more accurately.
- Fix RXDV/TXEN skew register default value and offset.

Acked-by Chin Liang See <[email protected]>

Thanks
Chin Liang