drm/i915: Set the Z inversion overlap field for BXT
Subsystems (2)
PATCH 1/2 drm/i915: Set the Z inversion overlap field for BXT
For broxton dual link Z-inversion overlap field is present in MIPI_CTRL register unlike the other platforms, hence setting the same in this patch.
--- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_dsi.c | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +4 -0
@@ -8107,6 +8107,10 @@ enum skl_disp_power_wells {#define BXT_PIPE_SELECT_B (1 << 7)#define BXT_PIPE_SELECT_A (0 << 7) +/* BXT has dual link Z inversion overlap field */ +#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) +#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 +#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)#define MIPI_DATA_ADDRESS (port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
drivers/gpu/drm/i915/intel_dsi.c +13 -3
@@ -392,11 +392,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)u32 port_ctrl;if (intel_dsi->dual_link ==DSI_DUAL_LINK_FRONT_BACK ) { - temp =I915_READ (VLV_CHICKEN_3 ); - temp &= ~PIXEL_OVERLAP_CNT_MASK | +if (IS_BROXTON (dev)) { +for_each_dsi_port (port, intel_dsi->ports) { + temp =I915_READ (MIPI_CTRL (port)); + temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << +BXT_PIXEL_OVERLAP_CNT_SHIFT ; +I915_WRITE (MIPI_CTRL (port), temp); + } + }else { + temp =I915_READ (VLV_CHICKEN_3 ); + temp &= ~PIXEL_OVERLAP_CNT_MASK | + intel_dsi->pixel_overlap <<PIXEL_OVERLAP_CNT_SHIFT ; -I915_WRITE (VLV_CHICKEN_3 , temp); +I915_WRITE (VLV_CHICKEN_3 , temp); + } }for_each_dsi_port (port, intel_dsi->ports) {
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PATCH 2/2 drm/i915: dual link pipe selection for bxt
Pipe is assigned based on the port, but it should be based on current crtc. Correcting the same in this patch.
--- drivers/gpu/drm/i915/intel_dsi.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-)
drivers/gpu/drm/i915/intel_dsi.c +14 -9
@@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)I915_WRITE (MIPI_CTRL (port), tmp |READ_REQUEST_PRIORITY_HIGH ); }else if (IS_BROXTON (dev)) { -/* -* FIXME: -* BXT can connect any PIPE to any MIPI port. -* Select the pipe based on the MIPI port read from -* VBT for now. Pick PIPE A for MIPI port A and C -* for port C. -*/ +enum pipe pipe = intel_crtc->pipe; + tmp =I915_READ (MIPI_CTRL (port)); tmp &= ~BXT_PIPE_SELECT_MASK ; -if (port ==PORT_A ) +switch (pipe) { +case PIPE_A : tmp |=BXT_PIPE_SELECT_A ; -else if (port ==PORT_C ) +break ; +case PIPE_B : + tmp |=BXT_PIPE_SELECT_B ; +break ; +case PIPE_C : tmp |=BXT_PIPE_SELECT_C ; +break ; +default : +DRM_ERROR ("Unknown pipe used\n" ); +return ; + }I915_WRITE (MIPI_CTRL (port), tmp); }
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Re: [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt
Quoted 29 lines · Deepak M
Pipe is assigned based on the port, but it should be based on current crtc. Correcting the same in this patch.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-)drivers/gpu/drm/i915/intel_dsi.c +2
-8@@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)I915_WRITE (MIPI_CTRL (port), tmp |READ_REQUEST_PRIORITY_HIGH ); }else if (IS_BROXTON (dev)) { -/* -* FIXME: -* BXT can connect any PIPE to any MIPI port. -* Select the pipe based on the MIPI port read from -* VBT for now. Pick PIPE A for MIPI port A and C -* for port C. -*/ +enum pipe pipe = intel_crtc->pipe; + tmp =I915_READ (MIPI_CTRL (port)); tmp &= ~BXT_PIPE_SELECT_MASK ; -if (port ==PORT_A )
drivers/gpu/drm/i915/intel_dsi.c static void intel_dsi_prepare(struct intel_encoder *intel_encoder) · line 914
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi.c +7
-1+switch (pipe) { +case PIPE_A : tmp |=BXT_PIPE_SELECT_A ; - else if (port == PORT_C) +break ; +case PIPE_B : + tmp |=BXT_PIPE_SELECT_B ; +break ; +case PIPE_C : tmp |=BXT_PIPE_SELECT_C ;
Please create a BXT_PIPE_SELECT(pipe) macro like we have for all the other outputs that support more than 1 pipe selection bit. See e.g. DP_PIPE_SELECT_CHV.
-Daniel
Quoted 15 lines
drivers/gpu/drm/i915/intel_dsi.c +5
-0+break ; +default : +DRM_ERROR ("Unknown pipe used\n" ); +return ; + }I915_WRITE (MIPI_CTRL (port), tmp); }Signature · 6 lines
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Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 1/1 drm/i915: dual link pipe selection for bxt
Pipe is assigned based on the port, but it should be based on current crtc. Correcting the same in this patch.
v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel)
--- drivers/gpu/drm/i915/i915_reg.h | 4 +--- drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------ 2 files changed, 4 insertions(+), 15 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +1 -3
@@ -8103,9 +8103,7 @@ enum skl_disp_power_wells {#define RGB_FLIP_TO_BGR (1 << 2)#define BXT_PIPE_SELECT_MASK (7 << 7) -#define BXT_PIPE_SELECT_C (2 << 7) -#define BXT_PIPE_SELECT_B (1 << 7) -#define BXT_PIPE_SELECT_A (0 << 7) +#define BXT_PIPE_SELECT (pipe) ((pipe) << 7)/* BXT has dual link Z inversion overlap field */ #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
drivers/gpu/drm/i915/intel_dsi.c +3 -12
@@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)I915_WRITE (MIPI_CTRL (port), tmp |READ_REQUEST_PRIORITY_HIGH ); }else if (IS_BROXTON (dev)) { -/* -* FIXME: -* BXT can connect any PIPE to any MIPI port. -* Select the pipe based on the MIPI port read from -* VBT for now. Pick PIPE A for MIPI port A and C -* for port C. -*/ +enum pipe pipe = intel_crtc->pipe; + tmp =I915_READ (MIPI_CTRL (port)); tmp &= ~BXT_PIPE_SELECT_MASK ; -if (port ==PORT_A ) - tmp |=BXT_PIPE_SELECT_A ; -else if (port ==PORT_C ) - tmp |=BXT_PIPE_SELECT_C ; - + tmp |=BXT_PIPE_SELECT (pipe);I915_WRITE (MIPI_CTRL (port), tmp); }
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Re: [PATCH] drm/i915: dual link pipe selection for bxt
Quoted 43 lines · Deepak M
Pipe is assigned based on the port, but it should be based on current crtc. Correcting the same in this patch.
v2: Use macro
BXT_PIPE_SELECT(pipe)(Daniel)Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 4 +--- drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------ 2 files changed, 4 insertions(+), 15 deletions(-)drivers/gpu/drm/i915/i915_reg.h +1
-3@@ -8103,9 +8103,7 @@ enum skl_disp_power_wells {#define RGB_FLIP_TO_BGR (1 << 2)#define BXT_PIPE_SELECT_MASK (7 << 7) -#define BXT_PIPE_SELECT_C (2 << 7) -#define BXT_PIPE_SELECT_B (1 << 7) -#define BXT_PIPE_SELECT_A (0 << 7) +#define BXT_PIPE_SELECT (pipe) ((pipe) << 7)/* BXT has dual link Z inversion overlap field */ #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)drivers/gpu/drm/i915/intel_dsi.c +2
-7@@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)I915_WRITE (MIPI_CTRL (port), tmp |READ_REQUEST_PRIORITY_HIGH ); }else if (IS_BROXTON (dev)) { -/* -* FIXME: -* BXT can connect any PIPE to any MIPI port. -* Select the pipe based on the MIPI port read from -* VBT for now. Pick PIPE A for MIPI port A and C -* for port C. -*/ +enum pipe pipe = intel_crtc->pipe; +
drivers/gpu/drm/i915/intel_dsi.c static void intel_dsi_prepare(struct intel_encoder *intel_encoder) · line 907
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi.c +1
-5tmp =I915_READ (MIPI_CTRL (port)); tmp &= ~BXT_PIPE_SELECT_MASK ; -if (port ==PORT_A ) - tmp |=BXT_PIPE_SELECT_A ; -else if (port ==PORT_C ) - tmp |=BXT_PIPE_SELECT_C ; - + tmp |=BXT_PIPE_SELECT (pipe);I915_WRITE (MIPI_CTRL (port), tmp);
There's way too much RMW going on in the DSI code though. Someone should probably do something about it.
Quoted 9 lines
drivers/gpu/drm/i915/intel_dsi.c +0
-0}Signature · 6 lines
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Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter
AppliedRe: [PATCH] drm/i915: dual link pipe selection for bxt
Quoted 57 lines · Ville Syrjälä
Quoted 43 lines · Deepak M
Pipe is assigned based on the port, but it should be based on current crtc. Correcting the same in this patch.
v2: Use macro
BXT_PIPE_SELECT(pipe)(Daniel)Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 4 +--- drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------ 2 files changed, 4 insertions(+), 15 deletions(-)drivers/gpu/drm/i915/i915_reg.h +1
-3@@ -8103,9 +8103,7 @@ enum skl_disp_power_wells {#define RGB_FLIP_TO_BGR (1 << 2)#define BXT_PIPE_SELECT_MASK (7 << 7) -#define BXT_PIPE_SELECT_C (2 << 7) -#define BXT_PIPE_SELECT_B (1 << 7) -#define BXT_PIPE_SELECT_A (0 << 7) +#define BXT_PIPE_SELECT (pipe) ((pipe) << 7)/* BXT has dual link Z inversion overlap field */ #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)drivers/gpu/drm/i915/intel_dsi.c +2
-7@@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)I915_WRITE (MIPI_CTRL (port), tmp |READ_REQUEST_PRIORITY_HIGH ); }else if (IS_BROXTON (dev)) { -/* -* FIXME: -* BXT can connect any PIPE to any MIPI port. -* Select the pipe based on the MIPI port read from -* VBT for now. Pick PIPE A for MIPI port A and C -* for port C. -*/ +enum pipe pipe = intel_crtc->pipe; +drivers/gpu/drm/i915/intel_dsi.c static void intel_dsi_prepare(struct intel_encoder *intel_encoder) · line 907
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi.c +1
-5tmp =I915_READ (MIPI_CTRL (port)); tmp &= ~BXT_PIPE_SELECT_MASK ; -if (port ==PORT_A ) - tmp |=BXT_PIPE_SELECT_A ; -else if (port ==PORT_C ) - tmp |=BXT_PIPE_SELECT_C ; - + tmp |=BXT_PIPE_SELECT (pipe);I915_WRITE (MIPI_CTRL (port), tmp);Reviewed-by Ville Syrjälä <[email protected]>
Quoted 2 lines
There's way too much RMW going on in the DSI code though. Someone should probably do something about it.
Yeah that'd be nice.
Queued for -next, thanks for the patch.
-Daniel
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Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt
In reply to Daniel VetterQuoted 42 lines
-----Original Message-----
From: Daniel Vetter [mailto:[email protected]] On Behalf Of Daniel Vetter
Sent: Wednesday, December 9, 2015 1:50 PM
To: Deepak, M <[email protected]>
Cc: [email protected]
Subject: Re: [Intel-gfx] [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxtdrivers/gpu/drm/i915/intel_dsi.c static void intel_dsi_prepare(struct intel_encoder
Quoted 14 lines · Deepak M
Pipe is assigned based on the port, but it should be based on current crtc. Correcting the same in this patch.
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/intel_dsi.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-)drivers/gpu/drm/i915/intel_dsi.c +0
-0@@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder
*intel_encoder)Quoted 15 lines
drivers/gpu/drm/i915/intel_dsi.c +2
-7I915_WRITE (MIPI_CTRL (port), tmp |READ_REQUEST_PRIORITY_HIGH ); }else if (IS_BROXTON (dev)) { -/* -* FIXME: -* BXT can connect any PIPE to any MIPI port. -* Select the pipe based on the MIPI port read from -* VBT for now. Pick PIPE A for MIPI port A and C -* for port C. -*/ +enum pipe pipe = intel_crtc->pipe; + tmp =I915_READ (MIPI_CTRL (port)); tmp &= ~BXT_PIPE_SELECT_MASK ;
Quoted 17 lines
drivers/gpu/drm/i915/intel_dsi.c static void intel_dsi_prepare(struct intel_encoder *intel_encoder) · line 914
Quoted 11 lines
drivers/gpu/drm/i915/intel_dsi.c +7
-2-if (port ==PORT_A ) +switch (pipe) { +case PIPE_A : tmp |=BXT_PIPE_SELECT_A ; -else if (port ==PORT_C ) +break ; +case PIPE_B : + tmp |=BXT_PIPE_SELECT_B ; +break ; +case PIPE_C : tmp |=BXT_PIPE_SELECT_C ;Please create a
BXT_PIPE_SELECT(pipe)macro like we have for all the other outputs that support more than 1 pipe selection bit. See e.g.DP_PIPE_SELECT_CHV.
-Daniel
[Deepak, M] Agreed, Have tried to address this comment http://lists.freedesktop.org/archives/intel-gfx/2015-December/082431.html
Quoted 11 lines
Quoted 11 lines
drivers/gpu/drm/i915/intel_dsi.c +5
-1+break ; +default : +DRM_ERROR ("Unknown pipe used\n" ); +return ; + }I915_WRITE (MIPI_CTRL (port), tmp); } --1.9.1
Quoted 9 lines
Quoted 4 lines
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Quoted 15 lines · Deepak M
For broxton dual link Z-inversion overlap field is present in
MIPI_CTRLregister unlike the other platforms, hence setting the same in this patch.Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_dsi.c | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/i915_reg.h +0
-0
drivers/gpu/drm/i915/i915_reg.h enum skl_disp_power_wells { · line 8112
Quoted 6 lines
drivers/gpu/drm/i915/i915_reg.h +3
-0@@ -8107,6 +8107,10 @@ enum skl_disp_power_wells {#define BXT_PIPE_SELECT_B (1 << 7)#define BXT_PIPE_SELECT_A (0 << 7) +/* BXT has dual link Z inversion overlap field */ +#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) +#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
This could be parametrized. eg:BXT_PIXEL_OVERLAP_CNT(x) ((x) << 10))
And so could the VLV version.
Quoted 10 lines
drivers/gpu/drm/i915/i915_reg.h +1
-0+#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)#define MIPI_DATA_ADDRESS (port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \drivers/gpu/drm/i915/intel_dsi.c +0
-0@@ -392,11 +392,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)u32 port_ctrl;
drivers/gpu/drm/i915/intel_dsi.c static void intel_dsi_port_enable(struct intel_encoder *encoder) · line 400
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi.c +5
-2if (intel_dsi->dual_link ==DSI_DUAL_LINK_FRONT_BACK ) { - temp =I915_READ (VLV_CHICKEN_3 ); - temp &= ~PIXEL_OVERLAP_CNT_MASK | +if (IS_BROXTON (dev)) { +for_each_dsi_port (port, intel_dsi->ports) { + temp =I915_READ (MIPI_CTRL (port)); + temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << +BXT_PIXEL_OVERLAP_CNT_SHIFT ;
That won't do anything sane.
Quoted 20 lines
drivers/gpu/drm/i915/intel_dsi.c +8
-1+I915_WRITE (MIPI_CTRL (port), temp); + } + }else { + temp =I915_READ (VLV_CHICKEN_3 ); + temp &= ~PIXEL_OVERLAP_CNT_MASK | + intel_dsi->pixel_overlap <<PIXEL_OVERLAP_CNT_SHIFT ; -I915_WRITE (VLV_CHICKEN_3 , temp); +I915_WRITE (VLV_CHICKEN_3 , temp); + } }for_each_dsi_port (port, intel_dsi->ports) {Signature · 6 lines
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Quoted 4 lines · Deepak M
For broxton dual link Z-inversion overlap field is present in
MIPI_CTRLregister unlike the other platforms, hence setting the same in this patch.
Quoted 40 lines
Signed-off-by Deepak M <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_dsi.c | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/i915_reg.h +4
-0@@ -8107,6 +8107,10 @@ enum skl_disp_power_wells {#define BXT_PIPE_SELECT_B (1 << 7)#define BXT_PIPE_SELECT_A (0 << 7) +/* BXT has dual link Z inversion overlap field */ +#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) +#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 +#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)#define MIPI_DATA_ADDRESS (port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \drivers/gpu/drm/i915/intel_dsi.c +8
-2@@ -392,11 +392,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)u32 port_ctrl;if (intel_dsi->dual_link ==DSI_DUAL_LINK_FRONT_BACK ) { - temp =I915_READ (VLV_CHICKEN_3 ); - temp &= ~PIXEL_OVERLAP_CNT_MASK | +if (IS_BROXTON (dev)) { +for_each_dsi_port (port, intel_dsi->ports) { + temp =I915_READ (MIPI_CTRL (port)); + temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << +BXT_PIXEL_OVERLAP_CNT_SHIFT ; +I915_WRITE (MIPI_CTRL (port), temp); + } + }else {
drivers/gpu/drm/i915/intel_dsi.c static void intel_dsi_port_enable(struct intel_encoder *encoder) · line 412
Quoted 10 lines
drivers/gpu/drm/i915/intel_dsi.c +5
-1+ temp =I915_READ (VLV_CHICKEN_3 ); + temp &= ~PIXEL_OVERLAP_CNT_MASK | + intel_dsi->pixel_overlap <<PIXEL_OVERLAP_CNT_SHIFT ; -I915_WRITE (VLV_CHICKEN_3 , temp); +I915_WRITE (VLV_CHICKEN_3 , temp); + } }for_each_dsi_port (port, intel_dsi->ports) {
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