arm64: dts: r8a7795: Add Cortex-A53 CPU cores
Subsystems (3)
PATCH 1/2 arm64: dts: r8a7795: Add Cortex-A53 CPU cores
From: Takeshi Kihara <[email protected]>
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 cores (4 x Cortex-A57 + 4 x Cortex-A53).
---
Note: This patch is picked from
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x
and rebased against
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 46 +++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 7 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +39 -7
@@ -60,6 +60,30 @@ device_type = "cpu"; enable-method = "psci"; }; + a53_0: cpu at 100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + }; + a53_1: cpu at 101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + }; + a53_2: cpu at 102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + enable-method = "psci"; + }; + a53_3: cpu at 103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + enable-method = "psci"; + }; }; extal_clk: extal {
@@ -115,7 +139,7 @@ reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x2000>; interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio at e6050000 {
@@ -235,23 +259,31 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, - <&a57_3>; + <&a57_3>, + <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; cpg: clock-controller at e6150000 {
Signature · 1 line
2.6.4
PATCH 2/2 arm64: dts: r8a7795: Add L2 cache-controller nodes
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).
---
Note: Geert: I picked your patch from
http://www.spinics.net/lists/arm-kernel/msg466628.html
incoporated some review comments and rebased it against
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +16 -0
@@ -39,6 +39,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; };
@@ -46,46 +47,61 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_2: cpu at 2 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x2>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_3: cpu at 3 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x3>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a53_0: cpu at 100 { compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x100>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; a53_1: cpu at 101 { compatible = "arm,cortex-a53","arm,armv8"; reg = <0x101>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; a53_2: cpu at 102 { compatible = "arm,cortex-a53","arm,armv8"; reg = <0x102>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; a53_3: cpu at 103 { compatible = "arm,cortex-a53","arm,armv8"; reg = <0x103>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; }; + L2_CA57: cache-controller at 0 { + compatible = "cache"; + }; + + L2_CA53: cache-controller at 1 { + compatible = "cache"; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;
Signature · 1 line
2.6.4
PATCH 2/2 arm64: dts: r8a7795: Add L2 cache-controller nodes
Hi Dirk,
Quoted 13 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>
Quoted 8 lines
---
Note: Geert: I picked your patch fromhttp://www.spinics.net/lists/arm-kernel/msg466628.html
incoporated some review comments and rebased it against
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1
This is more or less what I have locally, except that I kept the latency properties, pending discussion.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 2/2 arm64: dts: r8a7795: Add L2 cache-controller nodes
Quoted 19 lines · Geert Uytterhoeven
Hi Dirk,
Quoted 16 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>---
Note: Geert: I picked your patch from
Quoted 8 lines
Quoted 5 lines
http://www.spinics.net/lists/arm-kernel/msg466628.html
incoporated some review comments and rebased it against
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1
This is more or less what I have locally, except that I kept the latency properties
Hmm, maybe I missed anything, but the only part reading the latency I can find is
arch/arm/mm/cache-l2x0.c
[1] which isn't relevant for arm64?
Best regards
Dirk
[1]
./arch/arm/mm/cache-l2x0.c:1042: of_property_read_u32(np,
"arm,tag-latency", &tag);./arch/arm/mm/cache-l2x0.c:1143: of_property_read_u32_array(np,
"arm,tag-latency", tag, ARRAY_SIZE(tag));
PATCH 2/2 arm64: dts: r8a7795: Add L2 cache-controller nodes
Hi Dirk,
Quoted 28 lines · Dirk Behme
Quoted 19 lines · Geert Uytterhoeven
Quoted 18 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>---
Note: Geert: I picked your patch fromQuoted 7 lines
Quoted 4 lines
incoporated some review comments and rebased it against
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next
renesas-next-20151211v2-v4.4-rc1This is more or less what I have locally, except that I kept the latency properties
Quoted 6 lines
Hmm, maybe I missed anything, but the only part reading the latency I can find is
arch/arm/mm/cache-l2x0.c[1] which isn't relevant for arm64?
No driver using a property in DT is not a reason not to put the property in DT. The r8a7995 datasheet does contain the latency values to use.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 2/2 arm64: dts: r8a7795: Add L2 cache-controller nodes
Quoted 34 lines · Geert Uytterhoeven
Hi Dirk,
Quoted 31 lines · Dirk Behme
Quoted 19 lines · Geert Uytterhoeven
Quoted 18 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>---
Note: Geert: I picked your patch fromQuoted 7 lines
Quoted 4 lines
incoporated some review comments and rebased it against
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next
renesas-next-20151211v2-v4.4-rc1This is more or less what I have locally, except that I kept the latency properties
Hmm, maybe I missed anything, but the only part reading the latency I can find is
Quoted 7 lines
Quoted 3 lines
arch/arm/mm/cache-l2x0.c[1] which isn't relevant for arm64?
No driver using a property in DT is not a reason not to put the property in DT. The r8a7995 datasheet does contain the latency values to use.
While I agree with that, I would avoid having these values for 2 reasons:
1. Others might blindly copy and expect these setting to done in Linux or any non-secure OS using DT which is clearly not possible on ARM64
2. Going by your argument, we usually have much more in datasheets which are not all in DT, so strictly speaking that's not a reason to have it here.
Again I am not against it, just an opinion.
Signature · 2 lines
Regards, Sudeep
PATCH 1/2 arm64: dts: r8a7795: Add Cortex-A53 CPU cores
In reply to Dirk BehmeHi Dirk,
Quoted 7 lines · Dirk Behme
From: Takeshi Kihara <[email protected]>
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 cores (4 x Cortex-A57 + 4 x Cortex-A53).
Signed-off-by Takeshi Kihara <[email protected]>Signed-off-by Dirk Behme <[email protected]>
Thanks, I can confirm this works.
However, as the scheduler is not big.LITTLE aware (running processes are not migrated automatically to the faster CA57 cores when these are idle), it makes performance less deterministic.
Hence we would like to postpone this.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/2 arm64: dts: r8a7795: Add Cortex-A53 CPU cores
Hi Geert,
Quoted 8 lines · Geert Uytterhoeven
Hi Dirk,
Quoted 5 lines · Dirk Behme
From: Takeshi Kihara <[email protected]>
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 cores (4 x Cortex-A57 + 4 x Cortex-A53).
Quoted 8 lines
Quoted 2 lines
Signed-off-by Takeshi Kihara <[email protected]>Signed-off-by Dirk Behme <[email protected]>Thanks, I can confirm this works.
However, as the scheduler is not big.LITTLE aware (running processes are not migrated automatically to the faster CA57 cores when these are idle), it makes performance less deterministic.
What's the plan, then?
Waiting for big.LITTLE getting merged before enabling the A53? Or not using the A53 at all?
Best regards
Dirk