arm: socfpga: Fix emac1 doesn't work on socdk board
PATCH 1/1 arm: socfpga: Fix emac1 doesn't work on socdk board
Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock.
Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>
--- board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++------------ board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 16 insertions(+), 16 deletions(-)
board/altera/cyclone5-socdk/qts/pinmux_config.h +14 -14
@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {0 ,/* GENERALIO29 */ 0 ,/* GENERALIO30 */ 0 ,/* GENERALIO31 */ -0 ,/* MIXED1IO0 */ -1 ,/* MIXED1IO1 */ -1 ,/* MIXED1IO2 */ -1 ,/* MIXED1IO3 */ -1 ,/* MIXED1IO4 */ -0 ,/* MIXED1IO5 */ -0 ,/* MIXED1IO6 */ -0 ,/* MIXED1IO7 */ -1 ,/* MIXED1IO8 */ -1 ,/* MIXED1IO9 */ -1 ,/* MIXED1IO10 */ -1 ,/* MIXED1IO11 */ -0 ,/* MIXED1IO12 */ -0 ,/* MIXED1IO13 */ +2 ,/* MIXED1IO0 */ +2 ,/* MIXED1IO1 */ +2 ,/* MIXED1IO2 */ +2 ,/* MIXED1IO3 */ +2 ,/* MIXED1IO4 */ +2 ,/* MIXED1IO5 */ +2 ,/* MIXED1IO6 */ +2 ,/* MIXED1IO7 */ +2 ,/* MIXED1IO8 */ +2 ,/* MIXED1IO9 */ +2 ,/* MIXED1IO10 */ +2 ,/* MIXED1IO11 */ +2 ,/* MIXED1IO12 */ +2 ,/* MIXED1IO13 */ 0 ,/* MIXED1IO14 */ 1 ,/* MIXED1IO15 */ 1, /* MIXED1IO16 */
board/altera/cyclone5-socdk/qts/pll_config.h +2 -2
@@ -31,7 +31,7 @@#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
@@ -65,7 +65,7 @@#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000#define CONFIG_HPS_CLK_USBCLK_HZ 200000000#define CONFIG_HPS_CLK_NAND_HZ 50000000#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
Signature · 1 line
1.7.9.5
PATCH 1/1 arm: socfpga: Fix emac1 doesn't work on socdk board
Hi Shengjiang,
Quoted 10 lines · shengjiangwu
Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock.
Signed-off-by shengjiangwu <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Pavel Machek <[email protected]>Cc Marek Vasut <[email protected]>Cc Stefan Roese <[email protected]>
Thanks for the patch.
Quoted 61 lines
--- board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++-- ---------- board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 16 insertions(+), 16 deletions(-)board/altera/cyclone5-socdk/qts/pinmux_config.h +14
-14@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {0 ,/* GENERALIO29 */ 0 ,/* GENERALIO30 */ 0 ,/* GENERALIO31 */ -0 ,/* MIXED1IO0 */ -1 ,/* MIXED1IO1 */ -1 ,/* MIXED1IO2 */ -1 ,/* MIXED1IO3 */ -1 ,/* MIXED1IO4 */ -0 ,/* MIXED1IO5 */ -0 ,/* MIXED1IO6 */ -0 ,/* MIXED1IO7 */ -1 ,/* MIXED1IO8 */ -1 ,/* MIXED1IO9 */ -1 ,/* MIXED1IO10 */ -1 ,/* MIXED1IO11 */ -0 ,/* MIXED1IO12 */ -0 ,/* MIXED1IO13 */ +2 ,/* MIXED1IO0 */ +2 ,/* MIXED1IO1 */ +2 ,/* MIXED1IO2 */ +2 ,/* MIXED1IO3 */ +2 ,/* MIXED1IO4 */ +2 ,/* MIXED1IO5 */ +2 ,/* MIXED1IO6 */ +2 ,/* MIXED1IO7 */ +2 ,/* MIXED1IO8 */ +2 ,/* MIXED1IO9 */ +2 ,/* MIXED1IO10 */ +2 ,/* MIXED1IO11 */ +2 ,/* MIXED1IO12 */ +2 ,/* MIXED1IO13 */ 0 ,/* MIXED1IO14 */ 1 ,/* MIXED1IO15 */ 1, /* MIXED1IO16 */board/altera/cyclone5-socdk/qts/pll_config.h +1
-1@@ -31,7 +31,7 @@#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
board/altera/cyclone5-socdk/qts/pll_config.h line 68
Quoted 5 lines
board/altera/cyclone5-socdk/qts/pll_config.h +1
-1@@ -65,7 +65,7 @@#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
I believe the EMAC1 clock is still 250MHz which result of 25MHz * (79+1) / (1+1) / (3+1).
Thanks
Chin Liang
Quoted 3 lines
board/altera/cyclone5-socdk/qts/pll_config.h +0
-0#define CONFIG_HPS_CLK_USBCLK_HZ 200000000#define CONFIG_HPS_CLK_NAND_HZ 50000000#define CONFIG_HPS_CLK_SDMMC_HZ 200000000