arm: socfpga: Actually enable L2 cache
Subsystems (3)
PATCH 1/1 arm: socfpga: Actually enable L2 cache
The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache.
--- arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
arch/arm/mach-socfpga/misc.c +5 -2
@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32 (&pl310->pl310_aux_ctrl,L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE ); + +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN ); }/*
Signature · 1 line
2.1.4
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 21 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>--- arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)arch/arm/mach-socfpga/misc.c +1
-2@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */
arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 10 lines
arch/arm/mach-socfpga/misc.c +4
-0+clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32 (&pl310->pl310_aux_ctrl,L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE ); + +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );
Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
Thanks,
Stefan
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 24 lines · Stefan Roese
Quoted 23 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>--- arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)arch/arm/mach-socfpga/misc.c +2
-2@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );
Quoted 13 lines
arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 9 lines
arch/arm/mach-socfpga/misc.c +0
-0/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE);arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
And another comment. It might be necessary to disable the L2 cache when booting into Linux by providing the v7_outer_cache_enable() function. I noticed problems in Linux with MVEBU with the L2 cache still enabled.
Thanks,
Stefan
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 45 lines · Stefan Roese
Quoted 36 lines · Stefan Roese
Quoted 35 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)arch/arm/mach-socfpga/misc.c +2
-2@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE);Quoted 7 lines
arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 3 lines
arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
Quoted 4 lines
And another comment. It might be necessary to disable the L2 cache when booting into Linux by providing the
v7_outer_cache_enable()function. I noticed problems in Linux with MVEBU with the L2 cache still enabled.
This is the v7_outer_cache_enable() function. Do you have anything else in mind ?
Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 46 lines · Marek Vasut
Quoted 45 lines · Stefan Roese
Quoted 43 lines · Stefan Roese
Quoted 35 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)arch/arm/mach-socfpga/misc.c +2
-2@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE);arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 3 lines
arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
Quoted 7 lines
Quoted 4 lines
And another comment. It might be necessary to disable the L2 cache when booting into Linux by providing the
v7_outer_cache_enable()function. I noticed problems in Linux with MVEBU with the L2 cache still enabled.This is the
v7_outer_cache_enable()function. Do you have anything else in mind ?
Yes, I meant v7_outer_cache_disable() of course.
Thanks,
Stefan
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 52 lines · Stefan Roese
Quoted 51 lines · Marek Vasut
Quoted 49 lines · Stefan Roese
Quoted 36 lines · Stefan Roese
Quoted 35 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-socfpga/misc.cindex b110f5b..621f5d9 100644arch/arm/mach-socfpga/misc.c +2
-2@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE);Quoted 7 lines
arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 3 lines
arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
And another comment. It might be necessary to disable the L2 cache when booting into Linux by providing the
v7_outer_cache_enable()function. I noticed problems in Linux with MVEBU with the L2 cache still enabled.
Quoted 4 lines
Quoted 2 lines
This is the
v7_outer_cache_enable()function. Do you have anything else in mind ?Yes, I meant
v7_outer_cache_disable()of course.
Got it, thanks.
Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
In reply to Stefan RoeseQuoted 33 lines · Stefan Roese
Quoted 32 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)arch/arm/mach-socfpga/misc.c +2
-2@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32 (&pl310->pl310_aux_ctrl,L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE );
Quoted 7 lines
arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 3 lines
arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
Neither, but I didn't see any improvement on MX6 when I enabled L2 either.
The data corruption issue is still unresolved.
Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 42 lines · Marek Vasut
Quoted 33 lines · Stefan Roese
Quoted 32 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)arch/arm/mach-socfpga/misc.c +2
-2@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) { -/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32 (&pl310->pl310_aux_ctrl,L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE );Quoted 7 lines
arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 3 lines
arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
Quoted 1 line
Neither, but I didn't see any improvement on MX6 when I enabled L2 either.
Then my feeling is, that some other configuration is needed to effectively enable the L2 cache on those platforms. Sorry, but I have no clear suggestions right now. Other than to look at Linux for the L2 cache enabling.
Thanks,
Stefan
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 23 lines · Stefan Roese
Quoted 22 lines · Marek Vasut
Quoted 21 lines · Stefan Roese
Quoted 20 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-socfpga/misc.cindex b110f5b..621f5d9 100644arch/arm/mach-socfpga/misc.c +0
-0@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) {
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arch/arm/mach-socfpga/misc.c void enable_caches(void)
Quoted 6 lines
arch/arm/mach-socfpga/misc.c +2
-2-/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of
zeroes
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arch/arm/mach-socfpga/misc.c void enable_caches(void)
Quoted 9 lines
arch/arm/mach-socfpga/misc.c +3
-0*/ setbits_le32 (&pl310->pl310_aux_ctrl,L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE ); + +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see a bigger change in the performance (ethernet driver or dhrystone) by enabling the L2 cache?
Quoted 7 lines
Quoted 2 lines
Neither, but I didn't see any improvement on MX6 when I enabled L2 either.
Then my feeling is, that some other configuration is needed to effectively enable the L2 cache on those platforms. Sorry, but I have no clear suggestions right now. Other than to look at Linux for the L2 cache enabling.
The L2 cache is enabled, but the slowdown is not induced by the L2 cache. The L2 cache has no performance impact on other platforms either. Did you observe actual performance improvement with L2 cache ON anywhere ?
Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 59 lines · Marek Vasut
Quoted 25 lines · Stefan Roese
Quoted 24 lines · Marek Vasut
Quoted 22 lines · Stefan Roese
Quoted 21 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix
this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-socfpga/misc.cindex b110f5b..621f5d9 100644arch/arm/mach-socfpga/misc.c +0
-0@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) {Quoted 7 lines
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arch/arm/mach-socfpga/misc.c +2
-2-/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of
zeroes
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arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 9 lines
*/ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE);arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see
a bigger change in the performance (ethernet driver or dhrystone)
by enabling the L2 cache?Quoted 8 lines
Quoted 3 lines
Neither, but I didn't see any improvement on MX6 when I enabled L2
either.Then my feeling is, that some other configuration is needed to effectively enable the L2 cache on those platforms. Sorry, but I have no clear suggestions right now. Other than to look at Linux for the L2 cache enabling.
Quoted 6 lines
The L2 cache is enabled, but the slowdown is not induced by the L2 cache.
The L2 cache has no performance impact on other platforms either. Did you
observe actual performance improvement with L2 cache ON anywhere ?
Hmmm, here is the function for L2 cache within my development branch. Some of the latency tuning helps based on the benchmark result. Probably you can give it a try, Marek?
void v7_outer_cache_enable(void)
{
/* disable the L2 cache */
writel(0, &pl310_regs_base->pl310_ctrl);
/* enable BRESP, instruction and data prefetch, full line of
zeroes */
setbits_le32(&pl310_regs_base->pl310_aux_ctrl,
PL310_AUX_CTRL_FULL_LINE_ZERO_MASK |
PL310_AUX_CTRL_DATA_PREFETCH_MASK |
PL310_AUX_CTRL_INST_PREFETCH_MASK |
PL310_AUX_CTRL_EARLY_BRESP_MASK);
/* setup tag ram latency */
writel(0, &pl310_regs_base->pl310_tag_latency_ctrl);
/* setup data ram latency */
writel(0x10, &pl310_regs_base->pl310_data_latency_ctrl);
/* invalidate the cache before enable */
v7_outer_cache_inval_all();
/* enable the L2 cache */
writel(0x1, &pl310_regs_base->pl310_ctrl);
}Thanks
Chin Liang
Quoted 2 lines
Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 75 lines · Chin Liang See
Quoted 63 lines · Marek Vasut
Quoted 26 lines · Stefan Roese
Quoted 25 lines · Marek Vasut
On Saturday, December 19, 2015 at 11:03:45 AM, Stefan Roese
Quoted 22 lines · wrote:
Quoted 21 lines · Marek Vasut
The L2 cache was never enabled in the
v7_outer_cache_enable(), fix
this and enable the L2 cache.Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Chin Liang See <[email protected]>---
arch/arm/mach-socfpga/misc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-socfpga/misc.cindex b110f5b..621f5d9 100644arch/arm/mach-socfpga/misc.c +0
-0@@ -54,14 +54,17 @@ void enable_caches(void)void v7_outer_cache_enable (void ) {Quoted 8 lines
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arch/arm/mach-socfpga/misc.c +2
-2-/* disable the L2 cache */ -writel (0 , &pl310->pl310_ctrl); +/* Disable the L2 cache */ +clrbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );/* enable BRESP, instruction and data prefetch, full line of
zeroes
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arch/arm/mach-socfpga/misc.c void enable_caches(void) · line 67
Quoted 9 lines
*/ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE);arch/arm/mach-socfpga/misc.c +3
-0+ +/* Enable the L2 cache */ +setbits_le32 (&pl310->pl310_ctrl,L2X0_CTRL_EN );Thanks Marek. I would be interested in some number here. Do you see
a bigger change in the performance (ethernet driver or dhrystone)
by enabling the L2 cache?Quoted 8 lines
Quoted 3 lines
Neither, but I didn't see any improvement on MX6 when I enabled L2
either.Then my feeling is, that some other configuration is needed to effectively enable the L2 cache on those platforms. Sorry, but I have no clear suggestions right now. Other than to look at Linux for the L2 cache enabling.
Quoted 5 lines
The L2 cache is enabled, but the slowdown is not induced by the L2 cache.
The L2 cache has no performance impact on other platforms either. Did you
observe actual performance improvement with L2 cache ON anywhere ?Hmmm, here is the function for L2 cache within my development branch. Some of the latency tuning helps based on the benchmark result. Probably you can give it a try, Marek?
void
v7_outer_cache_enable(void)
Quoted 14 lines
{
/* disable the L2 cache */
writel(0, &pl310_regs_base->pl310_ctrl);
/* enable BRESP, instruction and data prefetch, full line of
zeroes */
setbits_le32(&pl310_regs_base->pl310_aux_ctrl,
PL310_AUX_CTRL_FULL_LINE_ZERO_MASK |
PL310_AUX_CTRL_DATA_PREFETCH_MASK |
PL310_AUX_CTRL_INST_PREFETCH_MASK |
PL310_AUX_CTRL_EARLY_BRESP_MASK);
/* setup tag ram latency */
writel(0, &pl310_regs_base->pl310_tag_latency_ctrl);Are you _sure_ this is a good idea to set the latency to 0x0 ?
Quoted 15 lines
/* setup data ram latency */ writel(0x10, &pl310_regs_base->pl310_data_latency_ctrl); /* invalidate the cache before enable */ v7_outer_cache_inval_all(); /* enable the L2 cache */ writel(0x1, &pl310_regs_base->pl310_ctrl); }Thanks
Chin LiangQuoted 2 lines
Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 1 line · Marek Vasut
On Monday, December 21, 2015 at 10:50:50 AM, Chin Liang See wrote:
[..]
Quoted 18 lines
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Hmmm, here is the function for L2 cache within my development branch.
Some of the latency tuning helps based on the benchmark result. Probably you can give it a try, Marek?void
v7_outer_cache_enable(void){ /* disable the L2 cache */ writel(0, &pl310_regs_base->pl310_ctrl); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310_regs_base->pl310_aux_ctrl, PL310_AUX_CTRL_FULL_LINE_ZERO_MASK | PL310_AUX_CTRL_DATA_PREFETCH_MASK | PL310_AUX_CTRL_INST_PREFETCH_MASK | PL310_AUX_CTRL_EARLY_BRESP_MASK);
Quoted 5 lines
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/* setup tag ram latency */ writel(0, &pl310_regs_base->pl310_tag_latency_ctrl);Are you _sure_ this is a good idea to set the latency to
0x0?
Actually it still have 1 cycle of latency, just no additional
Thanks
Chin Liang
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 26 lines · Chin Liang See
Quoted 1 line · Marek Vasut
On Monday, December 21, 2015 at 10:50:50 AM, Chin Liang See wrote:
[..]
Quoted 22 lines
Quoted 22 lines
Hmmm, here is the function for L2 cache within my development branch.
Some of the latency tuning helps based on the benchmark result. Probably you can give it a try, Marek?void
v7_outer_cache_enable(void)
{/* disable the L2 cache */ writel(0, &pl310_regs_base->pl310_ctrl); /* enable BRESP, instruction and data prefetch, full line ofzeroes */
setbits_le32(&pl310_regs_base->pl310_aux_ctrl, PL310_AUX_CTRL_FULL_LINE_ZERO_MASK | PL310_AUX_CTRL_DATA_PREFETCH_MASK | PL310_AUX_CTRL_INST_PREFETCH_MASK | PL310_AUX_CTRL_EARLY_BRESP_MASK);
Quoted 6 lines
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/* setup tag ram latency */ writel(0, &pl310_regs_base->pl310_tag_latency_ctrl);Are you _sure_ this is a good idea to set the latency to
0x0?Actually it still have 1 cycle of latency, just no additional
And that's OK on socfpga ? I would've expected some latency here.
Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 29 lines · Marek Vasut
Quoted 28 lines · Chin Liang See
Quoted 2 lines · Marek Vasut
On Monday, December 21, 2015 at 10:50:50 AM, Chin Liang See wrote:
[..]
Quoted 23 lines
Quoted 23 lines
Hmmm, here is the function for L2 cache within my development branch.
Some of the latency tuning helps based on the benchmark result. Probably you can give it a try, Marek?void
v7_outer_cache_enable(void)
{/* disable the L2 cache */ writel(0, &pl310_regs_base->pl310_ctrl); /* enable BRESP, instruction and data prefetch, fullline of
zeroes */
setbits_le32(&pl310_regs_base->pl310_aux_ctrl, PL310_AUX_CTRL_FULL_LINE_ZERO_MASK | PL310_AUX_CTRL_DATA_PREFETCH_MASK | PL310_AUX_CTRL_INST_PREFETCH_MASK | PL310_AUX_CTRL_EARLY_BRESP_MASK);
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/* setup tag ram latency */ writel(0, &pl310_regs_base->pl310_tag_latency_ctrl);Are you _sure_ this is a good idea to set the latency to
0x0?Actually it still have 1 cycle of latency, just no additional
And that's OK on socfpga ? I would've expected some latency here.
Yup, Linux is using the same value too
https://github.com/altera-opensource/linux-socfpga/blob/master/arch/arm/boot/dts/socfpga.dtsi
Thanks
Chin Liang
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Best regards,
Marek Vasut
PATCH 1/1 arm: socfpga: Actually enable L2 cache
Quoted 37 lines · Chin Liang See
Quoted 36 lines · Marek Vasut
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On Monday, December 21, 2015 at 10:50:50 AM, Chin Liang See
wrote:
[..]
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Hmmm, here is the function for L2 cache within my development branch.
Some of the latency tuning helps based on the benchmark result. Probably you can give it a try, Marek?void
v7_outer_cache_enable(void)
{/* disable the L2 cache */ writel(0, &pl310_regs_base->pl310_ctrl); /* enable BRESP, instruction and data prefetch, fullline of
zeroes */
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setbits_le32(&pl310_regs_base->pl310_aux_ctrl, PL310_AUX_CTRL_FULL_LINE_ZERO_MASK | PL310_AUX_CTRL_DATA_PREFETCH_MASK | PL310_AUX_CTRL_INST_PREFETCH_MASK | PL310_AUX_CTRL_EARLY_BRESP_MASK); /* setup tag ram latency */ writel(0, &pl310_regs_base->pl310_tag_latency_ctrl);Are you _sure_ this is a good idea to set the latency to
0x0?
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Actually it still have 1 cycle of latency, just no additional
And that's OK on socfpga ? I would've expected some latency here.
Yup, Linux is using the same value too
https://github.com/altera-opensource/linux-socfpga/blob/master/arch/arm/boot/dts/socfpga.dtsi
I find the value a bit odd, since other CortexA9 machines which I used always configured that to something higher than 0 . Can anyone comment on that ?
Best regards,
Marek Vasut