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arm: socfpga: Actually enable L2 cache

PATCH Superseded Marek Vasut 2 participants 3 messages Dec 20, 2015 – Dec 21, 2015

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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Marek Vasut

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#0 lore raw

PATCH v2 1/1 arm: socfpga: Actually enable L2 cache

The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
---
 arch/arm/mach-socfpga/misc.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

V2: Add v7_outer_cache_disable() as suggested by SR .

arch/arm/mach-socfpga/misc.c +11 -2
index b110f5b..a54d2b9 100644
@@ -54,14 +54,23 @@ void enable_caches(void)
 
 void v7_outer_cache_enable(void)
 {
-	/* disable the L2 cache */
-	writel(0, &pl310->pl310_ctrl);
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
 	/* enable BRESP, instruction and data prefetch, full line of zeroes */
 	setbits_le32(&pl310->pl310_aux_ctrl,
 		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
 		     L310_AUX_CTRL_INST_PREFETCH_MASK |
 		     L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+	/* Enable the L2 cache */
+	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
 
 /*
Signature · 1 line
2.1.4
#1 lore raw

PATCH v2 1/1 arm: socfpga: Actually enable L2 cache

Quoted 12 lines · Marek Vasut

The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
---
 arch/arm/mach-socfpga/misc.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

V2: Add v7_outer_cache_disable() as suggested by SR .

Acked-by Chin Liang See <[email protected]>

Thanks
Chin Liang

author Applied
#2 lore raw

PATCH v2 1/1 arm: socfpga: Actually enable L2 cache

Quoted 9 lines · Chin Liang See
Quoted 8 lines · Marek Vasut

The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>

---

Quoted 6 lines
Quoted 4 lines
 arch/arm/mach-socfpga/misc.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

V2: Add v7_outer_cache_disable() as suggested by SR .

Acked-by Chin Liang See <[email protected]>

Applied, thanks.

Best regards,
Marek Vasut