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arm: socfpga: Fix QSPI doesn't work on socdk board

PATCH New shengjiangwu 3 participants 4 messages Dec 22, 2015

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shengjiangwu

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#0 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.

Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>
---
 board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++++++------
 board/altera/cyclone5-socdk/qts/pll_config.h    |    2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)
board/altera/cyclone5-socdk/qts/pinmux_config.h +6 -6
index 442b1e0..06783dc 100644
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
 	2, /* MIXED1IO12 */
 	2, /* MIXED1IO13 */
 	0, /* MIXED1IO14 */
-	1, /* MIXED1IO15 */
-	1, /* MIXED1IO16 */
-	1, /* MIXED1IO17 */
-	1, /* MIXED1IO18 */
-	0, /* MIXED1IO19 */
-	0, /* MIXED1IO20 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
 	0, /* MIXED1IO21 */
 	0, /* MIXED2IO0 */
 	0, /* MIXED2IO1 */
board/altera/cyclone5-socdk/qts/pll_config.h +1 -1
index 9e336e3..4abd2e0 100644
@@ -14,7 +14,7 @@
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Quoted 10 lines · shengjiangwu

Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.

Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>
Quoted 5 lines
---
 board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++++++------
 board/altera/cyclone5-socdk/qts/pll_config.h    |    2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)
Acked-by Chin Liang See <[email protected]>

Thanks
Chin Liang

Applied
#2 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

In reply to shengjiangwu
Quoted 10 lines · shengjiangwu

Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.

Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>

Applied, thanks.

I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks

[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master

Best regards,
Marek Vasut

#3 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Quoted 12 lines · Marek Vasut
Quoted 10 lines · shengjiangwu

Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.

Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>
Quoted 7 lines

Applied, thanks.

I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks

[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master

Pushed. Please let me know how SoCDK works for you now and if there are still some problems.

Best regards,
Marek Vasut