arm: socfpga: Fix QSPI doesn't work on socdk board

PATCH New 圣江吴 3 participants 5 messages Dec 23, 2015

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圣江吴

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2015-12-23 02:26 UTC #0 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Quoted 92 lines

From: Marek Vasut
Date: 2015-12-23 10:07
To: ShengjiangWu
CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
Quoted 74 lines · ShengjiangWu
Quoted 47 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Wednesday, December 23, 2015 9:25 AM
To: ?? ?
Cc: u-boot at lists.denx.de; clsee at altera.com;
dinguyen at opensource.altera.com; dinh.linux at gmail.com; pavel at denx.de; sr at denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
Quoted 28 lines · ?? ?
On Dec 22, 2015, at 12:33 PM, Marek Vasut <[email protected]> wrote:
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
Quoted 10 lines · shengjiangwu
Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.
Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there are still some problems.
Quoted 8 lines
Best regards,
Marek Vasut
Hi Marek,
Thank you for your help, I tested the master branch, emac1 and QSPI works. Below is log.
Quoted 7 lines
Good! so we're happy ? Can you give USB a spin too? I think it might have some issues and I don't have the necessary cable here.
[...]
Best regards,
Marek Vasut
Hi Marek,
Yes, emac1 and qspi are working now. I'm afraid USB is not working,
=> usb reset
resetting USB...
USB0: Core Release: 2.93a
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
Quoted 8 lines
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
scanning bus 0 for devices... 1 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
U-Boot Root Hub

Quoted 2 lines

Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .

Hi Marek,

Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,

=> usb start
starting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Mass Storage (480 Mb/s, 98mA)
Generic USB Storage 000000000272

Best Regards,
ShengjiangWu

Marek Vasut

2015-12-23 02:27 UTC #1 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Quoted 106 lines · ?? ?

Quoted 90 lines
From: Marek Vasut
Date: 2015-12-23 10:07
To: ShengjiangWu
CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
Quoted 74 lines · ShengjiangWu
Quoted 47 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Wednesday, December 23, 2015 9:25 AM
To: ?? ?
Cc: u-boot at lists.denx.de; clsee at altera.com;
dinguyen at opensource.altera.com; dinh.linux at gmail.com; pavel at denx.de; sr at denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
Quoted 28 lines · ?? ?
On Dec 22, 2015, at 12:33 PM, Marek Vasut <[email protected]> wrote:
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
Quoted 10 lines · shengjiangwu
Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.
Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there are still some problems.
Quoted 8 lines
Best regards,
Marek Vasut
Hi Marek,
Thank you for your help, I tested the master branch, emac1 and QSPI works. Below is log.
Quoted 7 lines
Good! so we're happy ? Can you give USB a spin too? I think it might have some issues and I don't have the necessary cable here.
[...]
Best regards,
Marek Vasut
Hi Marek,
Yes, emac1 and qspi are working now. I'm afraid USB is not working,
=> usb reset
resetting USB...
USB0: Core Release: 2.93a
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
Quoted 8 lines
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
scanning bus 0 for devices... 1 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
U-Boot Root Hub
Quoted 2 lines
Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,
=> usb start
starting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)

Quoted 4 lines

| U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA)
Generic USB Storage 000000000272

Cool, thanks! Patch please ;-)

Chin Liang See

2015-12-23 02:29 UTC #2 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Quoted 121 lines · Marek Vasut

Quoted 120 lines · ?? ?
Quoted 102 lines
From: Marek Vasut
Date: 2015-12-23 10:07
To: ShengjiangWu
CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
Quoted 84 lines · ShengjiangWu
Quoted 55 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Wednesday, December 23, 2015 9:25 AM
To: ?? ?
Cc: u-boot at lists.denx.de; clsee at altera.com; dinguyen at opensource.altera.com; dinh.linux at gmail.com; pavel at denx.de;
sr at denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work
on socdk board
Quoted 37 lines · ?? ?
On Dec 22, 2015, at 12:33 PM, Marek Vasut <[email protected]> wrote:
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
Quoted 10 lines · shengjiangwu
Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.
Signed-off-by shengjiangwu <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefan Roese <[email protected]>
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see
if the CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there
are still some problems.
Best regards,
Marek Vasut
Quoted 5 lines
Hi Marek,
Thank you for your help, I tested the master branch, emac1 and QSPI
works. Below is log.
Quoted 8 lines
Good! so we're happy ? Can you give USB a spin too? I think it might
have some issues and I don't have the necessary cable here.
[...]
Best regards,
Marek Vasut
Hi Marek,
Yes, emac1 and qspi are working now. I'm afraid USB is not working,
=> usb reset
resetting USB...
USB0: Core Release: 2.93a
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
Quoted 8 lines
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
scanning bus 0 for devices... 1 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
U-Boot Root Hub
Quoted 3 lines
Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb
works,
=> usb start
starting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)

Quoted 6 lines

Quoted 4 lines
Quoted 1 line
U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA)
Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)

Nice, guess Altera email is very slow

Thanks
Chin Liang

Chin Liang See

2015-12-23 02:38 UTC #3 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Quoted 2 lines · Chin Liang See

Quoted 1 line · Marek Vasut
On Wednesday, December 23, 2015 at 03:26:07 AM, ?? ? wrote:

[..]

Quoted 15 lines

Quoted 15 lines
Quoted 15 lines
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb
works,
=> usb start
starting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)

Quoted 9 lines

Quoted 6 lines
Quoted 4 lines
Quoted 1 line
U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA)
Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)
Nice, guess Altera email is very slow

Yup, it work for me too with the pinmux change and dcache on.

U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC
spl: mmc boot mode: raw

U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC External Transceiver (1.8V)
       Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   dwmmc0 at ff704000: 0

*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit

Net:
Error: ethernet at ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
=> dcache
Data (writethrough) Cache is ON
=> usb reset
resetting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found => usb info
1: Hub, USB Revision 1.10
- U-Boot Root Hub
- Class: Hub
- PacketSize: 8 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 0.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms

2: Mass Storage, USB Revision 2.0
- USB DISK 2.0 0781076602A6
- Class: (from Interface) Mass Storage
- PacketSize: 64 Configurations: 1
- Vendor: 0x13fe Product 0x1e00 Version 1.16
Configuration: 1
- Interfaces: 1 Bus Powered 200mA
Interface: 0
- Alternate Setting 0, Endpoints: 2
- Class Mass Storage, Transp. SCSI, Bulk only
- Endpoint 1 In Bulk MaxPacket 512
- Endpoint 2 Out Bulk MaxPacket 512

Thanks
Chin Liang

Quoted 2 lines

Thanks
Chin Liang

Marek Vasut

2015-12-23 03:04 UTC #4 lore raw

PATCH 1/1 arm: socfpga: Fix QSPI doesn't work on socdk board

Quoted 76 lines · Chin Liang See

Quoted 2 lines · Chin Liang See
Quoted 1 line · Marek Vasut
On Wednesday, December 23, 2015 at 03:26:07 AM, ?? ? wrote:
[..]
Quoted 14 lines
Quoted 14 lines
Quoted 14 lines
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb
works,
=> usb start
starting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found => usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
Quoted 8 lines
Quoted 6 lines
Quoted 4 lines
Quoted 1 line
U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA)
Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)
Nice, guess Altera email is very slow
Yup, it work for me too with the pinmux change and dcache on.
U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC
spl: mmc boot mode: raw
U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC External Transceiver (1.8V)
       Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   dwmmc0 at ff704000: 0
*** Warning - bad CRC, using default environment
In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet at ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
=> dcache
Data (writethrough) Cache is ON
=> usb reset
resetting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found => usb info
1: Hub, USB Revision 1.10
- U-Boot Root Hub
- Class: Hub
- PacketSize: 8 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 0.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms

Quoted 12 lines

2: Mass Storage, USB Revision 2.0
- USB DISK 2.0 0781076602A6
- Class: (from Interface) Mass Storage
- PacketSize: 64 Configurations: 1
- Vendor: 0x13fe Product 0x1e00 Version 1.16
Configuration: 1
- Interfaces: 1 Bus Powered 200mA
Interface: 0
- Alternate Setting 0, Endpoints: 2
- Class Mass Storage, Transp. SCSI, Bulk only
- Endpoint 1 In Bulk MaxPacket 512
- Endpoint 2 Out Bulk MaxPacket 512

Cool, I will pick the patch shortly.