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MIPS: Add support for Microchip PIC32MZ[DA] family.

PATCH Superseded Purna Chandra Mandal 2 participants 4 messages Jan 4, 2016 – Jan 9, 2016

Subsystems (2)
MIPS Arm/actions semi architecture

v2 of 4 Superseded Latest is v4 →

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Purna Chandra Mandal

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#0 lore raw

PATCH v2 6/13 MIPS: Add support for Microchip PIC32MZ[DA] family.

Signed-off-by Purna Chandra Mandal <[email protected]>

---

Changes in v2:
- drop unnecessary board_early_init_f()
- use LEAF(), END() macros for lowlevel_init
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor of physical address in dts file

 arch/mips/cpu/start.S                     |   2 +
 arch/mips/dts/pic32mzda.dtsi              |  64 +++++++++++++
 arch/mips/mach-pic32/Kconfig              |  16 +++-
 arch/mips/mach-pic32/Makefile             |   2 +-
 arch/mips/mach-pic32/cpu.c                | 146 ++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/include/mach/pic32.h |   3 +
 arch/mips/mach-pic32/lowlevel_init.S      |  27 ++++++
 arch/mips/mach-pic32/reset.c              |  36 ++++++++
 8 files changed, 294 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c
arch/mips/cpu/start.S +2 -0
index e95cdca..a7e6722 100644
@@ -185,6 +185,8 @@ reset:
 	PTR_ADDU t0, k0, GD_MALLOC_BASE	# gd->malloc_base offset
 	sw	sp, 0(t0)
 #endif
+	/* Initialize args to zero. */
+	li	a0, 0x0
 
 	PTR_LA	t9, board_init_f
 	jr	t9
arch/mips/dts/pic32mzda.dtsi new file +64 -0

64 lines not on this page · raw message

arch/mips/mach-pic32/Kconfig +15 -1
index 98b0b88..a394791 100644
@@ -2,11 +2,25 @@ menu "Microchip PIC32 platforms"
 	depends on MACH_PIC32
 
 config SYS_SOC
-	default "none"
+	default "pic32mzda" if SOC_PIC32MZDA
 
 choice
 	prompt "PIC32 SoC select"
 
+config SOC_PIC32MZDA
+	bool "Microchip PIC32MZ[DA] family"
+	select SUPPORTS_LITTLE_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select SYS_MIPS_CACHE_INIT_RAM_LOAD
+	select MIPS_BOOT_CMDLINE_LEGACY
+	select MIPS_BOOT_FDT
+	select DM_SERIAL
+	select PIC32_SERIAL
+	select PIC32_PINCTRL
+	help
+	  This supports Microchip PIC32MZ[DA] family of microcontrollers.
+
 endchoice
 
 choice
arch/mips/mach-pic32/Makefile +1 -1
index cb42607..e321e65 100644
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
-obj-y = cpu.o
+obj-y = cpu.o lowlevel_init.o reset.o
\ No newline at end of file
arch/mips/mach-pic32/cpu.c +146 -0

154 lines not on this page · raw message

arch/mips/mach-pic32/include/mach/pic32.h +3 -0
index f618697..8d4b275 100644
@@ -76,4 +76,7 @@ static inline void __iomem *pic32_ioremap(phys_addr_t addr)
 	return (void __iomem *)CKSEG1ADDR(addr);
 }
 
+/* Core */
+const char *get_core_name(void);
+
 #endif	/* __PIC32_REGS_H__ */
arch/mips/mach-pic32/lowlevel_init.S new file +27 -0
new file mode 100644
index 0000000..bff5553
@@ -0,0 +1,27 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+*/
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm.h>
+
+LEAF(lowlevel_init)
+	/*
+	 * Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+	jr	ra
+	nop
+	END(lowlevel_init)
arch/mips/mach-pic32/reset.c new file +36 -0
new file mode 100644
index 0000000..70467cb
@@ -0,0 +1,36 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/pic32.h>
+
+#define SYSKEY          0x0030
+#define  UNLOCK_KEY1	0xaa996655
+#define  UNLOCK_KEY2	0x556699aa
+#define  LOCK_KEY	0
+
+#define RSWRST          0x1250
+
+void _machine_restart(void)
+{
+	void __iomem *base;
+
+	base = pic32_ioremap(PIC32_CFG_BASE);
+
+	/* unlock sequence */
+	writel(LOCK_KEY, base + SYSKEY);
+	writel(UNLOCK_KEY1, base + SYSKEY);
+	writel(UNLOCK_KEY2, base + SYSKEY);
+
+	/* soft reset */
+	writel(0x1, base + RSWRST);
+	(void) readl(base + RSWRST);
+
+	while (1)
+		;
+}
Signature · 1 line
1.8.3.1
#1 lore raw

PATCH v2 6/13 MIPS: Add support for Microchip PIC32MZ[DA] family.

2016-01-04 15:01 GMT+01:00 Purna Chandra Mandal <[email protected]>:

Quoted 29 lines
Signed-off-by Purna Chandra Mandal <[email protected]>

---

Changes in v2:
- drop unnecessary board_early_init_f()
- use LEAF(), END() macros for lowlevel_init
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor of physical address in dts file

 arch/mips/cpu/start.S                     |   2 +
 arch/mips/dts/pic32mzda.dtsi              |  64 +++++++++++++
 arch/mips/mach-pic32/Kconfig              |  16 +++-
 arch/mips/mach-pic32/Makefile             |   2 +-
 arch/mips/mach-pic32/cpu.c                | 146 ++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/include/mach/pic32.h |   3 +
 arch/mips/mach-pic32/lowlevel_init.S      |  27 ++++++
 arch/mips/mach-pic32/reset.c              |  36 ++++++++
 8 files changed, 294 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c
arch/mips/cpu/start.S +0 -0
index e95cdca..a7e6722 100644

arch/mips/cpu/start.S reset: · line 189

Quoted 5 lines
arch/mips/cpu/start.S +2 -0
@@ -185,6 +185,8 @@ reset:
        PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
        sw      sp, 0(t0)
 #endif
+       /* Initialize args to zero. */
+       li      a0, 0x0

please create a separate patch for this change. Also the code must be compatible with MIPS64 now, so please do:

PTR_LI a0, 0

Quoted 86 lines
arch/mips/cpu/start.S +0 -0
        PTR_LA  t9, board_init_f
        jr      t9
arch/mips/dts/pic32mzda.dtsi new file +64 -0
new file mode 100644
index 0000000..f518ba8
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2015 Microchip Technology, Inc.
+ * Purna Chandra Mandal, <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/microchip,clock.h>
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "microchip,pic32mzda", "microchip,pic32mz";
+
+       cpus {
+               cpu at 0 {
+                       compatible = "mips,mips14kc";
+               };
+       };
+
+       clock: clk at 1f801200 {
+               compatible = "microchip,pic32mzda_clk";
+               reg = <0x1f801200 0x1000>;
+               clock-cells = <1>;
+       };
+
+       uart1: serial at 1f822000 {
+               compatible = "microchip,pic32mzda-uart";
+               reg = <0x1f822000 0x50>;
+               interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+               clocks = <&clock PB2CLK>;
+       };
+
+       uart2: serial at 1f822200 {
+               compatible = "microchip,pic32mzda-uart";
+               reg = <0x1f822200 0x50>;
+               interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clock PB2CLK>;
+               status = "disabled";
+       };
+
+       uart6: serial at 1f822a00 {
+               compatible = "microchip,pic32mzda-uart";
+               reg = <0x1f822a00 0x50>;
+               interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clock PB2CLK>;
+               status = "disabled";
+       };
+
+       evic: interrupt-controller at 1f810000 {
+               compatible = "microchip,pic32mzda-evic";
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               reg = <0x1f810000 0x1000>;
+       };
+
+       pinctrl: pinctrl at 1f801400 {
+               compatible = "microchip,pic32mzda-pinctrl";
+               reg = <0x1f801400 0x100>, /* in  */
+                     <0x1f801500 0x200>; /* out */
+               status = "disabled";
+       };
+};
arch/mips/mach-pic32/Kconfig +1 -1
index 98b0b88..a394791 100644
@@ -2,11 +2,25 @@ menu "Microchip PIC32 platforms"
        depends on MACH_PIC32
 
 config SYS_SOC
-       default "none"
+       default "pic32mzda" if SOC_PIC32MZDA
 
 choice
        prompt "PIC32 SoC select"

arch/mips/mach-pic32/Kconfig menu "Microchip PIC32 platforms" · line 18

Quoted 10 lines
arch/mips/mach-pic32/Kconfig +8 -0
 
+config SOC_PIC32MZDA
+       bool "Microchip PIC32MZ[DA] family"
+       select SUPPORTS_LITTLE_ENDIAN
+       select SUPPORTS_CPU_MIPS32_R1
+       select SUPPORTS_CPU_MIPS32_R2
+       select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+       select MIPS_BOOT_CMDLINE_LEGACY
+       select MIPS_BOOT_FDT

those are user-selectable options and should not be enforced by the SoC. But you can enable them in your defconfig.

Quoted 25 lines
arch/mips/mach-pic32/Kconfig +6 -0
+       select DM_SERIAL
+       select PIC32_SERIAL
+       select PIC32_PINCTRL
+       help
+         This supports Microchip PIC32MZ[DA] family of microcontrollers.
+
 endchoice

choice

arch/mips/mach-pic32/Makefile +1 -1
index cb42607..e321e65 100644
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
-obj-y = cpu.o
+obj-y = cpu.o lowlevel_init.o reset.o
\ No newline at end of file
arch/mips/mach-pic32/cpu.c +0 -0
index 58fd3ab..7bd0f07 100644

arch/mips/mach-pic32/cpu.c line 7

Quoted 2 lines
arch/mips/mach-pic32/cpu.c +0 -0
@@ -6,8 +6,154 @@
  *
  */

your copyright and SPDX license identifier are missing

Quoted 30 lines
arch/mips/mach-pic32/cpu.c +28 -0
 #include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <debug_uart.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <mach/pic32.h>
+#include <mach/ddr.h>
+#include <dt-bindings/clock/microchip,clock.h>
 
+/* Flash prefetch */
+#define PRECON          0x00
+#define PRECONCLR       (PRECON + _CLR_OFFSET)
+#define PRECONSET       (PRECON + _SET_OFFSET)
+
+/* Flash ECCCON */
+#define ECC_MASK       0x03
+#define ECC_SHIFT      4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong clk_get_cpu_rate(void)
+{
+       int ret;
+       struct udevice *dev;
+
+       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+       if (ret) {
+               panic("uclass-clk: device not found\n");

arch/mips/mach-pic32/cpu.c line 47

Quoted 10 lines
arch/mips/mach-pic32/cpu.c +10 -0
+               return 0;
+       }
+
+       return clk_get_rate(dev);
+}
+
+/* initialize prefetch module related to cpu_clk */
+static void init_prefetch(void)
+{
+#define _MHZ(x)  ((x) * 1000000)

please do not define and undefine macros inside of function bodies. You could define it once at the beginning of this file or in a header file. You could also define the clock frequencies directly, e.g.

#define CLK_83_MHZ 83 * 1000 * 1000

Quoted 146 lines
arch/mips/mach-pic32/cpu.c +108 -0
+       void __iomem *base;
+       int v, nr_waits;
+       ulong rate;
+
+       rate = clk_get_cpu_rate();
+
+       /* get flash ECC type */
+       base = pic32_ioremap(PIC32_CFG_BASE);
+       v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
+       if (v < 2) {
+               if (rate < _MHZ(66))
+                       nr_waits = 0;
+               else if (rate < _MHZ(133))
+                       nr_waits = 1;
+               else
+                       nr_waits = 2;
+       } else {
+               if (rate <= _MHZ(83))
+                       nr_waits = 0;
+               else if (rate <= _MHZ(166))
+                       nr_waits = 1;
+               else
+                       nr_waits = 2;
+       }
+
+       base = pic32_ioremap(PREFETCH_BASE);
+       writel(nr_waits, base + PRECON);
+
+       /* Enable prefetch for all */
+       writel(0x30, base + PRECONSET);
+#undef _MHZ
+}
+
+/* arch specific CPU init after DM */
+int arch_cpu_init_dm(void)
+{
+       /* flash prefetch */
+       init_prefetch();
+       return 0;
+}
+
+/* Un-gate DDR2 modules (gated by default) */
+static void ddr2_pmd_ungate(void)
+{
+       void __iomem *regs;
+
+       regs = pic32_ioremap(PIC32_CFG_BASE);
+       writel(0, regs + PMD7);
+}
+
+/* initialize the DDR2 Controller and DDR2 PHY */
 phys_size_t initdram(int board_type)
 {
+       ddr2_pmd_ungate();
+       ddr2_phy_init();
+       ddr2_ctrl_init();
+       return ddr2_calculate_size();
+}
+
+int misc_init_r(void)
+{
+       set_io_port_base(0);
+       return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+const char *get_core_name(void)
+{
+       u32 proc_id;
+       const char *str;
+
+       proc_id = read_c0_prid();
+       switch (proc_id) {
+       case 0x19e28:
+               str = "PIC32MZ[DA]";
+               break;
+       default:
+               str = "UNKNOWN";
+       }
+
+       return str;
+}
+#endif
+
+#ifdef CONFIG_CMD_CLK
+int soc_clk_dump(void)
+{
+#define F_MHZ(x)       ((x) / 1000000)
+       int i, ret;
+       struct udevice *dev;
+
+       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+       if (ret) {
+               printf("clk-uclass not found\n");
+               return ret;
+       }
+
+       printf("PLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, PLLCLK)));
+       printf("CPU Speed: %lu MHz\n", F_MHZ(clk_get_rate(dev)));
+       printf("MPLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, MPLL)));
+
+       for (i = PB1CLK; i <= PB7CLK; i++)
+               printf("PB%d Clock Speed: %lu MHz\n",
+                      i - PB1CLK + 1, F_MHZ(clk_get_periph_rate(dev, i)));
+
+       for (i = REF1CLK; i <= REF5CLK; i++)
+               printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
+                      F_MHZ(clk_get_periph_rate(dev, i)));
+#undef F_MHZ
        return 0;
 }
+#endif
arch/mips/mach-pic32/include/mach/pic32.h +3 -0
index f618697..8d4b275 100644
@@ -76,4 +76,7 @@ static inline void __iomem *pic32_ioremap(phys_addr_t addr)
        return (void __iomem *)CKSEG1ADDR(addr);
 }
 
+/* Core */
+const char *get_core_name(void);
+
 #endif /* __PIC32_REGS_H__ */
arch/mips/mach-pic32/lowlevel_init.S new file +16 -0
new file mode 100644
index 0000000..bff5553
@@ -0,0 +1,27 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+*/
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm.h>
+
+LEAF(lowlevel_init)
+       /*
+        * Establish Cause
+        * (set IV bit)

arch/mips/mach-pic32/lowlevel_init.S line 26

Quoted 10 lines
arch/mips/mach-pic32/lowlevel_init.S new file +10 -0
+        */
+       li      t1, 0x00800000
+       mtc0    t1, CP0_CAUSE
+
+       /* Establish Wired (and Random) */
+       mtc0    zero, CP0_WIRED
+       nop
+
+       jr      ra
+       nop

please indent instructions in a delay slot with an extra space character. That is convention for U-Boot MIPS assemby code.

Quoted 47 lines
arch/mips/mach-pic32/lowlevel_init.S new file +1 -0
+       END(lowlevel_init)
arch/mips/mach-pic32/reset.c new file +36 -1
new file mode 100644
index 0000000..70467cb
@@ -0,0 +1,36 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/pic32.h>
+
+#define SYSKEY          0x0030
+#define  UNLOCK_KEY1   0xaa996655
+#define  UNLOCK_KEY2   0x556699aa
+#define  LOCK_KEY      0
+
+#define RSWRST          0x1250
+
+void _machine_restart(void)
+{
+       void __iomem *base;
+
+       base = pic32_ioremap(PIC32_CFG_BASE);
+
+       /* unlock sequence */
+       writel(LOCK_KEY, base + SYSKEY);
+       writel(UNLOCK_KEY1, base + SYSKEY);
+       writel(UNLOCK_KEY2, base + SYSKEY);
+
+       /* soft reset */
+       writel(0x1, base + RSWRST);
+       (void) readl(base + RSWRST);
+
+       while (1)
+               ;
+}
--

1.8.3.1

Signature · 1 line
- Daniel
author
#2 lore raw

PATCH v2 6/13 MIPS: Add support for Microchip PIC32MZ[DA] family.

Quoted 38 lines · Daniel Schwierzeck

2016-01-04 15:01 GMT+01:00 Purna Chandra Mandal <[email protected]>:

Quoted 29 lines
Signed-off-by Purna Chandra Mandal <[email protected]>

---

Changes in v2:
- drop unnecessary board_early_init_f()
- use LEAF(), END() macros for lowlevel_init
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor of physical address in dts file

 arch/mips/cpu/start.S                     |   2 +
 arch/mips/dts/pic32mzda.dtsi              |  64 +++++++++++++
 arch/mips/mach-pic32/Kconfig              |  16 +++-
 arch/mips/mach-pic32/Makefile             |   2 +-
 arch/mips/mach-pic32/cpu.c                | 146 ++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/include/mach/pic32.h |   3 +
 arch/mips/mach-pic32/lowlevel_init.S      |  27 ++++++
 arch/mips/mach-pic32/reset.c              |  36 ++++++++
 8 files changed, 294 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c
arch/mips/cpu/start.S +0 -0
index e95cdca..a7e6722 100644

arch/mips/cpu/start.S reset: · line 189

Quoted 5 lines
arch/mips/cpu/start.S +2 -0
@@ -185,6 +185,8 @@ reset:
        PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
        sw      sp, 0(t0)
 #endif
+       /* Initialize args to zero. */
+       li      a0, 0x0

please create a separate patch for this change. Also the code must be compatible with MIPS64 now, so please do:

Quoted 1 line

PTR_LI a0, 0

ack.

Quoted 86 lines
Quoted 86 lines
arch/mips/cpu/start.S +0 -0
        PTR_LA  t9, board_init_f
        jr      t9
arch/mips/dts/pic32mzda.dtsi new file +64 -0
new file mode 100644
index 0000000..f518ba8
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2015 Microchip Technology, Inc.
+ * Purna Chandra Mandal, <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/microchip,clock.h>
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "microchip,pic32mzda", "microchip,pic32mz";
+
+       cpus {
+               cpu at 0 {
+                       compatible = "mips,mips14kc";
+               };
+       };
+
+       clock: clk at 1f801200 {
+               compatible = "microchip,pic32mzda_clk";
+               reg = <0x1f801200 0x1000>;
+               clock-cells = <1>;
+       };
+
+       uart1: serial at 1f822000 {
+               compatible = "microchip,pic32mzda-uart";
+               reg = <0x1f822000 0x50>;
+               interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+               clocks = <&clock PB2CLK>;
+       };
+
+       uart2: serial at 1f822200 {
+               compatible = "microchip,pic32mzda-uart";
+               reg = <0x1f822200 0x50>;
+               interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clock PB2CLK>;
+               status = "disabled";
+       };
+
+       uart6: serial at 1f822a00 {
+               compatible = "microchip,pic32mzda-uart";
+               reg = <0x1f822a00 0x50>;
+               interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clock PB2CLK>;
+               status = "disabled";
+       };
+
+       evic: interrupt-controller at 1f810000 {
+               compatible = "microchip,pic32mzda-evic";
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               reg = <0x1f810000 0x1000>;
+       };
+
+       pinctrl: pinctrl at 1f801400 {
+               compatible = "microchip,pic32mzda-pinctrl";
+               reg = <0x1f801400 0x100>, /* in  */
+                     <0x1f801500 0x200>; /* out */
+               status = "disabled";
+       };
+};
arch/mips/mach-pic32/Kconfig +1 -1
index 98b0b88..a394791 100644
@@ -2,11 +2,25 @@ menu "Microchip PIC32 platforms"
        depends on MACH_PIC32
 
 config SYS_SOC
-       default "none"
+       default "pic32mzda" if SOC_PIC32MZDA
 
 choice
        prompt "PIC32 SoC select"
Quoted 10 lines

arch/mips/mach-pic32/Kconfig menu "Microchip PIC32 platforms" · line 17

Quoted 8 lines
arch/mips/mach-pic32/Kconfig +8 -0
+config SOC_PIC32MZDA
+       bool "Microchip PIC32MZ[DA] family"
+       select SUPPORTS_LITTLE_ENDIAN
+       select SUPPORTS_CPU_MIPS32_R1
+       select SUPPORTS_CPU_MIPS32_R2
+       select SYS_MIPS_CACHE_INIT_RAM_LOAD
+       select MIPS_BOOT_CMDLINE_LEGACY
+       select MIPS_BOOT_FDT

those are user-selectable options and should not be enforced by the SoC. But you can enable them in your defconfig.

ack.

Quoted 17 lines
Quoted 17 lines
arch/mips/mach-pic32/Kconfig +6 -0
+       select DM_SERIAL
+       select PIC32_SERIAL
+       select PIC32_PINCTRL
+       help
+         This supports Microchip PIC32MZ[DA] family of microcontrollers.
+
 endchoice
 
 choice
arch/mips/mach-pic32/Makefile +0 -0
index cb42607..e321e65 100644
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
Quoted 11 lines

arch/mips/mach-pic32/cpu.c line 7

Quoted 10 lines
arch/mips/mach-pic32/Makefile +1 -1
-obj-y = cpu.o
+obj-y = cpu.o lowlevel_init.o reset.o
\ No newline at end of file
arch/mips/mach-pic32/cpu.c +0 -0
index 58fd3ab..7bd0f07 100644
@@ -6,8 +6,154 @@
  *
  */

your copyright and SPDX license identifier are missing

Will add.

Quoted 44 lines
Quoted 30 lines
arch/mips/mach-pic32/cpu.c +28 -0
 #include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <debug_uart.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <mach/pic32.h>
+#include <mach/ddr.h>
+#include <dt-bindings/clock/microchip,clock.h>
 
+/* Flash prefetch */
+#define PRECON          0x00
+#define PRECONCLR       (PRECON + _CLR_OFFSET)
+#define PRECONSET       (PRECON + _SET_OFFSET)
+
+/* Flash ECCCON */
+#define ECC_MASK       0x03
+#define ECC_SHIFT      4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong clk_get_cpu_rate(void)
+{
+       int ret;
+       struct udevice *dev;
+
+       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+       if (ret) {
+               panic("uclass-clk: device not found\n");

arch/mips/mach-pic32/cpu.c line 47

Quoted 10 lines
arch/mips/mach-pic32/cpu.c +10 -0
+               return 0;
+       }
+
+       return clk_get_rate(dev);
+}
+
+/* initialize prefetch module related to cpu_clk */
+static void init_prefetch(void)
+{
+#define _MHZ(x)  ((x) * 1000000)

please do not define and undefine macros inside of function bodies. You could define it once at the beginning of this file or in a header file. You could also define the clock frequencies directly, e.g.

Quoted 1 line

#define CLK_83_MHZ 83 * 1000 * 1000

ack.

Quoted 150 lines
Quoted 150 lines
arch/mips/mach-pic32/cpu.c +108 -0
+       void __iomem *base;
+       int v, nr_waits;
+       ulong rate;
+
+       rate = clk_get_cpu_rate();
+
+       /* get flash ECC type */
+       base = pic32_ioremap(PIC32_CFG_BASE);
+       v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
+       if (v < 2) {
+               if (rate < _MHZ(66))
+                       nr_waits = 0;
+               else if (rate < _MHZ(133))
+                       nr_waits = 1;
+               else
+                       nr_waits = 2;
+       } else {
+               if (rate <= _MHZ(83))
+                       nr_waits = 0;
+               else if (rate <= _MHZ(166))
+                       nr_waits = 1;
+               else
+                       nr_waits = 2;
+       }
+
+       base = pic32_ioremap(PREFETCH_BASE);
+       writel(nr_waits, base + PRECON);
+
+       /* Enable prefetch for all */
+       writel(0x30, base + PRECONSET);
+#undef _MHZ
+}
+
+/* arch specific CPU init after DM */
+int arch_cpu_init_dm(void)
+{
+       /* flash prefetch */
+       init_prefetch();
+       return 0;
+}
+
+/* Un-gate DDR2 modules (gated by default) */
+static void ddr2_pmd_ungate(void)
+{
+       void __iomem *regs;
+
+       regs = pic32_ioremap(PIC32_CFG_BASE);
+       writel(0, regs + PMD7);
+}
+
+/* initialize the DDR2 Controller and DDR2 PHY */
 phys_size_t initdram(int board_type)
 {
+       ddr2_pmd_ungate();
+       ddr2_phy_init();
+       ddr2_ctrl_init();
+       return ddr2_calculate_size();
+}
+
+int misc_init_r(void)
+{
+       set_io_port_base(0);
+       return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+const char *get_core_name(void)
+{
+       u32 proc_id;
+       const char *str;
+
+       proc_id = read_c0_prid();
+       switch (proc_id) {
+       case 0x19e28:
+               str = "PIC32MZ[DA]";
+               break;
+       default:
+               str = "UNKNOWN";
+       }
+
+       return str;
+}
+#endif
+
+#ifdef CONFIG_CMD_CLK
+int soc_clk_dump(void)
+{
+#define F_MHZ(x)       ((x) / 1000000)
+       int i, ret;
+       struct udevice *dev;
+
+       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+       if (ret) {
+               printf("clk-uclass not found\n");
+               return ret;
+       }
+
+       printf("PLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, PLLCLK)));
+       printf("CPU Speed: %lu MHz\n", F_MHZ(clk_get_rate(dev)));
+       printf("MPLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, MPLL)));
+
+       for (i = PB1CLK; i <= PB7CLK; i++)
+               printf("PB%d Clock Speed: %lu MHz\n",
+                      i - PB1CLK + 1, F_MHZ(clk_get_periph_rate(dev, i)));
+
+       for (i = REF1CLK; i <= REF5CLK; i++)
+               printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
+                      F_MHZ(clk_get_periph_rate(dev, i)));
+#undef F_MHZ
        return 0;
 }
+#endif
arch/mips/mach-pic32/include/mach/pic32.h +3 -0
index f618697..8d4b275 100644
@@ -76,4 +76,7 @@ static inline void __iomem *pic32_ioremap(phys_addr_t addr)
        return (void __iomem *)CKSEG1ADDR(addr);
 }
 
+/* Core */
+const char *get_core_name(void);
+
 #endif /* __PIC32_REGS_H__ */
arch/mips/mach-pic32/lowlevel_init.S new file +20 -0
new file mode 100644
index 0000000..bff5553
@@ -0,0 +1,27 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+*/
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm.h>
+
+LEAF(lowlevel_init)
+       /*
+        * Establish Cause
+        * (set IV bit)
+        */
+       li      t1, 0x00800000
+       mtc0    t1, CP0_CAUSE
+
Quoted 8 lines

arch/mips/mach-pic32/lowlevel_init.S line 26

Quoted 6 lines
arch/mips/mach-pic32/lowlevel_init.S new file +6 -0
+       /* Establish Wired (and Random) */
+       mtc0    zero, CP0_WIRED
+       nop
+
+       jr      ra
+       nop

please indent instructions in a delay slot with an extra space character. That is convention for U-Boot MIPS assemby code.

ack.

Quoted 49 lines
Quoted 47 lines
arch/mips/mach-pic32/lowlevel_init.S new file +1 -0
+       END(lowlevel_init)
arch/mips/mach-pic32/reset.c new file +36 -1
new file mode 100644
index 0000000..70467cb
@@ -0,0 +1,36 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/pic32.h>
+
+#define SYSKEY          0x0030
+#define  UNLOCK_KEY1   0xaa996655
+#define  UNLOCK_KEY2   0x556699aa
+#define  LOCK_KEY      0
+
+#define RSWRST          0x1250
+
+void _machine_restart(void)
+{
+       void __iomem *base;
+
+       base = pic32_ioremap(PIC32_CFG_BASE);
+
+       /* unlock sequence */
+       writel(LOCK_KEY, base + SYSKEY);
+       writel(UNLOCK_KEY1, base + SYSKEY);
+       writel(UNLOCK_KEY2, base + SYSKEY);
+
+       /* soft reset */
+       writel(0x1, base + RSWRST);
+       (void) readl(base + RSWRST);
+
+       while (1)
+               ;
+}
--

1.8.3.1

#3 lore raw

PATCH v2 6/13 MIPS: Add support for Microchip PIC32MZ[DA] family.

Am Mittwoch, den 06.01.2016, 15:03 +0530 schrieb Purna Chandra Mandal:

Quoted 44 lines · Daniel Schwierzeck
Quoted 43 lines

2016-01-04 15:01 GMT+01:00 Purna Chandra Mandal <
purna.mandal at microchip.com>:

Quoted 32 lines
Signed-off-by Purna Chandra Mandal <[email protected]>

---

Changes in v2:
- drop unnecessary board_early_init_f()
- use LEAF(), END() macros for lowlevel_init
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor of physical address in dts file

 arch/mips/cpu/start.S                     |   2 +
 arch/mips/dts/pic32mzda.dtsi              |  64 +++++++++++++
 arch/mips/mach-pic32/Kconfig              |  16 +++-
 arch/mips/mach-pic32/Makefile             |   2 +-
 arch/mips/mach-pic32/cpu.c                | 146
++++++++++++++++++++++++++++++
 arch/mips/mach-pic32/include/mach/pic32.h |   3 +
 arch/mips/mach-pic32/lowlevel_init.S      |  27 ++++++
 arch/mips/mach-pic32/reset.c              |  36 ++++++++
 8 files changed, 294 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c
arch/mips/cpu/start.S +0 -0
index e95cdca..a7e6722 100644

arch/mips/cpu/start.S reset: · line 189

Quoted 5 lines
arch/mips/cpu/start.S +2 -0
@@ -185,6 +185,8 @@ reset:
        PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
        sw      sp, 0(t0)
 #endif
+       /* Initialize args to zero. */
+       li      a0, 0x0

please create a separate patch for this change. Also the code must be
compatible with MIPS64 now, so please do:

Quoted 3 lines
Quoted 1 line

PTR_LI a0, 0

ack.

I was mistaken, li would work too. Anyway a better approach would be

move a0, zero

Please use that, thanks.

Signature · 1 line
- Daniel