MIPS: sync asm header files with linux-4.4

index 3faac37..aecc8ce 100644
@@ -7,9 +7,6 @@
 #ifndef _MALTA_CONFIG_H
 #define _MALTA_CONFIG_H
 
-#include <asm/addrspace.h>
-#include <asm/malta.h>
-
 /*
  * System configuration
  */

@@ -83,14 +80,14 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(115200 * 16)
-#define CONFIG_SYS_NS16550_COM1		CKSEG1ADDR(MALTA_GT_UART0_BASE)
-#define CONFIG_SYS_NS16550_COM2		CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
+#define CONFIG_SYS_NS16550_COM1		0xb80003f8
+#define CONFIG_SYS_NS16550_COM2		0xbb0003f8
 #define CONFIG_CONS_INDEX		1
 
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_FLASH_BASE		(KSEG1 | MALTA_FLASH_BASE)
+#define CONFIG_SYS_FLASH_BASE		0xbe000000
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	128
 #define CONFIG_SYS_FLASH_CFI

index 79562f7..cae4a21 100644
@@ -53,8 +53,9 @@ static void malta_lcd_puts(const char *str)
 static enum core_card malta_core_card(void)
 {
 	u32 corid, rev;
+	const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
 
-	rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+	rev = __raw_readl(reg);
 	corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
 
 	switch (corid) {

index 0a1c5fc..67da6a8 100644
@@ -80,12 +80,14 @@ void vct_pin_mux_initialize(void);
  */
 static inline void reg_write(u32 addr, u32 data)
 {
-	__raw_writel(data, addr + REG_GLOBAL_START_ADDR);
+	void *reg = (void *)(addr + REG_GLOBAL_START_ADDR);
+	__raw_writel(data, reg);
 }
 
 static inline u32 reg_read(u32 addr)
 {
-	return __raw_readl(addr + REG_GLOBAL_START_ADDR);
+	const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR);
+	return __raw_readl(reg);
 }
 
 #endif /* _VCT_H */

index b768bb5..e7fe6ed 100644
@@ -10,6 +10,8 @@
 #ifndef _ASM_ADDRSPACE_H
 #define _ASM_ADDRSPACE_H
 
+#include <spaces.h>
+
 /*
  *  Configure language
  */

@@ -50,7 +52,7 @@
  */
 #define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
 #define XPHYSADDR(a)		((_ACAST64_(a)) &			\
-				 _CONST64_(0x000000ffffffffff))
+				 _CONST64_(0x0000ffffffffffff))
 
 #ifdef CONFIG_64BIT
 

new file mode 100644
index 0000000..c872bfd
@@ -0,0 +1,27 @@
+/* const.h: Macros for dealing with constants.  */
+
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally.  We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)	X
+#define _AT(T,X)	X
+#else
+#define __AC(X,Y)	(X##Y)
+#define _AC(X,Y)	__AC(X,Y)
+#define _AT(T,X)	((T)(X))
+#endif
+
+#define _BITUL(x)	(_AC(1,UL) << (x))
+#define _BITULL(x)	(_AC(1,ULL) << (x))
+
+#endif /* !(_LINUX_CONST_H) */

new file mode 100644
index 0000000..a6e9d94
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <cpu-feature-overrides.h>
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits			0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses	0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits			1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses	1
+# endif
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */

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new file mode 100644
index 0000000..613f844
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ...	 */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */

new file mode 100644
index 0000000..6b191d5
@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+						phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+						unsigned long flags)
+{
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return 0;
+}
+
+#define _page_cachable_default	_CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */

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index b768bb5..e7fe6ed 100644
@@ -10,6 +10,8 @@
 #ifndef _ASM_ADDRSPACE_H
 #define _ASM_ADDRSPACE_H
 
+#include <spaces.h>
+
 /*
  *  Configure language
  */

@@ -50,7 +52,7 @@
  */
 #define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
 #define XPHYSADDR(a)		((_ACAST64_(a)) &			\
-				 _CONST64_(0x000000ffffffffff))
+				 _CONST64_(0x0000ffffffffffff))
 
 #ifdef CONFIG_64BIT
 

new file mode 100644
index 0000000..c872bfd
@@ -0,0 +1,27 @@
+/* const.h: Macros for dealing with constants.  */
+
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally.  We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)	X
+#define _AT(T,X)	X
+#else
+#define __AC(X,Y)	(X##Y)
+#define _AC(X,Y)	__AC(X,Y)
+#define _AT(T,X)	((T)(X))
+#endif
+
+#define _BITUL(x)	(_AC(1,UL) << (x))
+#define _BITULL(x)	(_AC(1,ULL) << (x))
+
+#endif /* !(_LINUX_CONST_H) */

new file mode 100644
index 0000000..a6e9d94
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <cpu-feature-overrides.h>
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits			0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses	0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits			1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses	1
+# endif
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */

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new file mode 100644
index 0000000..613f844
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ...	 */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */

new file mode 100644
index 0000000..6b191d5
@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+						phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+						unsigned long flags)
+{
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return 0;
+}
+
+#define _page_cachable_default	_CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */

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index 8c9c4e2..44694a3 100644
@@ -1,8 +1,4 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
  * Copyright (C) 1999 by Silicon Graphics, Inc.
  * Copyright (C) 2001 MIPS Technologies, Inc.

@@ -13,6 +9,8 @@
  * Some of the routines below contain useless nops that will be optimized
  * away by gas in -O mode. These nops are however required to fill delay
  * slots in noreorder mode.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef __ASM_ASM_H
 #define __ASM_ASM_H

@@ -33,58 +31,58 @@
  * Not used for the kernel but here seems to be the right place.
  */
 #ifdef __PIC__
-#define CPRESTORE(register)                             \
+#define CPRESTORE(register)				\
 		.cprestore register
-#define CPADD(register)                                 \
+#define CPADD(register)					\
 		.cpadd	register
-#define CPLOAD(register)                                \
-		.cpload	register
+#define CPLOAD(register)				\
+		.cpload register
 #else
 #define CPRESTORE(register)
 #define CPADD(register)
 #define CPLOAD(register)
 #endif
 
-#define ENTRY(symbol)                                   \
-		.globl	symbol;                         \
-		.type	symbol, @function;              \
-		.ent	symbol, 0;                      \
+#define ENTRY(symbol)					\
+		.globl	symbol;				\
+		.type	symbol, @function;		\
+		.ent	symbol, 0;			\
 symbol:
 
 /*
  * LEAF - declare leaf routine
  */
-#define	LEAF(symbol)                                    \
-		.globl	symbol;                         \
-		.align	2;                              \
-		.type	symbol, @function;              \
-		.ent	symbol, 0;                      \
+#define LEAF(symbol)					\
+		.globl	symbol;				\
+		.align	2;				\
+		.type	symbol, @function;		\
+		.ent	symbol, 0;			\
 		.section .text.symbol, "x";             \
 symbol:		.frame	sp, 0, ra
 
 /*
  * NESTED - declare nested routine entry point
  */
-#define	NESTED(symbol, framesize, rpc)                  \
-		.globl	symbol;                         \
-		.align	2;                              \
-		.type	symbol, @function;              \
-		.ent	symbol, 0;                      \
+#define NESTED(symbol, framesize, rpc)			\
+		.globl	symbol;				\
+		.align	2;				\
+		.type	symbol, @function;		\
+		.ent	symbol, 0;			\
 		.section .text.symbol, "x";             \
 symbol:		.frame	sp, framesize, rpc
 
 /*
  * END - mark end of function
  */
-#define	END(function)                                   \
-		.end	function;		        \
+#define END(function)					\
+		.end	function;			\
 		.size	function, .-function
 
 /*
  * EXPORT - export definition of symbol
  */
 #define EXPORT(symbol)					\
-		.globl	symbol;                         \
+		.globl	symbol;				\
 symbol:
 
 /*

@@ -98,16 +96,16 @@ symbol:
 /*
  * ABS - export absolute symbol
  */
-#define	ABS(symbol,value)                               \
-		.globl	symbol;                         \
+#define ABS(symbol,value)				\
+		.globl	symbol;				\
 symbol		=	value
 
-#define	PANIC(msg)                                      \
+#define PANIC(msg)					\
 		.set	push;				\
-		.set	reorder;                        \
-		PTR_LA	a0, 8f;                          \
-		jal	panic;                          \
-9:		b	9b;                             \
+		.set	reorder;			\
+		PTR_LA	a0, 8f;				 \
+		jal	panic;				\
+9:		b	9b;				\
 		.set	pop;				\
 		TEXT(msg)
 

@@ -115,31 +113,31 @@ symbol		=	value
  * Print formatted string
  */
 #ifdef CONFIG_PRINTK
-#define PRINT(string)                                   \
+#define PRINT(string)					\
 		.set	push;				\
-		.set	reorder;                        \
-		PTR_LA	a0, 8f;                          \
-		jal	printk;                         \
+		.set	reorder;			\
+		PTR_LA	a0, 8f;				 \
+		jal	printk;				\
 		.set	pop;				\
 		TEXT(string)
 #else
 #define PRINT(string)
 #endif
 
-#define	TEXT(msg)                                       \
+#define TEXT(msg)					\
 		.pushsection .data;			\
-8:		.asciiz	msg;                            \
+8:		.asciiz msg;				\
 		.popsection;
 
 /*
  * Build text tables
  */
-#define TTABLE(string)                                  \
+#define TTABLE(string)					\
 		.pushsection .text;			\
-		.word	1f;                             \
+		.word	1f;				\
 		.popsection				\
 		.pushsection .data;			\
-1:		.asciiz	string;                         \
+1:		.asciiz string;				\
 		.popsection
 
 /*

@@ -151,21 +149,29 @@ symbol		=	value
  */
 #ifdef CONFIG_CPU_HAS_PREFETCH
 
-#define PREF(hint,addr)                                 \
+#define PREF(hint, addr)				\
 		.set	push;				\
-		.set	mips4;				\
+		.set	arch=r5000;			\
 		pref	hint, addr;			\
 		.set	pop
 
-#define PREFX(hint,addr)                                \
+#define PREFE(hint, addr)				\
+		.set	push;				\
+		.set	mips0;				\
+		.set	eva;				\
+		prefe	hint, addr;			\
+		.set	pop
+
+#define PREFX(hint, addr)				\
 		.set	push;				\
-		.set	mips4;				\
+		.set	arch=r5000;			\
 		prefx	hint, addr;			\
 		.set	pop
 
 #else /* !CONFIG_CPU_HAS_PREFETCH */
 
 #define PREF(hint, addr)
+#define PREFE(hint, addr)
 #define PREFX(hint, addr)
 
 #endif /* !CONFIG_CPU_HAS_PREFETCH */

@@ -174,42 +180,42 @@ symbol		=	value
  * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
  */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt)                                \
+#define MOVN(rd, rs, rt)				\
 		.set	push;				\
 		.set	reorder;			\
-		beqz	rt, 9f;                         \
-		move	rd, rs;                         \
+		beqz	rt, 9f;				\
+		move	rd, rs;				\
 		.set	pop;				\
 9:
-#define MOVZ(rd, rs, rt)                                \
+#define MOVZ(rd, rs, rt)				\
 		.set	push;				\
 		.set	reorder;			\
-		bnez	rt, 9f;                         \
-		move	rd, rs;                         \
+		bnez	rt, 9f;				\
+		move	rd, rs;				\
 		.set	pop;				\
 9:
 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt)                                \
+#define MOVN(rd, rs, rt)				\
 		.set	push;				\
 		.set	noreorder;			\
-		bnezl	rt, 9f;                         \
-		 move	rd, rs;                         \
+		bnezl	rt, 9f;				\
+		 move	rd, rs;				\
 		.set	pop;				\
 9:
-#define MOVZ(rd, rs, rt)                                \
+#define MOVZ(rd, rs, rt)				\
 		.set	push;				\
 		.set	noreorder;			\
-		beqzl	rt, 9f;                         \
-		 move	rd, rs;                         \
+		beqzl	rt, 9f;				\
+		 move	rd, rs;				\
 		.set	pop;				\
 9:
 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
     (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt)                                \
+#define MOVN(rd, rs, rt)				\
 		movn	rd, rs, rt
-#define MOVZ(rd, rs, rt)                                \
+#define MOVZ(rd, rs, rt)				\
 		movz	rd, rs, rt
 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
 

@@ -304,6 +310,7 @@ symbol		=	value
 #define LONG_SUBU	subu
 #define LONG_L		lw
 #define LONG_S		sw
+#define LONG_SP		swp
 #define LONG_SLL	sll
 #define LONG_SLLV	sllv
 #define LONG_SRL	srl

@@ -326,6 +333,7 @@ symbol		=	value
 #define LONG_SUBU	dsubu
 #define LONG_L		ld
 #define LONG_S		sd
+#define LONG_SP		sdp
 #define LONG_SLL	dsll
 #define LONG_SLLV	dsllv
 #define LONG_SRL	dsrl

index 24c6cda..3d79ebc 100644
@@ -4,6 +4,8 @@
  * of Coprocessor 0 registers.
  *
  * Copyright (c) 1998 Harald Koerfgen
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef __ASM_ISADEP_H

@@ -18,7 +20,7 @@
  * kernel or user mode? (CP0_STATUS)
  */
 #define KU_MASK 0x08
-#define	KU_USER 0x08
+#define KU_USER 0x08
 #define KU_KERN 0x00
 
 #else

@@ -26,7 +28,7 @@
  * kernel or user mode?
  */
 #define KU_MASK 0x18
-#define	KU_USER 0x10
+#define KU_USER 0x10
 #define KU_KERN 0x00
 
 #endif

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index ba7f538..02a3b16 100644
@@ -1,12 +1,10 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1994 Waldorf GMBH
  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
  * Copyright (C) 1996 Paul M. Antoine
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_PROCESSOR_H
 #define _ASM_PROCESSOR_H

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index 2e65cc3..f1efc45 100644
@@ -1,11 +1,11 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1985 MIPS Computer Systems, Inc.
  * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
  * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2011 Wind River Systems,
+ *   written by Ralf Baechle <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_REGDEF_H
 #define _ASM_REGDEF_H

@@ -30,9 +30,13 @@
 #define t2	$10
 #define t3	$11
 #define t4	$12
+#define ta0	$12
 #define t5	$13
+#define ta1	$13
 #define t6	$14
+#define ta2	$14
 #define t7	$15
+#define ta3	$15
 #define s0	$16	/* callee saved */
 #define s1	$17
 #define s2	$18

index e245614..bf8ff59 100644
@@ -27,7 +27,7 @@ static inline unsigned long icache_line_size(void)
 {
 	unsigned long conf1, il;
 	conf1 = read_c0_config1();
-	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
+	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
 	if (!il)
 		return 0;
 	return 2 << il;

@@ -37,7 +37,7 @@ static inline unsigned long dcache_line_size(void)
 {
 	unsigned long conf1, dl;
 	conf1 = read_c0_config1();
-	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
+	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
 	if (!dl)
 		return 0;
 	return 2 << dl;

index e7fe6ed..0994e96 100644
@@ -1,11 +1,9 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1996, 99 Ralf Baechle
  * Copyright (C) 2000, 2002  Maciej W. Rozycki
  * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_ADDRSPACE_H
 #define _ASM_ADDRSPACE_H

index c31ff6e..cce6995 100644
@@ -1,10 +1,8 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (c) 1994 - 1997, 1999, 2000  Ralf Baechle (ralf at gnu.org)
  * Copyright (c) 2000  Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_BITOPS_H
 #define _ASM_BITOPS_H

index b5e685f..67fdf71 100644
@@ -1,9 +1,7 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_BYTEORDER_H
 #define _ASM_BYTEORDER_H

index f3ce721..5e77dfa 100644
@@ -1,9 +1,7 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef	_ASM_CACHECTL
 #define	_ASM_CACHECTL

index af2adc7..a3b07c6 100644
@@ -1,12 +1,10 @@
 /*
  * Cache operations for the cache instruction.
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
  * (C) Copyright 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef	__ASM_CACHEOPS_H
 #define	__ASM_CACHEOPS_H

index c872bfd..f600e7a 100644
@@ -1,4 +1,8 @@
-/* const.h: Macros for dealing with constants.  */
+/*
+ * const.h: Macros for dealing with constants.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
 
 #ifndef _LINUX_CONST_H
 #define _LINUX_CONST_H

index 4deac52..90c0aff 100644
@@ -1,10 +1,7 @@
-/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
+/*
  * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_POSIX_TYPES_H
 #define _ASM_POSIX_TYPES_H

index 978d206..2a6b724 100644
@@ -1,10 +1,8 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
  * Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_REBOOT_H
 #define _ASM_REBOOT_H

index fc6bc0c..af6fbb4 100644
@@ -2,12 +2,10 @@
  * Various register offset definitions for debuggers, core file
  * examiners and whatnot.
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1995, 1999 by Ralf Baechle
  * Copyright (C) 1995, 1999 Silicon Graphics
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef __ASM_MIPS_REG_H
 #define __ASM_MIPS_REG_H

index 67f2658..2a03886 100644
@@ -1,11 +1,9 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1996, 1999, 2001 Ralf Baechle
  * Copyright (C) 1999 Silicon Graphics, Inc.
  * Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef __ASM_SGIDEFS_H
 #define __ASM_SGIDEFS_H

index 579a591..1fbe899 100644
@@ -1,11 +1,9 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
  * Copyright (c) 2000 by Silicon Graphics, Inc.
  * Copyright (c) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_STRING_H
 #define _ASM_STRING_H

index d56f73b..e6435cc 100644
@@ -1,8 +1,4 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1994 - 1999 by Ralf Baechle
  * Copyright (C) 1996 by Paul M. Antoine
  * Copyright (C) 1994 - 1999 by Ralf Baechle

@@ -12,6 +8,8 @@
  *
  * Kevin D. Kissell, kevink at mips.org and Carsten Langgaard, carstenl at mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_SYSTEM_H
 #define _ASM_SYSTEM_H

index aebafdb..627440d 100644
@@ -1,10 +1,8 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
  * Copyright (C) 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_TYPES_H
 #define _ASM_TYPES_H

index c25a846..eebe06a 100644
@@ -1,9 +1,7 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 2007 Ralf Baechle (ralf at linux-mips.org)
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef _ASM_MIPS_UNALIGNED_H
 #define _ASM_MIPS_UNALIGNED_H

index 0dfb54e..806bd26 100644
@@ -7,15 +7,9 @@
 #ifndef __MIPS_CACHE_H__
 #define __MIPS_CACHE_H__
 
-/*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	128
-#endif
+#define L1_CACHE_SHIFT		CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
 
 #endif /* __MIPS_CACHE_H__ */

index cfefc72..6aba404 100644
@@ -545,4 +545,58 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 {
 }
 
+#define __BUILD_CLRBITS(bwlq, sfx, end, type)				\
+									\
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr)	\
+{									\
+	type __val = __raw_read##bwlq(mem);				\
+	__val = end##_to_cpu(__val);					\
+	__val &= ~clr;							\
+	__val = cpu_to_##end(__val);					\
+	__raw_write##bwlq(__val, mem);					\
+}
+
+#define __BUILD_SETBITS(bwlq, sfx, end, type)				\
+									\
+static inline void setbits_##sfx(volatile void __iomem *mem, type set)	\
+{									\
+	type __val = __raw_read##bwlq(mem);				\
+	__val = end##_to_cpu(__val);					\
+	__val |= set;							\
+	__val = cpu_to_##end(__val);					\
+	__raw_write##bwlq(__val, mem);					\
+}
+
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type)			\
+									\
+static inline void clrsetbits_##sfx(volatile void __iomem *mem,		\
+					type clr, type set)		\
+{									\
+	type __val = __raw_read##bwlq(mem);				\
+	__val = end##_to_cpu(__val);					\
+	__val &= ~clr;							\
+	__val |= set;							\
+	__val = cpu_to_##end(__val);					\
+	__raw_write##bwlq(__val, mem);					\
+}
+
+#define BUILD_CLRSETBITS(bwlq, sfx, type)				\
+									\
+__BUILD_CLRBITS(bwlq, sfx, sfx, type)					\
+__BUILD_SETBITS(bwlq, sfx, sfx, type)					\
+__BUILD_CLRSETBITS(bwlq, sfx, sfx, type)
+
+#define __to_cpu(v)		(v)
+#define cpu_to__(v)		(v)
+
+__BUILD_CLRBITS(b, 8, _, u8)
+__BUILD_SETBITS(b, 8, _, u8)
+__BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, u16)
+BUILD_CLRSETBITS(w, be16, u16)
+BUILD_CLRSETBITS(l, le32, u32)
+BUILD_CLRSETBITS(l, be32, u32)
+BUILD_CLRSETBITS(q, le64, u64)
+BUILD_CLRSETBITS(q, be64, u64)
+
 #endif /* _ASM_IO_H */

index b2d4a09..e80990e 100644
@@ -5,8 +5,191 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
+#include <asm/io.h>
+
 /*
  * mips_io_port_base is the begin of the address space to which x86 style
  * I/O ports are mapped.
  */
 const unsigned long mips_io_port_base = -1;
+
+static const void __iomem *addr1 = (const void __iomem *)CKSEG1ADDR(0x80000000);
+static void __iomem *addr2 = (void __iomem *)CKSEG1ADDR(0x80001000);
+
+void test_readb(void)
+{
+	u8 val = readb(addr1);
+	writeb(val, addr2);
+}
+
+void test_readw(void)
+{
+	u16 val = readw(addr1);
+	writew(val, addr2);
+}
+
+void test_readl(void)
+{
+	u32 val = readl(addr1);
+	writel(val, addr2);
+}
+
+void test_readq(void)
+{
+	u32 val = readq(addr1);
+	writeq(val, addr2);
+}
+
+void test_readb_be(void)
+{
+	u8 val = readb_be(addr1);
+	writeb_be(val, addr2);
+}
+
+void test_readw_be(void)
+{
+	u16 val = readw_be(addr1);
+	writew_be(val, addr2);
+}
+
+void test_readl_be(void)
+{
+	u32 val = readl_be(addr1);
+	writel_be(val, addr2);
+}
+
+void test_readq_be(void)
+{
+	u32 val = readq_be(addr1);
+	writeq_be(val, addr2);
+}
+
+void test_raw_readb(void)
+{
+	u8 val = __raw_readb(addr1);
+	__raw_writeb(val, addr2);
+}
+
+void test_raw_readw(void)
+{
+	u16 val = __raw_readw(addr1);
+	__raw_writew(val, addr2);
+}
+
+void test_raw_readl(void)
+{
+	u32 val = __raw_readl(addr1);
+	__raw_writel(val, addr2);
+}
+
+void test_raw_readq(void)
+{
+	u32 val = __raw_readq(addr1);
+	__raw_writeq(val, addr2);
+}
+
+void test_clrbits_8(void)
+{
+	clrbits_8(addr2, BIT(2));
+}
+
+void test_setbits_8(void)
+{
+	setbits_8(addr2, BIT(3));
+}
+
+void test_clrsetbits_8(void)
+{
+	clrsetbits_8(addr2, BIT(2), BIT(3));
+}
+
+void test_clrbits_le16(void)
+{
+	clrbits_le16(addr2, BIT(9));
+}
+
+void test_setbits_le16(void)
+{
+	setbits_le16(addr2, BIT(10));
+}
+
+void test_clrsetbits_le16(void)
+{
+	clrsetbits_le16(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be16(void)
+{
+	clrbits_be16(addr2, BIT(9));
+}
+
+void test_setbits_be16(void)
+{
+	setbits_be16(addr2, BIT(10));
+}
+
+void test_clrsetbits_be16(void)
+{
+	clrsetbits_be16(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_le32(void)
+{
+	clrbits_le32(addr2, BIT(9));
+}
+
+void test_setbits_le32(void)
+{
+	setbits_le32(addr2, BIT(10));
+}
+
+void test_clrsetbits_le32(void)
+{
+	clrsetbits_le32(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be32(void)
+{
+	clrbits_be32(addr2, BIT(9));
+}
+
+void test_setbits_be32(void)
+{
+	setbits_be32(addr2, BIT(10));
+}
+
+void test_clrsetbits_be32(void)
+{
+	clrsetbits_be32(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_le64(void)
+{
+	clrbits_le64(addr2, BIT(9));
+}
+
+void test_setbits_le64(void)
+{
+	setbits_le64(addr2, BIT(10));
+}
+
+void test_clrsetbits_le64(void)
+{
+	clrsetbits_le64(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be64(void)
+{
+	clrbits_be64(addr2, BIT(9));
+}
+
+void test_setbits_be64(void)
+{
+	setbits_be64(addr2, BIT(10));
+}
+
+void test_clrsetbits_be64(void)
+{
+	clrsetbits_be64(addr2, BIT(9), BIT(10));
+}