arm64: dts: r8a7795: Add L2 cache-controller nodes
Subsystems (3)
PATCH v2 1/1 arm64: dts: r8a7795: Add L2 cache-controller nodes
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
---
Changes in v2: Dropped the not yet merged Cortex A53 part.
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +8 -0
@@ -39,6 +39,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; };
@@ -46,22 +47,29 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_2: cpu at 2 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x2>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_3: cpu at 3 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x3>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; }; + L2_CA57: cache-controller at 0 { + compatible = "cache"; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;
Signature · 1 line
2.7.0
PATCH v2 1/1 arm64: dts: r8a7795: Add L2 cache-controller nodes
Quoted 49 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>---
Changes in v2: Dropped the not yet merged Cortex A53 part.arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm64/boot/dts/renesas/r8a7795.dtsi +4
-0@@ -39,6 +39,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; };@@ -46,22 +47,29 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_2: cpu at 2 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x2>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_3: cpu at 3 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x3>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci";
arch/arm64/boot/dts/renesas/r8a7795.dtsi line 75
Quoted 10 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +4
-0}; }; + L2_CA57: cache-controller at 0 { + compatible = "cache"; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;
Any further comments to this? If not, could this be applied?
Best regards
Dirk
PATCH v2 1/1 arm64: dts: r8a7795: Add L2 cache-controller nodes
[CC new linux-renesas-soc ML]
Hi Dirk,
Quoted 11 lines · Dirk Behme
Quoted 10 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>
[snip]
Quoted 1 line
Any further comments to this? If not, could this be applied?
Sorry for the delay.
This looks good; I have queued it up.
It should appear in the next (and devel) branches of my renesas tree soon. And in linux-next whenever it includes my updated next branch.
PATCH v2 1/1 arm64: dts: r8a7795: Add L2 cache-controller nodes
Hi Dirk,
Quoted 15 lines · Simon Horman
Quoted 11 lines · Dirk Behme
Quoted 10 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>[snip]
Quoted 8 lines
Quoted 1 line
Any further comments to this? If not, could this be applied?
Sorry for the delay.
This looks good; I have queued it up.
It should appear in the next (and devel) branches of my renesas tree soon. And in linux-next whenever it includes my updated next branch.
So you not only dropped the (controversial) timing related properties, but in addition:
+ cache-unified;
+ cache-level = <2>;
At least the "cache-level" property is marked as required in ePAPR. For "cache-unified", the wording is not that strict in ePAPR, but that property depends on being a unified cache in the first place.
So I think these two properties should be re-added.
Sorry for not noticing before.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v2 1/1 arm64: dts: r8a7795: Add L2 cache-controller nodes
Quoted 33 lines · Geert Uytterhoeven
Hi Dirk,
Quoted 15 lines · Simon Horman
Quoted 11 lines · Dirk Behme
Quoted 10 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>[snip]
Quoted 8 lines
Quoted 1 line
Any further comments to this? If not, could this be applied?
Sorry for the delay.
This looks good; I have queued it up.
It should appear in the next (and devel) branches of my renesas tree soon. And in linux-next whenever it includes my updated next branch.
So you not only dropped the (controversial) timing related properties, but in addition:
(quoted diff) +2
-0+ cache-unified; + cache-level = <2>;
Quoted 5 lines
At least the "cache-level" property is marked as required in ePAPR. For "cache-unified", the wording is not that strict in ePAPR, but that property depends on being a unified cache in the first place.
So I think these two properties should be re-added.
If I remember correctly, first, these entries are not used at all on ARMv8. And second, I think it was mentioned that we therefore want to drop them:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394936.html
Best regards
Dirk
PATCH v2 1/1 arm64: dts: r8a7795: Add L2 cache-controller nodes
Hi Dirk,
Quoted 38 lines · Dirk Behme
Quoted 37 lines · Geert Uytterhoeven
Quoted 17 lines · Simon Horman
Quoted 11 lines · Dirk Behme
Quoted 10 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>[snip]
Quoted 1 line
Any further comments to this? If not, could this be applied?
Quoted 7 lines
Sorry for the delay.
This looks good; I have queued it up.
It should appear in the next (and devel) branches of my renesas tree soon.
And in linux-next whenever it includes my updated next branch.So you not only dropped the (controversial) timing related properties, but in addition:
(quoted diff) +2
-0+ cache-unified; + cache-level = <2>;At least the "cache-level" property is marked as required in ePAPR. For "cache-unified", the wording is not that strict in ePAPR, but that property
depends on being a unified cache in the first place.
Quoted 8 lines
Quoted 1 line
So I think these two properties should be re-added.
If I remember correctly, first, these entries are not used at all on ARMv8. And second, I think it was mentioned that we therefore want to drop them:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394936.html
I believe the discussion was only about the latency properties, which are documented in the l2c2x0 DT bindings, and deemed to not apply here (CC Sudeep).
The DT bindings documented in ePAPR are generic, and apply to all hardware, unless extended or overridden by more-specific DT bindings.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v2 1/1 arm64: dts: r8a7795: Add L2 cache-controller nodes
Hi Geert,
Quoted 46 lines · Geert Uytterhoeven
Hi Dirk,
Quoted 43 lines · Dirk Behme
Quoted 32 lines · Geert Uytterhoeven
Quoted 17 lines · Simon Horman
Quoted 11 lines · Dirk Behme
Quoted 10 lines · Dirk Behme
From: Geert Uytterhoeven <[email protected]>
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways).
Signed-off-by Geert Uytterhoeven <[email protected]>Signed-off-by Dirk Behme <[email protected]>[snip]
Quoted 1 line
Any further comments to this? If not, could this be applied?
Quoted 7 lines
Sorry for the delay.
This looks good; I have queued it up.
It should appear in the next (and devel) branches of my renesas tree soon.
And in linux-next whenever it includes my updated next branch.So you not only dropped the (controversial) timing related properties, but in addition:
(quoted diff) +2
-0+ cache-unified; + cache-level = <2>;Quoted 6 lines
At least the "cache-level" property is marked as required in ePAPR. For "cache-unified", the wording is not that strict in ePAPR, but that property
depends on being a unified cache in the first place.So I think these two properties should be re-added.
If I remember correctly, first, these entries are not used at all on ARMv8. And second, I think it was mentioned that we therefore want to drop them:
Quoted 6 lines
I believe the discussion was only about the latency properties, which are documented in the l2c2x0 DT bindings, and deemed to not apply here
Hmm, the two bindings cache-unified and cache-level are documented in bindings/arm/l2c2x0.txt, too.
Quoted 2 lines
The DT bindings documented in ePAPR are generic, and apply to all hardware, unless extended or overridden by more-specific DT bindings.
I still can't see the benefit of adding entries to the device tree which are not used at all (and most probably don't make sense on that platform). But if anybody has a different opinion and maybe good arguments for it, that would be fine, too :)
Best regards
Dirk