ARM: ARMv7: PSCI: add PSCI v1.0 support

-----Original Message-----
From: Chenhui Zhao
Sent: Wednesday, March 16, 2016 3:05 PM
To: Hongbo Zhang <[email protected]>
Cc: trini at konsulko.com; sbabic at denx.de; ijc at hellion.org.uk; hdegoede at redhat.com; twarren at nvidia.com; Huan Wang <[email protected]>; york sun <[email protected]>;
jan.kiszka at siemens.com; Frank Li <[email protected]>; Peng Fan <[email protected]>; Zhengxiong Jin <[email protected]>;
oss at buserror.net; u-boot at lists.denx.de; albert.u.boot at aribaud.net
Subject: Re: [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared

Add Hongbo.

Thanks,
Chenhui

________________________________________
From: Dongsheng Wang <[email protected]>
Sent: Monday, January 18, 2016 12:27 PM
To: albert.u.boot at aribaud.net
Cc: trini at konsulko.com; sbabic at denx.de; ijc at hellion.org.uk; hdegoede at redhat.com; twarren at nvidia.com; Huan Wang; york sun; jan.kiszka at siemens.com; Frank Li; Peng Fan; Zhengxiong Jin; Chenhui Zhao; oss at buserror.net; u-boot at lists.denx.de; Dongsheng Wang
Subject: [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared

From: Wang Dongsheng <[email protected]>

All of cpu share the same targetPC space that is unsafe. So move target PC save space into CPU stack.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S     |  4 +--
 arch/arm/cpu/armv7/mx7/psci.S         |  4 +--
 arch/arm/cpu/armv7/psci.S             | 51 ++++++++++++++++++++++++++++----
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S |  4 +--
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S |  4 +--
 arch/arm/cpu/armv7/virt-dt.c          |  3 ++-
 arch/arm/include/asm/psci.h           |  4 +++
 arch/arm/mach-tegra/psci.S            |  4 +--
 8 files changed, 53 insertions(+), 25 deletions(-)

arch/arm/cpu/armv7/ls102xa/psci.S +1 -3

index 0b067d9..3a34064 100644
@@ -36,9 +36,7 @@ psci_cpu_on:
        and     r1, r1, #0xff
 
        mov     r0, r1
-       bl      psci_get_cpu_stack_top
-       str     r2, [r0]
-       dsb
+       bl      psci_save_target_pc
 
        @ Get DCFG base address
        movw    r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)

arch/arm/cpu/armv7/mx7/psci.S +1 -3

index 34c6ab3..cb39f27 100644
@@ -30,9 +30,7 @@ psci_cpu_on:
        push    {lr}
 
        mov     r0, r1
-       bl      psci_get_cpu_stack_top
-       str     r2, [r0]
-       dsb
+       bl      psci_save_target_pc
 
        ldr     r2, =psci_cpu_entry
        bl      imx_cpu_on

arch/arm/cpu/armv7/psci.S +2 -0

index 2425f6a..0e0f98e 100644
@@ -20,6 +20,8 @@
 #include <asm/macro.h>
 #include <asm/psci.h>
 
+#define SAVE_SPACE_TARGET_PC_OFFSET    0x0
+
        .pushsection ._secure.text, "ax"
 
        .arch_extension sec

@@ -196,27 +198,58 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)

arch/arm/cpu/armv7/psci.S +5 -2

+       cmp     r4, #0
+       beq     out_psci_stack_align
+       add     r5, r5, #PSCI_STACK_ALIGN_SIZE
+       lsr     r5, r5, #12
        lsl     r5, r5, #12
-       sub     r5, r5, #4                      @ reserve 1 word for target PC
-       sub     r0, r5, r0                      @ here's our stack!
+

arch/arm/cpu/armv7/psci.S +19 -2

+
+       bx      r10
+ENDPROC(psci_get_cpu_save_space)
+
+@ Expects cpu ID in r0 and PC in r2, please ignore the return value.
+ENTRY(psci_save_target_pc)
+       push    {lr}
+
+       @ Save target PC into stack
+       bl      psci_get_cpu_save_space
+       str     r2, [r0, #SAVE_SPACE_TARGET_PC_OFFSET]
+       dsb
+
+       pop     {lr}
+       bx      lr
+ENDPROC(psci_save_target_pc)
+
 ENTRY(psci_cpu_entry)
        bl      psci_enable_smp
 
        bl      _nonsec_init
 
        bl      psci_get_cpu_id                 @ CPU ID => r0
-       bl      psci_get_cpu_stack_top          @ stack top => r0
-       ldr     r0, [r0]                        @ target PC at stack top
+       bl      psci_get_cpu_save_space
+       ldr     r0, [r0, #SAVE_SPACE_TARGET_PC_OFFSET]
        b       _do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 

arch/arm/cpu/armv7/sunxi/psci_sun6i.S +1 -3

index b96c5ef..e8981af 100644
@@ -135,9 +135,7 @@ psci_cpu_on:
        push    {lr}
 
        mov     r0, r1
-       bl      psci_get_cpu_stack_top  @ get stack top of target CPU
-       str     r2, [r0]                @ store target PC at stack top
-       dsb
+       bl      psci_save_target_pc
 
        movw    r0, #(SUN6I_CPUCFG_BASE & 0xffff)
        movt    r0, #(SUN6I_CPUCFG_BASE >> 16)

arch/arm/cpu/armv7/sunxi/psci_sun7i.S +1 -3

index 59d7ff0..a1fcc71 100644
@@ -124,9 +124,7 @@ psci_cpu_on:
        push    {lr}
 
        mov     r0, r1
-       bl      psci_get_cpu_stack_top  @ get stack top of target CPU
-       str     r2, [r0]                @ store target PC at stack top
-       dsb
+       bl      psci_save_target_pc
 
        movw    r0, #(SUN7I_CPUCFG_BASE & 0xffff)
        movt    r0, #(SUN7I_CPUCFG_BASE >> 16)

arch/arm/cpu/armv7/virt-dt.c +1 -1

index f1251d1..5ca353c 100644
@@ -126,7 +126,8 @@ int psci_update_dt(void *fdt)
 #ifndef CONFIG_ARMV7_SECURE_BASE
        /* secure code lives in RAM, keep it alive */
        fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
-                       __secure_end - __secure_start);
+                       __secure_end + CONFIG_MAX_CPUS *

PSCI_PERCPU_STACK_SIZE

arch/arm/cpu/armv7/virt-dt.c +1 -0

+                       + PSCI_STACK_ALIGN_SIZE - __secure_start);
 #endif
 
        return fdt_psci(fdt);

arch/arm/include/asm/psci.h +4 -0

index f7b8f65..274dbda 100644
@@ -18,6 +18,10 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
+#define PSCI_STACK_ALIGN_SIZE          0x1000
+
+/* 1kB for percpu stack */
+#define PSCI_PERCPU_STACK_SIZE         0x400
 
 #define PSCI_FN_BASE                   0x84000000
 #define PSCI_FN_ID(n)                  (PSCI_FN_BASE + (n))

arch/arm/mach-tegra/psci.S +1 -4

index 5f326c9..e83566e 100644
@@ -91,9 +91,7 @@ ENTRY(psci_cpu_on)
        push    {lr}
 
        mov     r0, r1
-       bl      psci_get_cpu_stack_top  @ get stack top of target CPU
-       str     r2, [r0]                @ store target PC at stack top
-       dsb
+       bl      psci_save_target_pc
 
        ldr     r6, =TEGRA_RESET_EXCEPTION_VECTOR
        ldr     r5, =psci_cpu_entry
--

2.1.0.27.g96db324

Hi Dongsheng,

Quoted 93 lines

-----Original Message-----
From: Chenhui Zhao
Sent: Wednesday, March 16, 2016 3:05 PM
To: Hongbo Zhang <[email protected]>
Cc: trini at konsulko.com; sbabic at denx.de; ijc at hellion.org.uk; hdegoede at redhat.com; twarren at nvidia.com; Huan Wang <[email protected]>; york sun <[email protected]>;
jan.kiszka at siemens.com; Frank Li <[email protected]>; Peng Fan <[email protected]>; Zhengxiong Jin <[email protected]>;
oss at buserror.net; u-boot at lists.denx.de; albert.u.boot at aribaud.net
Subject: Re: [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared

Add Hongbo.

Thanks,
Chenhui

________________________________________
From: Dongsheng Wang <[email protected]>
Sent: Monday, January 18, 2016 12:27 PM
To: albert.u.boot at aribaud.net
Cc: trini at konsulko.com; sbabic at denx.de; ijc at hellion.org.uk; hdegoede at redhat.com; twarren at nvidia.com; Huan Wang; york sun; jan.kiszka at siemens.com; Frank Li; Peng Fan; Zhengxiong Jin; Chenhui Zhao; oss at buserror.net; u-boot at lists.denx.de; Dongsheng Wang
Subject: [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared

From: Wang Dongsheng <[email protected]>

All of cpu share the same targetPC space that is unsafe. So move target PC save space into CPU stack.

Signed-off-by Wang Dongsheng <[email protected]>

---
  arch/arm/cpu/armv7/ls102xa/psci.S     |  4 +--
  arch/arm/cpu/armv7/mx7/psci.S         |  4 +--
  arch/arm/cpu/armv7/psci.S             | 51 ++++++++++++++++++++++++++++----
---
  arch/arm/cpu/armv7/sunxi/psci_sun6i.S |  4 +--
arch/arm/cpu/armv7/sunxi/psci_sun7i.S |  4 +--
  arch/arm/cpu/armv7/virt-dt.c          |  3 ++-
  arch/arm/include/asm/psci.h           |  4 +++
  arch/arm/mach-tegra/psci.S            |  4 +--
  8 files changed, 53 insertions(+), 25 deletions(-)

arch/arm/cpu/armv7/ls102xa/psci.S +1 -3

index 0b067d9..3a34064 100644
@@ -36,9 +36,7 @@ psci_cpu_on:
         and     r1, r1, #0xff
 
         mov     r0, r1
-       bl      psci_get_cpu_stack_top
-       str     r2, [r0]
-       dsb
+       bl      psci_save_target_pc
 
         @ Get DCFG base address
         movw    r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)

arch/arm/cpu/armv7/mx7/psci.S +1 -3

index 34c6ab3..cb39f27 100644
@@ -30,9 +30,7 @@ psci_cpu_on:
         push    {lr}
 
         mov     r0, r1
-       bl      psci_get_cpu_stack_top
-       str     r2, [r0]
-       dsb
+       bl      psci_save_target_pc
 
         ldr     r2, =psci_cpu_entry
         bl      imx_cpu_on

arch/arm/cpu/armv7/psci.S index renamed from arch/arm/cpu/armv7/psci.S +0 -0

2425f6a..0e0f98e 100644

arch/arm/cpu/armv7/psci.S +2 -0

@@ -20,6 +20,8 @@
  #include <asm/macro.h>
  #include <asm/psci.h>
 
+#define SAVE_SPACE_TARGET_PC_OFFSET    0x0
+
         .pushsection ._secure.text, "ax"
 
         .arch_extension sec

@@ -196,27 +198,58 @@ ENDPROC(psci_cpu_off_common)
 

arch/arm/cpu/armv7/psci.S ENDPROC(psci_cpu_off_common) · line 205

Quoted 12 lines

arch/arm/cpu/armv7/psci.S +4 -5

  @ expects CPU ID in r0 and returns stack top in r0
  ENTRY(psci_get_cpu_stack_top)
-       mov     r5, #0x400                      @ 1kB of stack per CPU
-       mul     r0, r0, r5
-
+       @ Align psci_text_end minumum page size. Even if page is greater than
+       @ 4K, we still can ensure that data is always safe access by the CPU.
         ldr     r5, =psci_text_end              @ end of monitor text
-       add     r5, r5, #0x2000                 @ Skip two pages
-       lsr     r5, r5, #12                     @ Align to start of page
+       @ Detect page border
+       lsl     r4, r5, #20

Why do you shift it 20 bits? I guess you wanted to shift 12 bits instead.

Quoted 14 lines

arch/arm/cpu/armv7/psci.S +10 -2

+       cmp     r4, #0
+       beq     out_psci_stack_align
+       add     r5, r5, #PSCI_STACK_ALIGN_SIZE
+       lsr     r5, r5, #12
         lsl     r5, r5, #12
-       sub     r5, r5, #4                      @ reserve 1 word for target PC
-       sub     r0, r5, r0                      @ here's our stack!
+
+out_psci_stack_align:
+       mov     r4, #PSCI_PERCPU_STACK_SIZE
+       add     r0, r0, #1
+       mul     r0, r0, r4
+       add     r0, r0, r5
 

arch/arm/cpu/armv7/psci.S ENDPROC(psci_cpu_off_common) · line 223

Quoted 6 lines

arch/arm/cpu/armv7/psci.S +3 -0

         bx      lr
  ENDPROC(psci_get_cpu_stack_top)
 
+@ Save space in percpu stack tail.
+@ expects CPU ID in r0 and returns save space address in r0.
+ENTRY(psci_get_cpu_save_space)

It is better to use term "reserve" here instead of "save"

arch/arm/cpu/armv7/psci.S ENDPROC(psci_cpu_off_common) · line 227

Quoted 4 lines

arch/arm/cpu/armv7/psci.S +4 -0

+       mov     r10, lr
+
+       bl      psci_get_cpu_stack_top
+       sub     r0, r0, #PSCI_PERCPU_STACK_SIZE

(r0 - PSCI_PERCPU_STACK_SIZE ) is stack top of next CPU's stack. (r0 - PSCI_PERCPU_STACK_SIZE +1 ) is the stack tail you want, right?

From: Wang Dongsheng <[email protected]>

Add validation code to make sure target cpu ID is valid.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/ls102xa/psci.S +8 -3

index 461b785..3091362 100644
@@ -25,13 +25,34 @@
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+#define AFFINITY_LEVEL_PROCESSOR_SHIFT		8
 @ Expect target CPU in r1, return the target cpu number in R0
 .globl	psci_get_target_cpu_id
 psci_get_target_cpu_id:
-	@ Clear and Get the correct CPU number
-	and	r1, r1, #0xff
-	mov	r0, r1
+	@ Get the CPU number
+	and	r0, r1, #0xff
 
+	@ Verify bit[31:24], bits must be zero.
+	tst	r1, #0xff000000
+	bne	out_psci_get_target_cpu_id
+
+	@ Verify Affinity level 2: Cluster, only one cluster in LS1021xa

SoC.

arch/arm/cpu/armv7/ls102xa/psci.S +7 -0

+	tst	r1, #0xff0000
+	bne	out_psci_get_target_cpu_id
+
+	@ Verify Affinity level 1: Processors, should in 0xf00 processor.
+	lsr	r1, r1, #AFFINITY_LEVEL_PROCESSOR_SHIFT
+	teq	r1, #0xf
+	bne	out_psci_get_target_cpu_id

Quoted 46 lines

From: Wang Dongsheng <[email protected]>

Add validation code to make sure target cpu ID is valid.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/ls102xa/psci.S +8 -3

index 461b785..3091362 100644
@@ -25,13 +25,34 @@
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+#define AFFINITY_LEVEL_PROCESSOR_SHIFT		8
 @ Expect target CPU in r1, return the target cpu number in R0
 .globl	psci_get_target_cpu_id
 psci_get_target_cpu_id:
-	@ Clear and Get the correct CPU number
-	and	r1, r1, #0xff
-	mov	r0, r1
+	@ Get the CPU number
+	and	r0, r1, #0xff
 
+	@ Verify bit[31:24], bits must be zero.
+	tst	r1, #0xff000000
+	bne	out_psci_get_target_cpu_id
+
+	@ Verify Affinity level 2: Cluster, only one cluster in LS1021xa

SoC.

arch/arm/cpu/armv7/ls102xa/psci.S +12 -0

+	tst	r1, #0xff0000
+	bne	out_psci_get_target_cpu_id
+
+	@ Verify Affinity level 1: Processors, should in 0xf00 processor.
+	lsr	r1, r1, #AFFINITY_LEVEL_PROCESSOR_SHIFT
+	teq	r1, #0xf
+	bne	out_psci_get_target_cpu_id
+
+	@ Verify CPU, Affinity level 0: Only 0, 1 is effective value.
+	cmp	r0, #2
+	bge	out_psci_get_target_cpu_id
+

arch/arm/cpu/armv7/ls102xa/psci.S line 56

Quoted 5 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+	bx	lr
+
+out_psci_get_target_cpu_id:
+	mov	r0, #PSCI_RET_INVALID_PARAMS
 	bx	lr

Where do you check for ALREADY_ON or ON_PENDING?

arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 108

Quoted 8 lines

arch/arm/cpu/armv7/virt-dt.c +5 -1

+
+#ifdef CONFIG_ARMV7_PSCI_GTE_1_0
+	tmp = fdt_psci_gte_1_0_fixup(fdt, nodeoff);
 	if (tmp)
 		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", PSCI_FN_MIGRATE);
+#endif
+	tmp = fdt_psci_0_1_fixup(fdt, nodeoff);

The "gte" is needless verbosity and is inconsistent with "fdt_psci_0_1_fixup" which lacks it.

From: Wang Dongsheng <[email protected]>

Based on PSCI v1.0, implement interface for ls102xa SoC:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S          | 110
+++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 board/freescale/ls1021aqds/Makefile        |   1 +
 board/freescale/ls1021aqds/psci.S          |  36 ++++++++++
 board/freescale/ls1021atwr/Makefile        |   1 +
 board/freescale/ls1021atwr/psci.S          |  28 ++++++++
 include/configs/ls1021aqds.h               |   3 +
 include/configs/ls1021atwr.h               |   1 +
 8 files changed, 177 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

arch/arm/cpu/armv7/ls102xa/psci.S +30 -2

index 3091362..bfc908e 100644
@@ -12,19 +12,72 @@
 #include <asm/arch-armv7/generictimer.h>
 #include <asm/psci.h>
 
+#define RCPM_TWAITSR		0x04C
+
 #define SCFG_CORE0_SFT_RST      0x130
 #define SCFG_CORESRENCR         0x204
 
-#define DCFG_CCSR_BRR           0x0E4
-#define DCFG_CCSR_SCRATCHRW1    0x200
+#define DCFG_CCSR_RSTCR			0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ	0x2
+#define DCFG_CCSR_BRR			0x0E4
+#define DCFG_CCSR_SCRATCHRW1		0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK		0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
 	.arch_extension sec
 
+	.align	5
+
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+.globl	psci_version
+psci_version:
+	movw	r0, #0
+	movt	r0, #1
+
+	bx	lr
+
+_ls102x_psci_supported_table:
+	.word	PSCI_FN_PSCI_VERSION
+	.word	PSCI_FN_PSCI_VERSION_FEATURE_MASK
+	.word	PSCI_FN_CPU_SUSPEND
+	.word	PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+	.word	PSCI_FN_CPU_OFF
+	.word	PSCI_FN_CPU_OFF_FEATURE_MASK

arch/arm/cpu/armv7/ls102xa/psci.S +28 -0

+
 #define AFFINITY_LEVEL_PROCESSOR_SHIFT		8
 @ Expect target CPU in r1, return the target cpu number in R0
 .globl	psci_get_target_cpu_id

@@ -128,6 +181,57 @@ psci_cpu_off:
 1:	wfi
 	b	1b
 
+.globl	psci_cpu_suspend
+psci_cpu_suspend:
+	mov	r0, #PSCI_RET_INVALID_PARAMS
+	bx	lr
+
+.globl	psci_affinity_info
+psci_affinity_info:
+	push	{lr}
+
+	mov	r0, #PSCI_RET_INVALID_PARAMS
+
+	@ Verify Affinity level
+	cmp	r2, #0
+	bne	out_affinity_info
+
+	bl	psci_get_target_cpu_id
+	cmp	r0, #PSCI_RET_INVALID_PARAMS
+	beq	out_affinity_info
+	mov	r1, r0
+
+	@ Get RCPM base address
+	movw	r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
+	movt	r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+	mov	r0, #PSCI_AFFINITY_LEVEL_ON
+
+	@ Detect target CPU state

Quoted 82 lines

From: Wang Dongsheng <[email protected]>

Based on PSCI v1.0, implement interface for ls102xa SoC:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S          | 110
+++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 board/freescale/ls1021aqds/Makefile        |   1 +
 board/freescale/ls1021aqds/psci.S          |  36 ++++++++++
 board/freescale/ls1021atwr/Makefile        |   1 +
 board/freescale/ls1021atwr/psci.S          |  28 ++++++++
 include/configs/ls1021aqds.h               |   3 +
 include/configs/ls1021atwr.h               |   1 +
 8 files changed, 177 insertions(+), 4 deletions(-)  create mode

100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S

arch/arm/cpu/armv7/ls102xa/psci.S +34 -2

index 3091362..bfc908e 100644
@@ -12,19 +12,72 @@
 #include <asm/arch-armv7/generictimer.h>  #include <asm/psci.h>
 
+#define RCPM_TWAITSR		0x04C
+
 #define SCFG_CORE0_SFT_RST      0x130
 #define SCFG_CORESRENCR         0x204
 
-#define DCFG_CCSR_BRR           0x0E4
-#define DCFG_CCSR_SCRATCHRW1    0x200
+#define DCFG_CCSR_RSTCR			0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ	0x2
+#define DCFG_CCSR_BRR			0x0E4
+#define DCFG_CCSR_SCRATCHRW1		0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK		0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
 	.arch_extension sec
 
+	.align	5
+
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+.globl	psci_version
+psci_version:
+	movw	r0, #0
+	movt	r0, #1
+
+	bx	lr
+
+_ls102x_psci_supported_table:
+	.word	PSCI_FN_PSCI_VERSION
+	.word	PSCI_FN_PSCI_VERSION_FEATURE_MASK
+	.word	PSCI_FN_CPU_SUSPEND
+	.word	PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+	.word	PSCI_FN_CPU_OFF
+	.word	PSCI_FN_CPU_OFF_FEATURE_MASK
+	.word	PSCI_FN_CPU_ON
+	.word	PSCI_FN_CPU_ON_FEATURE_MASK
+	.word	PSCI_FN_AFFINITY_INFO
+	.word	PSCI_FN_AFFINITY_INFO_FEATURE_MASK

arch/arm/cpu/armv7/ls102xa/psci.S line 65

Quoted 6 lines

arch/arm/cpu/armv7/ls102xa/psci.S +6 -0

+	.word	PSCI_FN_SYSTEM_OFF
+	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+	.word	PSCI_FN_SYSTEM_RESET
+	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+	.word	0
+	.word	PSCI_RET_NOT_SUPPORTED

Can you use the main _psci_table instead of duplicating it?

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+.globl	psci_features
+psci_features:
+	adr	r2, _ls102x_psci_supported_table

arch/arm/cpu/armv7/ls102xa/psci.S line 75

Quoted 6 lines

arch/arm/cpu/armv7/ls102xa/psci.S +6 -0

+1:	ldr	r3, [r2]
+	cmp	r3, #0
+	beq	out_psci_features
+	cmp	r1, r3
+	addne	r2, r2, #8
+	bne	1b

Why are you adding 8 here?

arch/arm/cpu/armv7/ls102xa/psci.S line 79

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+out_psci_features:
+	ldr	r0, [r2, #4]
+	bx	lr

If you find a match, you're supposed to return zero, not the next function id in the table.
How did you test this? There should really be a test suite for runtime services such as this, especially when trying to comply with a standard.

Quoted 41 lines

arch/arm/cpu/armv7/ls102xa/psci.S +32 -0

+
 #define AFFINITY_LEVEL_PROCESSOR_SHIFT		8
 @ Expect target CPU in r1, return the target cpu number in R0
 .globl	psci_get_target_cpu_id

@@ -128,6 +181,57 @@ psci_cpu_off:
 1:	wfi
 	b	1b
 
+.globl	psci_cpu_suspend
+psci_cpu_suspend:
+	mov	r0, #PSCI_RET_INVALID_PARAMS
+	bx	lr
+
+.globl	psci_affinity_info
+psci_affinity_info:
+	push	{lr}
+
+	mov	r0, #PSCI_RET_INVALID_PARAMS
+
+	@ Verify Affinity level
+	cmp	r2, #0
+	bne	out_affinity_info
+
+	bl	psci_get_target_cpu_id
+	cmp	r0, #PSCI_RET_INVALID_PARAMS
+	beq	out_affinity_info
+	mov	r1, r0
+
+	@ Get RCPM base address
+	movw	r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
+	movt	r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+	mov	r0, #PSCI_AFFINITY_LEVEL_ON
+
+	@ Detect target CPU state
+	ldr	r2, [r4, #RCPM_TWAITSR]
+	rev	r2, r2
+	lsr	r2, r2, r1
+	ands	r2, r2, #1

arch/arm/cpu/armv7/ls102xa/psci.S psci_cpu_off: · line 220

Quoted 6 lines

arch/arm/cpu/armv7/ls102xa/psci.S +6 -0

+	beq	out_affinity_info
+
+	mov	r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+	pop	{pc}

Where do you check for ON_PENDING?

Hi Scott,

Quoted 83 lines · Dongsheng Wang

Quoted 82 lines

From: Wang Dongsheng <[email protected]>

Based on PSCI v1.0, implement interface for ls102xa SoC:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S          | 110
+++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 board/freescale/ls1021aqds/Makefile        |   1 +
 board/freescale/ls1021aqds/psci.S          |  36 ++++++++++
 board/freescale/ls1021atwr/Makefile        |   1 +
 board/freescale/ls1021atwr/psci.S          |  28 ++++++++
 include/configs/ls1021aqds.h               |   3 +
 include/configs/ls1021atwr.h               |   1 +
 8 files changed, 177 insertions(+), 4 deletions(-)  create mode

100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S

arch/arm/cpu/armv7/ls102xa/psci.S +34 -2

index 3091362..bfc908e 100644
@@ -12,19 +12,72 @@
 #include <asm/arch-armv7/generictimer.h>  #include <asm/psci.h>
 
+#define RCPM_TWAITSR		0x04C
+
 #define SCFG_CORE0_SFT_RST      0x130
 #define SCFG_CORESRENCR         0x204
 
-#define DCFG_CCSR_BRR           0x0E4
-#define DCFG_CCSR_SCRATCHRW1    0x200
+#define DCFG_CCSR_RSTCR			0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ	0x2
+#define DCFG_CCSR_BRR			0x0E4
+#define DCFG_CCSR_SCRATCHRW1		0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK		0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
 	.arch_extension sec
 
+	.align	5
+
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+.globl	psci_version
+psci_version:
+	movw	r0, #0
+	movt	r0, #1
+
+	bx	lr
+
+_ls102x_psci_supported_table:
+	.word	PSCI_FN_PSCI_VERSION
+	.word	PSCI_FN_PSCI_VERSION_FEATURE_MASK
+	.word	PSCI_FN_CPU_SUSPEND
+	.word	PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+	.word	PSCI_FN_CPU_OFF
+	.word	PSCI_FN_CPU_OFF_FEATURE_MASK
+	.word	PSCI_FN_CPU_ON
+	.word	PSCI_FN_CPU_ON_FEATURE_MASK
+	.word	PSCI_FN_AFFINITY_INFO
+	.word	PSCI_FN_AFFINITY_INFO_FEATURE_MASK

Quoted 9 lines

arch/arm/cpu/armv7/ls102xa/psci.S line 65

Quoted 6 lines

arch/arm/cpu/armv7/ls102xa/psci.S +6 -0

+	.word	PSCI_FN_SYSTEM_OFF
+	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+	.word	PSCI_FN_SYSTEM_RESET
+	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+	.word	0
+	.word	PSCI_RET_NOT_SUPPORTED

Can you use the main _psci_table instead of duplicating it?

The main table does not apply here. Because this table shows what is supported in our platform.

And this table also contains the sub-feature mask of PSCI functions.

Quoted 4 lines

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+.globl	psci_features
+psci_features:
+	adr	r2, _ls102x_psci_supported_table

Quoted 9 lines

arch/arm/cpu/armv7/ls102xa/psci.S line 75

Quoted 6 lines

arch/arm/cpu/armv7/ls102xa/psci.S +6 -0

+1:	ldr	r3, [r2]
+	cmp	r3, #0
+	beq	out_psci_features
+	cmp	r1, r3
+	addne	r2, r2, #8
+	bne	1b

Why are you adding 8 here?

+4 is the sub-feature mask of the PSCI function. So we need to +8 to jump to next PSCI function.
.word PSCI_FN_PSCI_VERSION
.word PSCI_FN_PSCI_VERSION_FEATURE_MASK

Quoted 11 lines

arch/arm/cpu/armv7/ls102xa/psci.S line 79

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+out_psci_features:
+	ldr	r0, [r2, #4]
+	bx	lr

If you find a match, you're supposed to return zero, not the next function id in
the table.
How did you test this? There should really be a test suite for runtime services
such as this, especially when trying to comply with a standard.

I think maybe you missed something about this code. The return value is PSCI_FN_PSCI_XXXXXX_FEATURE_MASK,
not return next function ID.

Quoted 95 lines

Hi Scott,

Quoted 92 lines · Dongsheng Wang

Quoted 78 lines

From: Wang Dongsheng <[email protected]>

Based on PSCI v1.0, implement interface for ls102xa SoC:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S          | 110
+++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 board/freescale/ls1021aqds/Makefile        |   1 +
 board/freescale/ls1021aqds/psci.S          |  36 ++++++++++
 board/freescale/ls1021atwr/Makefile        |   1 +
 board/freescale/ls1021atwr/psci.S          |  28 ++++++++
 include/configs/ls1021aqds.h               |   3 +
 include/configs/ls1021atwr.h               |   1 +
 8 files changed, 177 insertions(+), 4 deletions(-)  create mode

100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S

arch/arm/cpu/armv7/ls102xa/psci.S +30 -2

index 3091362..bfc908e 100644
@@ -12,19 +12,72 @@
 #include <asm/arch-armv7/generictimer.h>  #include <asm/psci.h>
 
+#define RCPM_TWAITSR		0x04C
+
 #define SCFG_CORE0_SFT_RST      0x130
 #define SCFG_CORESRENCR         0x204
 
-#define DCFG_CCSR_BRR           0x0E4
-#define DCFG_CCSR_SCRATCHRW1    0x200
+#define DCFG_CCSR_RSTCR			0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ	0x2
+#define DCFG_CCSR_BRR			0x0E4
+#define DCFG_CCSR_SCRATCHRW1		0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK		0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
 	.arch_extension sec
 
+	.align	5
+
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+.globl	psci_version
+psci_version:
+	movw	r0, #0
+	movt	r0, #1
+
+	bx	lr
+
+_ls102x_psci_supported_table:
+	.word	PSCI_FN_PSCI_VERSION
+	.word	PSCI_FN_PSCI_VERSION_FEATURE_MASK
+	.word	PSCI_FN_CPU_SUSPEND
+	.word	PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+	.word	PSCI_FN_CPU_OFF
+	.word	PSCI_FN_CPU_OFF_FEATURE_MASK

arch/arm/cpu/armv7/ls102xa/psci.S line 64

Quoted 10 lines

arch/arm/cpu/armv7/ls102xa/psci.S +10 -0

+	.word	PSCI_FN_CPU_ON
+	.word	PSCI_FN_CPU_ON_FEATURE_MASK
+	.word	PSCI_FN_AFFINITY_INFO
+	.word	PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+	.word	PSCI_FN_SYSTEM_OFF
+	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+	.word	PSCI_FN_SYSTEM_RESET
+	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+	.word	0
+	.word	PSCI_RET_NOT_SUPPORTED

Can you use the main _psci_table instead of duplicating it?

Quoted 2 lines

The main table does not apply here. Because this table shows what is supported in our platform.

How does that set differ from what's in the main table?

Quoted 1 line

And this table also contains the sub-feature mask of PSCI functions.

...which is always zero. As of PSCI 1.0 there's only one function that supports subfeatures, and you could put an explicit check in for that if it ever needs a non-zero value.

Quoted 31 lines

Quoted 4 lines

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+.globl	psci_features
+psci_features:
+	adr	r2, _ls102x_psci_supported_table

Quoted 9 lines

arch/arm/cpu/armv7/ls102xa/psci.S line 75

Quoted 6 lines

arch/arm/cpu/armv7/ls102xa/psci.S +6 -0

+1:	ldr	r3, [r2]
+	cmp	r3, #0
+	beq	out_psci_features
+	cmp	r1, r3
+	addne	r2, r2, #8
+	bne	1b

Why are you adding 8 here?

+4 is the sub-feature mask of the PSCI function. So we need to +8 to +jump to
next PSCI function.
.word PSCI_FN_PSCI_VERSION
.word PSCI_FN_PSCI_VERSION_FEATURE_MASK

Quoted 10 lines

arch/arm/cpu/armv7/ls102xa/psci.S line 79

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+out_psci_features:
+	ldr	r0, [r2, #4]
+	bx	lr

If you find a match, you're supposed to return zero, not the next function id in the table.
How did you test this? There should really be a test suite for runtime services such as this, especially when trying to comply with a standard.

Quoted 2 lines

I think maybe you missed something about this code. The return value is PSCI_FN_PSCI_XXXXXX_FEATURE_MASK, not return next function ID.

Yes, I misread the table and missed the masks. But see above about them being unnecessary.

In any case, a test suite would be very helpful.

Hi Scott,

Thanks for your review.

Quoted 96 lines · Dongsheng Wang

Quoted 95 lines

Hi Scott,

Quoted 92 lines · Dongsheng Wang

Quoted 78 lines

From: Wang Dongsheng <[email protected]>

Based on PSCI v1.0, implement interface for ls102xa SoC:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by Wang Dongsheng <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/psci.S          | 110
+++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 board/freescale/ls1021aqds/Makefile        |   1 +
 board/freescale/ls1021aqds/psci.S          |  36 ++++++++++
 board/freescale/ls1021atwr/Makefile        |   1 +
 board/freescale/ls1021atwr/psci.S          |  28 ++++++++
 include/configs/ls1021aqds.h               |   3 +
 include/configs/ls1021atwr.h               |   1 +
 8 files changed, 177 insertions(+), 4 deletions(-)  create mode

100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S

arch/arm/cpu/armv7/ls102xa/psci.S +30 -2

index 3091362..bfc908e 100644
@@ -12,19 +12,72 @@
 #include <asm/arch-armv7/generictimer.h>  #include <asm/psci.h>
 
+#define RCPM_TWAITSR		0x04C
+
 #define SCFG_CORE0_SFT_RST      0x130
 #define SCFG_CORESRENCR         0x204
 
-#define DCFG_CCSR_BRR           0x0E4
-#define DCFG_CCSR_SCRATCHRW1    0x200
+#define DCFG_CCSR_RSTCR			0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ	0x2
+#define DCFG_CCSR_BRR			0x0E4
+#define DCFG_CCSR_SCRATCHRW1		0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK		0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
 	.arch_extension sec
 
+	.align	5
+
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+.globl	psci_version
+psci_version:
+	movw	r0, #0
+	movt	r0, #1
+
+	bx	lr
+
+_ls102x_psci_supported_table:
+	.word	PSCI_FN_PSCI_VERSION
+	.word	PSCI_FN_PSCI_VERSION_FEATURE_MASK
+	.word	PSCI_FN_CPU_SUSPEND
+	.word	PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+	.word	PSCI_FN_CPU_OFF
+	.word	PSCI_FN_CPU_OFF_FEATURE_MASK

arch/arm/cpu/armv7/ls102xa/psci.S line 64

Quoted 10 lines

arch/arm/cpu/armv7/ls102xa/psci.S +10 -0

+	.word	PSCI_FN_CPU_ON
+	.word	PSCI_FN_CPU_ON_FEATURE_MASK
+	.word	PSCI_FN_AFFINITY_INFO
+	.word	PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+	.word	PSCI_FN_SYSTEM_OFF
+	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+	.word	PSCI_FN_SYSTEM_RESET
+	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+	.word	0
+	.word	PSCI_RET_NOT_SUPPORTED

Can you use the main _psci_table instead of duplicating it?

Quoted 5 lines

Quoted 2 lines

The main table does not apply here. Because this table shows what is supported in our platform.

How does that set differ from what's in the main table?

The main table include all of functions about PSCI spec. If we use main table to match the pass in parameter, it will always return SUPPORT.

This table just we supported table, if the parameter not matched in this table it will finally return NOT_SUPPORTED.

The main table include in functions ID and function handle, not match this feature return value, we not need to get the functions handler, just need to return sub-feature, and this table will return sub-feature if the PSCI ID be matched.

Quoted 6 lines

Quoted 1 line

And this table also contains the sub-feature mask of PSCI functions.

...which is always zero. As of PSCI 1.0 there's only one function that supports subfeatures, and you could put an explicit check in for that if it ever needs a non-zero value.

Yes, for now there is only one function that supports sub-features. But this table is easy to extend, even if PSCI defines some other sub-features we just need to take care this table, and not need to modify the code logic. :)

Quoted 31 lines

Quoted 31 lines

Quoted 4 lines

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+.globl	psci_features
+psci_features:
+	adr	r2, _ls102x_psci_supported_table

Quoted 9 lines

arch/arm/cpu/armv7/ls102xa/psci.S line 75

Quoted 6 lines

arch/arm/cpu/armv7/ls102xa/psci.S +6 -0

+1:	ldr	r3, [r2]
+	cmp	r3, #0
+	beq	out_psci_features
+	cmp	r1, r3
+	addne	r2, r2, #8
+	bne	1b

Why are you adding 8 here?

+4 is the sub-feature mask of the PSCI function. So we need to +8 to +jump to
next PSCI function.
.word PSCI_FN_PSCI_VERSION
.word PSCI_FN_PSCI_VERSION_FEATURE_MASK

Quoted 10 lines

arch/arm/cpu/armv7/ls102xa/psci.S line 79

Quoted 4 lines

arch/arm/cpu/armv7/ls102xa/psci.S +4 -0

+
+out_psci_features:
+	ldr	r0, [r2, #4]
+	bx	lr

If you find a match, you're supposed to return zero, not the next function id in the table.
How did you test this? There should really be a test suite for runtime services such as this, especially when trying to comply with a standard.

Quoted 8 lines

Quoted 2 lines

I think maybe you missed something about this code. The return value is PSCI_FN_PSCI_XXXXXX_FEATURE_MASK, not return next function ID.

Yes, I misread the table and missed the masks. But see above about them being unnecessary.

In any case, a test suite would be very helpful.

Yes, thanks for your friendly reminder. And this table has tested on ls1021 platform. :)

Regards,
-Dongsheng

From: Wang Dongsheng <[email protected]>

Support PSCI v1.0 for u-boot.

Wang Dongsheng (9):
ARM: PSCI: Change function ID base value
ARM: PSCI: Change PSCI related macro definition style
ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared
ARM: ARMv7: PSCI: Factor out reusable psci_cpu_on_common
ARM: ARMv7: PSCI: Pass contextID to target CPU
ARM: ARMv7: PSCI: ls102xa: Verify CPU ID for CPU_ON
ARM: ARMv7: PSCI: Add PSCI 1.0 version support
ARM: ARMv7: PSCI: ls102xa: add psci functions implemention
ARM: ARMv7: PSCI: ls102xa: put secure text section into OCRAM

 arch/arm/cpu/armv7/ls102xa/psci.S          | 155 +++++++++++++++++++++++--
--
 arch/arm/cpu/armv7/mx7/psci.S              |   5 -
 arch/arm/cpu/armv7/nonsec_virt.S           |   4 +
 arch/arm/cpu/armv7/psci.S                  | 162 ++++++++++++++++++++++++++---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S      |  11 +-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S      |  11 +-
 arch/arm/cpu/armv7/virt-dt.c               |  48 ++++++---
 arch/arm/include/asm/arch-ls102xa/config.h |   3 +-
 arch/arm/include/asm/psci.h                |  62 ++++++++---
 arch/arm/mach-tegra/psci.S                 |  11 +-
 board/freescale/ls1021aqds/Makefile        |   1 +
 board/freescale/ls1021aqds/psci.S          |  36 +++++++
 board/freescale/ls1021atwr/Makefile        |   1 +
 board/freescale/ls1021atwr/psci.S          |  28 +++++
 include/configs/ls1021aqds.h               |   3 +
 include/configs/ls1021atwr.h               |   2 +
 16 files changed, 451 insertions(+), 92 deletions(-)  create mode 100644

board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S

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2.1.0.27.g96db324