Skip to contentSkip to conversation

irqchip/gic: Only populate set_affinity for the root controller

PATCH In review Jon Hunter 2 participants 4 messages Feb 9, 2016 – Feb 11, 2016

Subsystems (2)
irqchip drivers Arm generic interrupt controller drivers
lore
Share & tools
lore

Jon Hunter

author
#0 lore raw

PATCH 1/2 irqchip/gic: Only populate set_affinity for the root controller

Setting the affinity of an IRQ, it only applicable for the root interrupt controller and so only populate this operator for the root controller.

Signed-off-by Jon Hunter <[email protected]>
---
 drivers/irqchip/irq-gic.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)
drivers/irqchip/irq-gic.c +5 -6
index 911758c056c1..db7b161b0295 100644
@@ -384,9 +384,6 @@ static struct irq_chip gic_chip = {
 	.irq_unmask		= gic_unmask_irq,
 	.irq_eoi		= gic_eoi_irq,
 	.irq_set_type		= gic_set_type,
-#ifdef CONFIG_SMP
-	.irq_set_affinity	= gic_set_affinity,
-#endif
 	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,
 	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,
 	.flags			= IRQCHIP_SET_TYPE_MASKED |

@@ -400,9 +397,6 @@ static struct irq_chip gic_eoimode1_chip = {
 	.irq_unmask		= gic_unmask_irq,
 	.irq_eoi		= gic_eoimode1_eoi_irq,
 	.irq_set_type		= gic_set_type,
-#ifdef CONFIG_SMP
-	.irq_set_affinity	= gic_set_affinity,
-#endif
 	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,
 	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,
 	.irq_set_vcpu_affinity	= gic_irq_set_vcpu_affinity,

@@ -1039,6 +1033,11 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 		gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
 	}
 
+#ifdef CONFIG_SMP
+	if (gic_nr == 0)
+		gic->chip.irq_set_affinity = gic_set_affinity;
+#endif
+
 #ifdef CONFIG_GIC_NON_BANKED
 	if (percpu_offset) { /* Frankein-GIC without banked registers... */
 		unsigned int cpu;
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH 2/2 irqchip/gic: Only set the EOImodeNS bit for the root controller

EOImode1 is only used for the root controller and hence only the root controller uses the eoimode1 functions for handling interrupts. However, if the root controller supports EOImode1, then the EOImodeNS bit will be set for all GICs, enabling EOImode1. This is not what we want and this causes interrupts on non-root GICs to only be dropped in priority but never deactivated. Therefore, only set the EOImodeNS bit for the root controller.

Signed-off-by Jon Hunter <[email protected]>
---
 drivers/irqchip/irq-gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/irqchip/irq-gic.c +1 -1
index db7b161b0295..8f9ebf714e2b 100644
@@ -437,7 +437,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
 	u32 bypass = 0;
 	u32 mode = 0;
 
-	if (static_key_true(&supports_deactivate))
+	if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
 		mode = GIC_CPU_CTRL_EOImodeNS;
 
 	/*
Signature · 1 line
2.1.4
Acked-by on v1 2/2
#2 lore raw

Re: [PATCH 2/2] irqchip/gic: Only set the EOImodeNS bit for the root controller

Quoted 9 lines · Jon Hunter

EOImode1 is only used for the root controller and hence only the root controller uses the eoimode1 functions for handling interrupts. However, if the root controller supports EOImode1, then the EOImodeNS bit will be set for all GICs, enabling EOImode1. This is not what we want and this causes interrupts on non-root GICs to only be dropped in priority but never deactivated. Therefore, only set the EOImodeNS bit for the root controller.

Signed-off-by Jon Hunter <[email protected]>
Acked-by Marc Zyngier <[email protected]>
	M.
Signature · 1 line
Jazz is not dead. It just smells funny...