drm/msm/hdmi: HDMI support on MSM8996
Subsystems (5)
v2 cover drm/msm/hdmi: HDMI support on MSM8996
HDMI on MSM8996 has a TX block that is compatible with the older versions apart from some minor changes. The HDMI PHY and PLL on MSM8996 are new.
The series refactors the code such that there is a separate HDMI PHY driver, similar to what we already have for DSI. This makes it easier to integrate new PHYs like the one in msm8996.
Changes in v2:
- Fix copy/paste error in dt-binding patch.
- Update commit messages to point out that HDMI functionality will break if we pull in the commits that adds the PHY driver, but not the commit that updates PHY/PLL register offsets.
- Change the order of patches such that bisectability issues are reduced to a minimum.
Archit Taneja (13):
drm/msm/dsi: Create separate Makefile/Kconfig drm/msm/hdmi: Create separate Makefile/Kconfig drm/msm/edp: Create separate Makefile/Kconfig drm/msm/hdmi: Clean up connector gpio usage drm/msm/hdmi: Fix connector detect when there is no HPD gpio drm/msm/hdmi: Create a separate HDMI PHY driver drm/msm/hdmi: Manage HDMI PLL through PHY driver drm/msm/hdmi: Make HDMI core get its PHY drm/msm/hdmi: Convert PHY files according to new design drm/msm/hdmi: Update generated headers to split PHY/PLL offsets drm/msm/hdmi: Update generated headers for HDMI 8996 PHY drm/msm/hdmi: HDMI 8996 PHY/PLL support
dt-bindings: msm/hdmi: Add HDMI PHY bindings
.../devicetree/bindings/display/msm/hdmi.txt | 39 +- drivers/gpu/drm/msm/Kconfig | 42 +- drivers/gpu/drm/msm/Makefile | 39 +- drivers/gpu/drm/msm/dsi/Kconfig | 40 ++ drivers/gpu/drm/msm/dsi/Makefile | 13 + drivers/gpu/drm/msm/edp/Kconfig | 7 + drivers/gpu/drm/msm/edp/Makefile | 3 + drivers/gpu/drm/msm/hdmi/Kconfig | 7 + drivers/gpu/drm/msm/hdmi/Makefile | 6 + drivers/gpu/drm/msm/hdmi/hdmi.c | 98 ++- drivers/gpu/drm/msm/hdmi/hdmi.h | 78 ++- drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 657 +++++++++++++++--- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 8 +- drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 138 ++-- drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 228 ++++++ drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 503 +------------- drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 766 +++++++++++++++++++++ drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 196 ++---- drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c | 94 +-- drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c | 461 +++++++++++++ drivers/gpu/drm/msm/msm_drv.h | 33 + 21 files changed, 2495 insertions(+), 961 deletions(-) create mode 100644 drivers/gpu/drm/msm/dsi/Kconfig create mode 100644 drivers/gpu/drm/msm/dsi/Makefile create mode 100644 drivers/gpu/drm/msm/edp/Kconfig create mode 100644 drivers/gpu/drm/msm/edp/Makefile create mode 100644 drivers/gpu/drm/msm/hdmi/Kconfig create mode 100644 drivers/gpu/drm/msm/hdmi/Makefile create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy.c create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH v2 1/13 drm/msm/dsi: Create separate Makefile/Kconfig
The msm Makefile and Kconfig are getting conjusted. Move out the DSI related stuff into separate Kconfig and Makefile.
--- drivers/gpu/drm/msm/Kconfig | 40 +--------------------------------------- drivers/gpu/drm/msm/Makefile | 22 ++++------------------ drivers/gpu/drm/msm/dsi/Kconfig | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/Makefile | 13 +++++++++++++ 4 files changed, 58 insertions(+), 57 deletions(-) create mode 100644 drivers/gpu/drm/msm/dsi/Kconfig create mode 100644 drivers/gpu/drm/msm/dsi/Makefile
drivers/gpu/drm/msm/Kconfig +1 -39
@@ -24,42 +24,4 @@ config DRM_MSM_REGISTER_LOGGING that can be parsed by envytools demsm tool. If enabled, register logging can be switched on via msm.reglog=y module param. -config DRM_MSM_DSI - bool "Enable DSI support in MSM DRM driver" - depends on DRM_MSM - select DRM_PANEL - select DRM_MIPI_DSI - default y - help - Choose this option if you have a need for MIPI DSI connector - support. - -config DRM_MSM_DSI_PLL - bool "Enable DSI PLL driver in MSM DRM" - depends on DRM_MSM_DSI && COMMON_CLK - default y - help - Choose this option to enable DSI PLL driver which provides DSI - source clocks under common clock framework. - -config DRM_MSM_DSI_28NM_PHY - bool "Enable DSI 28nm PHY driver in MSM DRM" - depends on DRM_MSM_DSI - default y - help - Choose this option if the 28nm DSI PHY is used on the platform. - -config DRM_MSM_DSI_20NM_PHY - bool "Enable DSI 20nm PHY driver in MSM DRM" - depends on DRM_MSM_DSI - default y - help - Choose this option if the 20nm DSI PHY is used on the platform. - -config DRM_MSM_DSI_28NM_8960_PHY - bool "Enable DSI 28nm 8960 PHY driver in MSM DRM" - depends on DRM_MSM_DSI - default y - help - Choose this option if the 28nm DSI PHY 8960 variant is used on the - platform. +source "drivers/gpu/drm/msm/dsi/Kconfig"
drivers/gpu/drm/msm/Makefile +4 -18
@@ -1,5 +1,4 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm -ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi msm-y := \ adreno/adreno_device.o \
@@ -50,25 +49,12 @@ msm-y := \ msm_rd.o \ msm_ringbuffer.o +msm-$(CONFIG_DRM_MSM_DSI) += mdp/mdp4/mdp4_dsi_encoder.o \ + mdp/mdp5/mdp5_cmd_encoder.o + msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o -msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ - mdp/mdp4/mdp4_dsi_encoder.o \ - dsi/dsi_cfg.o \ - dsi/dsi_host.o \ - dsi/dsi_manager.o \ - dsi/phy/dsi_phy.o \ - mdp/mdp5/mdp5_cmd_encoder.o - -msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o -msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o -msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o - -ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y) -msm-y += dsi/pll/dsi_pll.o -msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o -msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o -endif +obj-$(CONFIG_DRM_MSM_DSI) += dsi/ obj-$(CONFIG_DRM_MSM) += msm.o
drivers/gpu/drm/msm/dsi/Kconfig new file +40 -0
@@ -0,0 +1,40 @@ +config DRM_MSM_DSI + bool "Enable DSI support in MSM DRM driver" + depends on DRM_MSM + select DRM_PANEL + select DRM_MIPI_DSI + default y + help + Choose this option if you have a need for MIPI DSI connector + support. + +if DRM_MSM_DSI + +config DRM_MSM_DSI_PLL + bool "Enable DSI PLL driver in MSM DRM" + default y + help + Choose this option to enable DSI PLL driver which provides DSI + source clocks under common clock framework. + +config DRM_MSM_DSI_28NM_PHY + bool "Enable DSI 28nm PHY driver in MSM DRM" + default y + help + Choose this option if the 28nm DSI PHY is used on the platform. + +config DRM_MSM_DSI_20NM_PHY + bool "Enable DSI 20nm PHY driver in MSM DRM" + default y + help + Choose this option if the 20nm DSI PHY is used on the platform. + +config DRM_MSM_DSI_28NM_8960_PHY + bool "Enable DSI 28nm 8960 PHY driver in MSM DRM" + depends on DRM_MSM_DSI + default y + help + Choose this option if the 28nm DSI PHY 8960 variant is used on the + platform. + +endif
drivers/gpu/drm/msm/dsi/Makefile new file +13 -0
@@ -0,0 +1,13 @@ +ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm -Idrivers/gpu/drm/msm/dsi + +obj-y := dsi.o dsi_cfg.o dsi_host.o dsi_manager.o phy/dsi_phy.o + +obj-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += phy/dsi_phy_28nm.o +obj-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += phy/dsi_phy_20nm.o +obj-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += phy/dsi_phy_28nm_8960.o + +ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y) +obj-y += pll/dsi_pll.o +obj-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += pll/dsi_pll_28nm.o +obj-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += pll/dsi_pll_28nm_8960.o +endif
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v2 2/13 drm/msm/hdmi: Create separate Makefile/Kconfig
In reply to Archit TanejaThe msm Makefile and Kconfig are getting conjusted. HDMI is going to have more configs and files in the future to manage, which will make managing these harder.
Move HDMI related stuff into separate Kconfig and Makefile.
--- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/Makefile | 10 +--------- drivers/gpu/drm/msm/hdmi/Kconfig | 7 +++++++ drivers/gpu/drm/msm/hdmi/Makefile | 4 ++++ drivers/gpu/drm/msm/msm_drv.h | 16 ++++++++++++++++ 5 files changed, 29 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/msm/hdmi/Kconfig create mode 100644 drivers/gpu/drm/msm/hdmi/Makefile
drivers/gpu/drm/msm/Kconfig +1 -0
@@ -25,3 +25,4 @@ config DRM_MSM_REGISTER_LOGGING logging can be switched on via msm.reglog=y module param. source "drivers/gpu/drm/msm/dsi/Kconfig" +source "drivers/gpu/drm/msm/hdmi/Kconfig"
drivers/gpu/drm/msm/Makefile +1 -9
@@ -5,15 +5,6 @@ msm-y := \ adreno/adreno_gpu.o \ adreno/a3xx_gpu.o \ adreno/a4xx_gpu.o \ - hdmi/hdmi.o \ - hdmi/hdmi_audio.o \ - hdmi/hdmi_bridge.o \ - hdmi/hdmi_connector.o \ - hdmi/hdmi_hdcp.o \ - hdmi/hdmi_i2c.o \ - hdmi/hdmi_phy_8960.o \ - hdmi/hdmi_phy_8x60.o \ - hdmi/hdmi_phy_8x74.o \ edp/edp.o \ edp/edp_aux.o \ edp/edp_bridge.o \
@@ -56,5 +47,6 @@ msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o obj-$(CONFIG_DRM_MSM_DSI) += dsi/ +obj-$(CONFIG_DRM_MSM_HDMI) += hdmi/ obj-$(CONFIG_DRM_MSM) += msm.o
drivers/gpu/drm/msm/hdmi/Kconfig new file +7 -0
@@ -0,0 +1,7 @@ +config DRM_MSM_HDMI + bool "Enable HDMI support in MSM DRM driver" + depends on DRM_MSM + default y + help + Choose this option if you have a need for HDMI connector + support.
drivers/gpu/drm/msm/hdmi/Makefile new file +4 -0
@@ -0,0 +1,4 @@ +ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm + +obj-y := hdmi.o hdmi_audio.o hdmi_bridge.o hdmi_connector.o hdmi_hdcp.o \ + hdmi_i2c.o hdmi_phy_8960.o hdmi_phy_8x60.o hdmi_phy_8x74.o
drivers/gpu/drm/msm/msm_drv.h +16 -0
@@ -242,10 +242,26 @@ struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,struct drm_fb_helper *msm_fbdev_init (struct drm_device *dev);struct hdmi ; +#ifdef CONFIG_DRM_MSM_HDMI int hdmi_modeset_init (struct hdmi *hdmi,struct drm_device *dev,struct drm_encoder *encoder);void __init hdmi_register (void ); void __exit hdmi_unregister(void); +#else +static inline int hdmi_modeset_init (struct hdmi *hdmi,struct drm_device *dev, +struct drm_encoder *encoder) +{ +return -EINVAL ; +} + +static inline void __init hdmi_register (void ) +{ +} + +static inline void __exit hdmi_unregister(void) +{ +} +#endif struct msm_edp ;void __init msm_edp_register (void );
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH v2 3/13 drm/msm/edp: Create separate Makefile/Kconfig
In reply to Archit TanejaThe msm Makefile and Kconfig are getting conjusted. Move EDP related stuff into separate Kconfig and Makefile.
--- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/Makefile | 7 +------ drivers/gpu/drm/msm/edp/Kconfig | 7 +++++++ drivers/gpu/drm/msm/edp/Makefile | 3 +++ drivers/gpu/drm/msm/msm_drv.h | 17 +++++++++++++++++ 5 files changed, 29 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/msm/edp/Kconfig create mode 100644 drivers/gpu/drm/msm/edp/Makefile
drivers/gpu/drm/msm/Kconfig +1 -0
@@ -26,3 +26,4 @@ config DRM_MSM_REGISTER_LOGGING source "drivers/gpu/drm/msm/dsi/Kconfig" source "drivers/gpu/drm/msm/hdmi/Kconfig" +source "drivers/gpu/drm/msm/edp/Kconfig"
drivers/gpu/drm/msm/Makefile +1 -6
@@ -5,12 +5,6 @@ msm-y := \ adreno/adreno_gpu.o \ adreno/a3xx_gpu.o \ adreno/a4xx_gpu.o \ - edp/edp.o \ - edp/edp_aux.o \ - edp/edp_bridge.o \ - edp/edp_connector.o \ - edp/edp_ctrl.o \ - edp/edp_phy.o \ mdp/mdp_format.o \ mdp/mdp_kms.o \ mdp/mdp4/mdp4_crtc.o \
@@ -48,5 +42,6 @@ msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o obj-$(CONFIG_DRM_MSM_DSI) += dsi/ obj-$(CONFIG_DRM_MSM_HDMI) += hdmi/ +obj-$(CONFIG_DRM_MSM_EDP) += edp/ obj-$(CONFIG_DRM_MSM) += msm.o
drivers/gpu/drm/msm/edp/Kconfig new file +7 -0
@@ -0,0 +1,7 @@ +config DRM_MSM_EDP + bool "Enable EDP support in MSM DRM driver" + depends on DRM_MSM + default y + help + Choose this option if you have a need for Embedded Display + Port encoder support.
drivers/gpu/drm/msm/edp/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm + +obj-y := edp.o edp_aux.o edp_bridge.o edp_connector.o edp_ctrl.o edp_phy.o
drivers/gpu/drm/msm/msm_drv.h +17 -0
@@ -264,10 +264,27 @@ static inline void __exit hdmi_unregister(void)#endif struct msm_edp ; +#ifdef CONFIG_DRM_MSM_EDP void __init msm_edp_register (void ); void __exit msm_edp_unregister(void);int msm_edp_modeset_init (struct msm_edp *edp,struct drm_device *dev,struct drm_encoder *encoder); +#else +static inline void __init msm_edp_register (void ) +{ +} + +static inline void __exit msm_edp_unregister(void) +{ +} + +static inline int msm_edp_modeset_init (struct msm_edp *edp, +struct drm_device *dev, +struct drm_encoder *encoder) +{ +return -EINVAL ; +} +#endif struct msm_dsi ;enum msm_dsi_encoder_id {
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH v2 4/13 drm/msm/hdmi: Clean up connector gpio usage
In reply to Archit TanejaMake gpio allocation and usage iterative by parsing the gpios on a given platform from a list. This gives us flexibility over what all gpios exist for a platform, whether they are input or output, and what value they should be set to.
In particular, this will make HDMI on 8x96 platforms easier to integrate with the driver, as it doesn't have a HPD gpio input to them. Also, it cleans things up a bit.
We still use the legacy gpio api here, as we might need to backport this driver to downstream kernels.
--- drivers/gpu/drm/msm/hdmi/hdmi.c | 31 +++++-- drivers/gpu/drm/msm/hdmi/hdmi.h | 11 ++- drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 129 +++++++++--------------------- 3 files changed, 69 insertions(+), 102 deletions(-)
drivers/gpu/drm/msm/hdmi/hdmi.c +24 -7
@@ -390,7 +390,21 @@ static struct hdmi_platform_config hdmi_tx_8996_config = { .hpd_freq = hpd_clk_freq_8x74, }; -static int get_gpio (struct device *dev,struct device_node *of_node,const char *name) +static const struct { +const char *name; +const bool output; +const int value; +const char *label; +} hdmi_gpio_pdata[] = { + {"qcom,hdmi-tx-ddc-clk" , true,1 ,"HDMI_DDC_CLK" }, + {"qcom,hdmi-tx-ddc-data" , true,1 ,"HDMI_DDC_DATA" }, + {"qcom,hdmi-tx-hpd" , false,1 ,"HDMI_HPD" }, + {"qcom,hdmi-tx-mux-en" , true,1 ,"HDMI_MUX_EN" }, + {"qcom,hdmi-tx-mux-sel" , true,0 ,"HDMI_MUX_SEL" }, + {"qcom,hdmi-tx-mux-lpm" , true,1 ,"HDMI_MUX_LPM" }, +}; + +static int get_gpio (struct device_node *of_node,const char *name) {int gpio =of_get_named_gpio (of_node, name,0 );if (gpio <0 ) {
@@ -413,6 +427,7 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)static struct hdmi_platform_config *hdmi_cfg;struct hdmi *hdmi;struct device_node *of_node = dev->of_node; +int i; hdmi_cfg = (struct hdmi_platform_config *)of_device_get_match_data (dev);
@@ -423,12 +438,14 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data) hdmi_cfg->mmio_name ="core_physical" ; hdmi_cfg->qfprom_mmio_name ="qfprom_physical" ; - hdmi_cfg->ddc_clk_gpio =get_gpio (dev, of_node,"qcom,hdmi-tx-ddc-clk" ); - hdmi_cfg->ddc_data_gpio =get_gpio (dev, of_node,"qcom,hdmi-tx-ddc-data" ); - hdmi_cfg->hpd_gpio =get_gpio (dev, of_node,"qcom,hdmi-tx-hpd" ); - hdmi_cfg->mux_en_gpio =get_gpio (dev, of_node,"qcom,hdmi-tx-mux-en" ); - hdmi_cfg->mux_sel_gpio =get_gpio (dev, of_node,"qcom,hdmi-tx-mux-sel" ); - hdmi_cfg->mux_lpm_gpio =get_gpio (dev, of_node,"qcom,hdmi-tx-mux-lpm" ); + +for (i =0 ; i <HDMI_MAX_NUM_GPIO ; i++) { + hdmi_cfg->gpios[i].num =get_gpio (of_node, + hdmi_gpio_pdata[i].name); + hdmi_cfg->gpios[i].output = hdmi_gpio_pdata[i].output; + hdmi_cfg->gpios[i].value = hdmi_gpio_pdata[i].value; + hdmi_cfg->gpios[i].label = hdmi_gpio_pdata[i].label; + } dev->platform_data = hdmi_cfg;
drivers/gpu/drm/msm/hdmi/hdmi.h +9 -2
@@ -27,10 +27,18 @@#include "msm_drv.h" #include "hdmi.xml.h" +#define HDMI_MAX_NUM_GPIO 6struct hdmi_phy ;struct hdmi_platform_config ; +struct hdmi_gpio_data { +int num; +bool output; +int value; +const char *label; +}; +struct hdmi_audio {bool enabled;struct hdmi_audio_infoframe infoframe;
@@ -111,8 +119,7 @@ struct hdmi_platform_config {int pwr_clk_cnt;/* gpio's: */ -int ddc_clk_gpio, ddc_data_gpio, hpd_gpio, mux_en_gpio, mux_sel_gpio; -int mux_lpm_gpio; +struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO ]; };void hdmi_set_mode (struct hdmi *hdmi,bool power_on);
drivers/gpu/drm/msm/hdmi/hdmi_connector.c +36 -93
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Signature · 7 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v2 5/13 drm/msm/hdmi: Fix connector detect when there is no HPD gpio
In reply to Archit TanejaSome platforms may not have a HPD gpio line to detect Hot Plug signal from the connector. They need to rely only on reading REG_HDMI_HPD_INT_STATUS for HPD.
Modify hdmi_connector_detect logic such that it checks for HPD only using the status register if there is no HPD gpio.
--- drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/gpu/drm/msm/hdmi/hdmi_connector.c +9 -0
@@ -301,9 +301,18 @@ static enum drm_connector_status hdmi_connector_detect( {struct hdmi_connector *hdmi_connector =to_hdmi_connector (connector);struct hdmi *hdmi = hdmi_connector->hdmi; +const struct hdmi_platform_config *config = hdmi->config; +struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX ];enum drm_connector_status stat_gpio, stat_reg;int retry =20 ; +/* +* some platforms may not have hpd gpio. Rely only on the status +* provided by REG_HDMI_HPD_INT_STATUS in this case. +*/ +if (hpd_gpio.num ==-1 ) +return detect_reg (hdmi); + do { stat_gpio = detect_gpio(hdmi); stat_reg = detect_reg(hdmi);
Signature · 2 lines
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PATCH v2 6/13 drm/msm/hdmi: Create a separate HDMI PHY driver
In reply to Archit TanejaCreate a phy device that represents the TX PHY and PLL parts of the HDMI block.
This makes management of PHY specific resources (regulators and clocks) much easier, and makes the PHY and PLL usable independently. It also simplifies the core HDMI driver, which currently assigns phy ops among many other things.
The PHY driver implementation done here is very similar to the PHY driver we already have for DSI.
Keep the old hdmi_phy_funcs ops for now. The driver will use these until the HDMI PHY/PLL register offsets aren't considered as separate domains (i.e. their offsets start from 0).
--- drivers/gpu/drm/msm/hdmi/Makefile | 4 +- drivers/gpu/drm/msm/hdmi/hdmi.c | 2 + drivers/gpu/drm/msm/hdmi/hdmi.h | 48 +++++++- drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 188 +++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 18 +++ drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 6 + drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c | 20 ++++ 7 files changed, 280 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy.c
drivers/gpu/drm/msm/hdmi/Makefile +2 -2
@@ -1,4 +1,4 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm -obj-y := hdmi.o hdmi_audio.o hdmi_bridge.o hdmi_connector.o hdmi_hdcp.o \ - hdmi_i2c.o hdmi_phy_8960.o hdmi_phy_8x60.o hdmi_phy_8x74.o +obj-y := hdmi.o hdmi_phy.o hdmi_audio.o hdmi_bridge.o hdmi_connector.o \ + hdmi_hdcp.o hdmi_i2c.o hdmi_phy_8960.o hdmi_phy_8x60.o hdmi_phy_8x74.o
drivers/gpu/drm/msm/hdmi/hdmi.c +2 -0
@@ -626,10 +626,12 @@ static struct platform_driver hdmi_driver = {void __init hdmi_register (void ) { +hdmi_phy_driver_register ();platform_driver_register (&hdmi_driver); } void __exit hdmi_unregister(void) {platform_driver_unregister (&hdmi_driver); +hdmi_phy_driver_unregister (); }
drivers/gpu/drm/msm/hdmi/hdmi.h +44 -4
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drivers/gpu/drm/msm/hdmi/hdmi_phy.c new file +188 -0
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drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c +18 -0
@@ -464,6 +464,24 @@ static const struct hdmi_phy_funcs hdmi_phy_8960_funcs = { .powerdown = hdmi_phy_8960_powerdown, }; +static const char *const hdmi_phy_8960_reg_names[] = { +"core-vdda" , +}; + +static const char *const hdmi_phy_8960_clk_names[] = { +"slave_iface_clk" , +}; + +const struct hdmi_phy_cfg hdmi_phy_8960_cfg = { + .type =MSM_HDMI_PHY_8960 , + .powerup = hdmi_phy_8960_powerup, + .powerdown = hdmi_phy_8960_powerdown, + .reg_names = hdmi_phy_8960_reg_names, + .num_regs =ARRAY_SIZE (hdmi_phy_8960_reg_names), + .clk_names = hdmi_phy_8960_clk_names, + .num_clks =ARRAY_SIZE (hdmi_phy_8960_clk_names), +}; +struct hdmi_phy *hdmi_phy_8960_init (struct hdmi *hdmi) {struct hdmi_phy_8960 *phy_8960;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c +6 -0
@@ -155,6 +155,12 @@ static const struct hdmi_phy_funcs hdmi_phy_8x60_funcs = { .powerdown = hdmi_phy_8x60_powerdown, }; +const struct hdmi_phy_cfg hdmi_phy_8x60_cfg = { + .type = MSM_HDMI_PHY_8x60, + .powerup = hdmi_phy_8x60_powerup, + .powerdown = hdmi_phy_8x60_powerdown, +}; +struct hdmi_phy *hdmi_phy_8x60_init (struct hdmi *hdmi) {struct hdmi_phy_8x60 *phy_8x60;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c +20 -0
@@ -67,6 +67,26 @@ static const struct hdmi_phy_funcs hdmi_phy_8x74_funcs = { .powerdown = hdmi_phy_8x74_powerdown, }; +static const char *const hdmi_phy_8x74_reg_names[] = { +"core-vdda" , +"vddio" , +}; + +static const char *const hdmi_phy_8x74_clk_names[] = { +"iface_clk" , +"alt_iface_clk" +}; + +const struct hdmi_phy_cfg hdmi_phy_8x74_cfg = { + .type = MSM_HDMI_PHY_8x74, + .powerup = hdmi_phy_8x74_powerup, + .powerdown = hdmi_phy_8x74_powerdown, + .reg_names = hdmi_phy_8x74_reg_names, + .num_regs =ARRAY_SIZE (hdmi_phy_8x74_reg_names), + .clk_names = hdmi_phy_8x74_clk_names, + .num_clks =ARRAY_SIZE (hdmi_phy_8x74_clk_names), +}; +struct hdmi_phy *hdmi_phy_8x74_init (struct hdmi *hdmi) {struct hdmi_phy_8x74 *phy_8x74;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH v2 7/13 drm/msm/hdmi: Manage HDMI PLL through PHY driver
In reply to Archit TanejaAdd a helper to initialize PLL in the PHY driver. HDMI PLLs are going to have their own mmio base different from that of PHY.
For the clock code in hdmi_phy_8960.c, some changes were needed for it to work with the updated register offsets. Create a copy of the updated clock code in hdmi_pll_8960.c, instead of rewriting it in hdmi_phy_8960.c itself. This removes the need to place CONFIG_COMMON_CLOCK checks all around, makes the code more legible, and also removes some old checkpatch warnings with the original code.
The older hdmi pll clock ops in hdmi_phy_8960.c will be removed later. The driver will use these until the HDMI PHY/PLL register offsets aren't considered as separate domains (i.e. their offsets start from 0).
--- drivers/gpu/drm/msm/hdmi/Makefile | 2 + drivers/gpu/drm/msm/hdmi/hdmi.h | 9 + drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 35 +++ drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c | 461 +++++++++++++++++++++++++++++++ 4 files changed, 507 insertions(+) create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
drivers/gpu/drm/msm/hdmi/Makefile +2 -0
@@ -2,3 +2,5 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm obj-y := hdmi.o hdmi_phy.o hdmi_audio.o hdmi_bridge.o hdmi_connector.o \ hdmi_hdcp.o hdmi_i2c.o hdmi_phy_8960.o hdmi_phy_8x60.o hdmi_phy_8x74.o + +obj-$(CONFIG_COMMON_CLK) += hdmi_pll_8960.o
drivers/gpu/drm/msm/hdmi/hdmi.h +9 -0
@@ -199,6 +199,15 @@ void hdmi_phy_powerdown(struct hdmi_phy *phy);void __init hdmi_phy_driver_register (void ); void __exit hdmi_phy_driver_unregister(void); +#ifdef CONFIG_COMMON_CLK +int hdmi_pll_8960_init (struct platform_device *pdev); +#else +int hdmi_pll_8960_init (struct platform_device *pdev); +{ +return -ENODEV ; +} +#endif +/* * audio: */
drivers/gpu/drm/msm/hdmi/hdmi_phy.c +35 -0
@@ -118,6 +118,28 @@ void hdmi_phy_powerdown(struct hdmi_phy *phy) phy->cfg->powerdown (phy); } +static int hdmi_phy_pll_init (struct platform_device *pdev, +enum hdmi_phy_type type) +{ +int ret; + +switch (type) { +case MSM_HDMI_PHY_8960 : + ret =hdmi_pll_8960_init (pdev); +break ; +/* +* we don't have PLL support for these, don't report an error for now +*/ +case MSM_HDMI_PHY_8x60: +case MSM_HDMI_PHY_8x74: +default : + ret =0 ; +break ; + } + +return ret; +} +static int hdmi_phy_probe (struct platform_device *pdev) {struct device *dev = &pdev->dev;
@@ -146,6 +168,19 @@ static int hdmi_phy_probe(struct platform_device *pdev)pm_runtime_enable (&pdev->dev); + ret =hdmi_phy_resource_enable (phy); +if (ret) +return ret; + + ret =hdmi_phy_pll_init (pdev, phy->cfg->type); +if (ret) { +dev_err (dev,"couldn't init PLL\n" ); +hdmi_phy_resource_disable (phy); +return ret; + } + +hdmi_phy_resource_disable (phy); +platform_set_drvdata (pdev, phy);return 0 ;
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c new file +461 -0
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Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH v2 8/13 drm/msm/hdmi: Make HDMI core get its PHY
In reply to Archit TanejaMake HDMI core get its PHY by parsing the qcom,hdmi-phy phandle. The core will use this PHY reference to enable/disable PHY. The driver defers probe until PHY isn't available.
--- drivers/gpu/drm/msm/hdmi/hdmi.c | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/hdmi/hdmi.h | 2 ++ 2 files changed, 42 insertions(+)
drivers/gpu/drm/msm/hdmi/hdmi.c +40 -0
@@ -83,12 +83,46 @@ static void hdmi_destroy(struct hdmi *hdmi)if (phy) phy->funcs->destroy (phy); +if (hdmi->phy_dev) { +put_device (hdmi->phy_dev); + hdmi->phy =NULL ; + hdmi->phy_dev =NULL ; + } +if (hdmi->i2c)hdmi_i2c_destroy (hdmi->i2c);platform_set_drvdata (hdmi->pdev,NULL ); } +static int hdmi_get_phy (struct hdmi *hdmi) +{ +struct platform_device *pdev = hdmi->pdev; +struct platform_device *phy_pdev; +struct device_node *phy_node; + + phy_node =of_parse_phandle (pdev->dev.of_node,"qcom,hdmi-phy" ,0 ); +if (!phy_node) { +dev_err (&pdev->dev,"cannot find phy device\n" ); +return -ENXIO ; + } + + phy_pdev =of_find_device_by_node (phy_node); +if (phy_pdev) + hdmi->phy =platform_get_drvdata (phy_pdev); + +of_node_put (phy_node); + +if (!phy_pdev || !hdmi->phy) { +dev_err (&pdev->dev,"phy driver is not ready\n" ); +return -EPROBE_DEFER ; + } + + hdmi->phy_dev =get_device (&phy_pdev->dev); + +return 0 ; +} +/* construct hdmi at bind/probe time, grab all the resources. If * we are to EPROBE_DEFER we want to do it here, rather than later * at modeset_init() time
@@ -232,6 +266,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev) goto fail; } + ret =hdmi_get_phy (hdmi); +if (ret) { +dev_err (&pdev->dev,"failed to get phy\n" ); + goto fail; + } + hdmi->hdcp_ctrl =hdmi_hdcp_init (hdmi);if (IS_ERR (hdmi->hdcp_ctrl)) {dev_warn (&pdev->dev,"failed to init hdcp: disabled\n" );
drivers/gpu/drm/msm/hdmi/hdmi.h +2 -0
@@ -71,6 +71,8 @@ struct hdmi {struct clk **pwr_clks;struct hdmi_phy *phy; +struct device *phy_dev; +struct i2c_adapter *i2c;struct drm_connector *connector;struct drm_bridge *bridge;
Signature · 7 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v2 9/13 drm/msm/hdmi: Convert PHY files according to new design
In reply to Archit TanejaRemove the old PHY ops managed by hdmi_platform_config and use them as ops provided by the HDMI PHY driver.
Remove the old HDMI 8960 PLL code that used the top level HDMI TX mmio base.
NOTE: With this commit, HDMI functionality will break until the HDMI PHY/PLL register offsets in hdmi.xml.h aren't updated to be used as separate domains.
--- drivers/gpu/drm/msm/hdmi/hdmi.c | 25 +- drivers/gpu/drm/msm/hdmi/hdmi.h | 10 - drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 8 +- drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 493 +------------------------------ drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 194 +++++------- drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c | 82 +---- 6 files changed, 100 insertions(+), 712 deletions(-)
drivers/gpu/drm/msm/hdmi/hdmi.c +1 -24
@@ -69,8 +69,6 @@ static irqreturn_t hdmi_irq(int irq, void *dev_id)static void hdmi_destroy (struct hdmi *hdmi) { -struct hdmi_phy *phy = hdmi->phy; -/* * at this point, hpd has been disabled, * after flush workq, it's safe to deinit hdcp
@@ -80,8 +78,6 @@ static void hdmi_destroy(struct hdmi *hdmi)destroy_workqueue (hdmi->workq); }hdmi_hdcp_destroy (hdmi); -if (phy) - phy->funcs->destroy (phy);if (hdmi->phy_dev) {put_device (hdmi->phy_dev);
@@ -144,18 +140,6 @@ static struct hdmi *hdmi_init(struct platform_device *pdev) hdmi->config = config;spin_lock_init (&hdmi->reg_lock); -/* not sure about which phy maps to which msm.. probably I miss some */ -if (config->phy_init) { - hdmi->phy = config->phy_init (hdmi); - -if (IS_ERR (hdmi->phy)) { - ret =PTR_ERR (hdmi->phy); -dev_err (&pdev->dev,"failed to load phy: %d\n" , ret); - hdmi->phy =NULL ; - goto fail; - } - } - hdmi->mmio =msm_ioremap (pdev, config->mmio_name,"HDMI" );if (IS_ERR (hdmi->mmio)) { ret =PTR_ERR (hdmi->mmio);
@@ -373,15 +357,12 @@ fail:static const char *pwr_reg_names_none[] = {};static const char *hpd_reg_names_none[] = {}; -static struct hdmi_platform_config hdmi_tx_8660_config = { - .phy_init = hdmi_phy_8x60_init, -}; +static struct hdmi_platform_config hdmi_tx_8660_config;static const char *hpd_reg_names_8960[] = {"core-vdda" ,"hdmi-mux" };static const char *hpd_clk_names_8960[] = {"core_clk" ,"master_iface_clk" ,"slave_iface_clk" };static struct hdmi_platform_config hdmi_tx_8960_config = { - .phy_init = hdmi_phy_8960_init,HDMI_CFG (hpd_reg,8960 ),HDMI_CFG (hpd_clk,8960 ), };
@@ -393,7 +374,6 @@ static const char *hpd_clk_names_8x74[] = {"iface_clk", "core_clk", "mdp_core_clstatic unsigned long hpd_clk_freq_8x74[] = {0 ,19200000 ,0 };static struct hdmi_platform_config hdmi_tx_8974_config = { - .phy_init = hdmi_phy_8x74_init, HDMI_CFG(pwr_reg, 8x74), HDMI_CFG(hpd_reg, 8x74), HDMI_CFG(pwr_clk, 8x74),
@@ -404,7 +384,6 @@ static struct hdmi_platform_config hdmi_tx_8974_config = {static const char *hpd_reg_names_8084[] = {"hpd-gdsc" ,"hpd-5v" ,"hpd-5v-en" };static struct hdmi_platform_config hdmi_tx_8084_config = { - .phy_init = hdmi_phy_8x74_init, HDMI_CFG(pwr_reg, 8x74),HDMI_CFG (hpd_reg,8084 ), HDMI_CFG(pwr_clk, 8x74),
@@ -413,7 +392,6 @@ static struct hdmi_platform_config hdmi_tx_8084_config = { };static struct hdmi_platform_config hdmi_tx_8994_config = { - .phy_init =NULL ,/* nothing to do for this HDMI PHY 20nm */ HDMI_CFG(pwr_reg, 8x74),HDMI_CFG (hpd_reg, none), HDMI_CFG(pwr_clk, 8x74),
@@ -422,7 +400,6 @@ static struct hdmi_platform_config hdmi_tx_8994_config = { };static struct hdmi_platform_config hdmi_tx_8996_config = { - .phy_init =NULL ,HDMI_CFG (pwr_reg, none),HDMI_CFG (hpd_reg, none), HDMI_CFG(pwr_clk, 8x74),
drivers/gpu/drm/msm/hdmi/hdmi.h +0 -10
@@ -99,7 +99,6 @@ struct hdmi {/* platform config data (ie. from DT, or pdata) */ struct hdmi_platform_config { -struct hdmi_phy *(*phy_init)(struct hdmi *hdmi);const char *mmio_name;const char *qfprom_mmio_name;
@@ -144,11 +143,6 @@ static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)/* * hdmi phy: */ -struct hdmi_phy_funcs { -void (*destroy)(struct hdmi_phy *phy); -void (*powerup)(struct hdmi_phy *phy,unsigned long int pixclock); -void (*powerdown)(struct hdmi_phy *phy); -};enum hdmi_phy_type { MSM_HDMI_PHY_8x60,
@@ -180,10 +174,6 @@ struct hdmi_phy {struct clk **clks; }; -struct hdmi_phy *hdmi_phy_8960_init (struct hdmi *hdmi); -struct hdmi_phy *hdmi_phy_8x60_init (struct hdmi *hdmi); -struct hdmi_phy *hdmi_phy_8x74_init (struct hdmi *hdmi); -static inline void hdmi_phy_write (struct hdmi_phy *phy,u32 reg,u32 data) {msm_writel (data, phy->mmio + reg);
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +4 -4
@@ -95,13 +95,13 @@ static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)DBG ("power up" );if (!hdmi->power_on) { +hdmi_phy_resource_enable (phy);power_on (bridge); hdmi->power_on = true;hdmi_audio_update (hdmi); } -if (phy) - phy->funcs->powerup (phy, hdmi->pixclock); +hdmi_phy_powerup (phy, hdmi->pixclock);hdmi_set_mode (hdmi, true);
@@ -129,13 +129,13 @@ static void hdmi_bridge_post_disable(struct drm_bridge *bridge)DBG ("power down" );hdmi_set_mode (hdmi, false); -if (phy) - phy->funcs->powerdown (phy); +hdmi_phy_powerdown (phy);if (hdmi->power_on) {power_off (bridge); hdmi->power_on = false;hdmi_audio_update (hdmi); +hdmi_phy_resource_disable (phy); } }
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c +14 -479
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drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c +72 -122
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drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c +9 -73
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Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH v2 10/13 drm/msm/hdmi: Update generated headers to split PHY/PLL offsets
In reply to Archit Taneja- Create separate domains for 8960 PHY and PLL
- Create separate domains for 8x60 PHY
--- drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 157 +++++++++++++++++------------------- 1 file changed, 74 insertions(+), 83 deletions(-)
drivers/gpu/drm/msm/hdmi/hdmi.xml.h +74 -83
@@ -8,17 +8,8 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) +- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml ( 28770 bytes, from 2015-11-03 11:09:10) +- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-02-09 03:18:10) Copyright (C) 2013-2015 by the following authors: - Rob Clark <[email protected]> (robclark)
@@ -559,7 +550,7 @@ static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370 -#define REG_HDMI_8x60_PHY_REG0 0x00000300 +#define REG_HDMI_8x60_PHY_REG0 0x00000000#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL (uint32_t val)
@@ -567,7 +558,7 @@ static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; } -#define REG_HDMI_8x60_PHY_REG1 0x00000304 +#define REG_HDMI_8x60_PHY_REG1 0x00000004#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL (uint32_t val)
@@ -581,7 +572,7 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; } -#define REG_HDMI_8x60_PHY_REG2 0x00000308 +#define REG_HDMI_8x60_PHY_REG2 0x00000008#define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001#define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002#define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
@@ -591,152 +582,152 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)#define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080 -#define REG_HDMI_8x60_PHY_REG3 0x0000030c +#define REG_HDMI_8x60_PHY_REG3 0x0000000c#define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001 -#define REG_HDMI_8x60_PHY_REG4 0x00000310 +#define REG_HDMI_8x60_PHY_REG4 0x00000010 -#define REG_HDMI_8x60_PHY_REG5 0x00000314 +#define REG_HDMI_8x60_PHY_REG5 0x00000014 -#define REG_HDMI_8x60_PHY_REG6 0x00000318 +#define REG_HDMI_8x60_PHY_REG6 0x00000018 -#define REG_HDMI_8x60_PHY_REG7 0x0000031c +#define REG_HDMI_8x60_PHY_REG7 0x0000001c -#define REG_HDMI_8x60_PHY_REG8 0x00000320 +#define REG_HDMI_8x60_PHY_REG8 0x00000020 -#define REG_HDMI_8x60_PHY_REG9 0x00000324 +#define REG_HDMI_8x60_PHY_REG9 0x00000024 -#define REG_HDMI_8x60_PHY_REG10 0x00000328 +#define REG_HDMI_8x60_PHY_REG10 0x00000028 -#define REG_HDMI_8x60_PHY_REG11 0x0000032c +#define REG_HDMI_8x60_PHY_REG11 0x0000002c -#define REG_HDMI_8x60_PHY_REG12 0x00000330 +#define REG_HDMI_8x60_PHY_REG12 0x00000030#define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002#define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010 -#define REG_HDMI_8960_PHY_REG0 0x00000400 +#define REG_HDMI_8960_PHY_REG0 0x00000000 -#define REG_HDMI_8960_PHY_REG1 0x00000404 +#define REG_HDMI_8960_PHY_REG1 0x00000004 -#define REG_HDMI_8960_PHY_REG2 0x00000408 +#define REG_HDMI_8960_PHY_REG2 0x00000008 -#define REG_HDMI_8960_PHY_REG3 0x0000040c +#define REG_HDMI_8960_PHY_REG3 0x0000000c -#define REG_HDMI_8960_PHY_REG4 0x00000410 +#define REG_HDMI_8960_PHY_REG4 0x00000010 -#define REG_HDMI_8960_PHY_REG5 0x00000414 +#define REG_HDMI_8960_PHY_REG5 0x00000014 -#define REG_HDMI_8960_PHY_REG6 0x00000418 +#define REG_HDMI_8960_PHY_REG6 0x00000018 -#define REG_HDMI_8960_PHY_REG7 0x0000041c +#define REG_HDMI_8960_PHY_REG7 0x0000001c -#define REG_HDMI_8960_PHY_REG8 0x00000420 +#define REG_HDMI_8960_PHY_REG8 0x00000020 -#define REG_HDMI_8960_PHY_REG9 0x00000424 +#define REG_HDMI_8960_PHY_REG9 0x00000024 -#define REG_HDMI_8960_PHY_REG10 0x00000428 +#define REG_HDMI_8960_PHY_REG10 0x00000028 -#define REG_HDMI_8960_PHY_REG11 0x0000042c +#define REG_HDMI_8960_PHY_REG11 0x0000002c -#define REG_HDMI_8960_PHY_REG12 0x00000430 +#define REG_HDMI_8960_PHY_REG12 0x00000030#define HDMI_8960_PHY_REG12_SW_RESET 0x00000020#define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080 -#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000434 +#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034 -#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000438 +#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038 -#define REG_HDMI_8960_PHY_REG_MISC0 0x0000043c +#define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c -#define REG_HDMI_8960_PHY_REG13 0x00000440 +#define REG_HDMI_8960_PHY_REG13 0x00000040 -#define REG_HDMI_8960_PHY_REG14 0x00000444 +#define REG_HDMI_8960_PHY_REG14 0x00000044 -#define REG_HDMI_8960_PHY_REG15 0x00000448 +#define REG_HDMI_8960_PHY_REG15 0x00000048 -#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000500 +#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000 -#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000504 +#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004 -#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000508 +#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008 -#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000050c +#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c -#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000510 +#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010 -#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000514 +#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014 -#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000518 +#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008 -#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000051c +#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c -#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000520 +#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020 -#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000524 +#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024 -#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000528 +#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028 -#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000052c +#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c -#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000530 +#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030 -#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000534 +#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034 -#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000538 +#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038 -#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000053c +#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c -#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000540 +#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040 -#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000544 +#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044 -#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000548 +#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048 -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000054c +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000550 +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050 -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000554 +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054 -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000558 +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058 -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000055c +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000560 +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060 -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000564 +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064 -#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000568 +#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068 -#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000056c +#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c -#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000570 +#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070 -#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000574 +#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074 -#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000578 +#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078 -#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000057c +#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c -#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000580 +#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080 -#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000584 +#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084 -#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000588 +#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088 -#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000058c +#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c -#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000590 +#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090 -#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000594 +#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094 -#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000598 +#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001 -#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000059c +#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c#define REG_HDMI_8x74_ANA_CFG0 0x00000000
Signature · 7 lines
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PATCH v2 11/13 drm/msm/hdmi: Update generated headers for HDMI 8996 PHY
In reply to Archit TanejaAdds HDMI 8996 PHY offsets. The offsets are divided into 3 parts:
- Core HDMI PHY registers
- HDMI PLL registers (part of QSERDES block)
- HDMI TX lane registers (part of QSERDES block)
--- drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 500 +++++++++++++++++++++++++++++++++++- 1 file changed, 498 insertions(+), 2 deletions(-)
drivers/gpu/drm/msm/hdmi/hdmi.xml.h +498 -2
@@ -8,10 +8,10 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml ( 28770 bytes, from 2015-11-03 11:09:10) +- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-08 08:20:42) - /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-02-09 03:18:10) -Copyright (C) 2013-2015 by the following authors: +Copyright (C) 2013-2016 by the following authors: - Rob Clark <[email protected]> (robclark) Permission is hereby granted, free of charge, to any person obtaining
@@ -834,5 +834,501 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 +#define REG_HDMI_8996_PHY_CFG 0x00000000 + +#define REG_HDMI_8996_PHY_PD_CTL 0x00000004 + +#define REG_HDMI_8996_PHY_MODE 0x00000008 + +#define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c + +#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010 + +#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014 + +#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018 + +#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c + +#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020 + +#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024 + +#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028 + +#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c + +#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030 + +#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034 + +#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038 + +#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c + +#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040 + +#define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044 + +#define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048 + +#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c + +#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050 + +#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054 + +#define REG_HDMI_8996_PHY_CLOCK 0x00000058 + +#define REG_HDMI_8996_PHY_MISC1 0x0000005c + +#define REG_HDMI_8996_PHY_MISC2 0x00000060 + +#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064 + +#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068 + +#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c + +#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070 + +#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074 + +#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078 + +#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c + +#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080 + +#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084 + +#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088 + +#define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c + +#define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090 + +#define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094 + +#define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098 + +#define REG_HDMI_8996_PHY_STATUS 0x0000009c + +#define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0 + +#define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4 + +#define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8 + +#define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac + +#define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0 + +#define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4 + +#define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8 + +#define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc + +#define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0 + +#define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4 + +#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000 + +#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004 + +#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008 + +#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c + +#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010 + +#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014 + +#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018 + +#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c + +#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020 + +#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024 + +#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028 + +#define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c + +#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030 + +#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034 + +#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038 + +#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c + +#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068 + +#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c + +#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c + +#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070 + +#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074 + +#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078 + +#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c + +#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c + +#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c + +#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098 + +#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c + +#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0 + +#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4 + +#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8 + +#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8 + +#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac + +#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0 + +#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4 + +#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8 + +#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc + +#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0 + +#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8 + +#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc + +#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0 + +#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4 + +#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8 + +#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8 + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0 + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4 + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8 + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0 + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4 + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8 + +#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc + +#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100 + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104 + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108 + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110 + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114 + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118 + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c + +#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144 + +#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148 + +#define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c + +#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150 + +#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154 + +#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c + +#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160 + +#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164 + +#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168 + +#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c + +#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170 + +#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174 + +#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178 + +#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c + +#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180 + +#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184 + +#define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188 + +#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c + +#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198 + +#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c + +#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0 + +#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4 + +#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8 + +#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac + +#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8 + +#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc + +#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0 + +#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004 + +#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008 + +#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c + +#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010 + +#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020 + +#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030 + +#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c + +#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040 + +#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044 + +#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048 + +#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c + +#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050 + +#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c + +#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060 + +#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064 + +#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c + +#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090 + +#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094 + +#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098 + +#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c + +#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0 + +#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4 + +#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8 + +#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac + +#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc + +#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0 + +#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8 + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0 + +#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4 + +#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8 + +#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108 + +#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c + +#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110 +#endif /* HDMI_XML */
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH v2 12/13 drm/msm/hdmi: HDMI 8996 PHY/PLL support
In reply to Archit TanejaAdd support for the HDMI PHY/PLL found in MSM8996/APQ8096.
Unlike the previous phys supported in the driver, this doesn't need the powerup/powerdown ops. The PLL prepare/unprepare clock ops enable/disable the phy itself.
--- drivers/gpu/drm/msm/hdmi/Makefile | 2 +- drivers/gpu/drm/msm/hdmi/hdmi.h | 8 + drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 + drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 766 +++++++++++++++++++++++++++++++ 4 files changed, 780 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
drivers/gpu/drm/msm/hdmi/Makefile +1 -1
@@ -3,4 +3,4 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm obj-y := hdmi.o hdmi_phy.o hdmi_audio.o hdmi_bridge.o hdmi_connector.o \ hdmi_hdcp.o hdmi_i2c.o hdmi_phy_8960.o hdmi_phy_8x60.o hdmi_phy_8x74.o -obj-$(CONFIG_COMMON_CLK) += hdmi_pll_8960.o +obj-$(CONFIG_COMMON_CLK) += hdmi_pll_8960.o hdmi_phy_8996.o
drivers/gpu/drm/msm/hdmi/hdmi.h +8 -0
@@ -148,6 +148,7 @@ enum hdmi_phy_type { MSM_HDMI_PHY_8x60,MSM_HDMI_PHY_8960 , MSM_HDMI_PHY_8x74, +MSM_HDMI_PHY_8996 , MSM_HDMI_PHY_MAX, };
@@ -164,6 +165,7 @@ struct hdmi_phy_cfg {extern const struct hdmi_phy_cfg hdmi_phy_8x60_cfg;extern const struct hdmi_phy_cfg hdmi_phy_8960_cfg;extern const struct hdmi_phy_cfg hdmi_phy_8x74_cfg; +extern const struct hdmi_phy_cfg hdmi_phy_8996_cfg;struct hdmi_phy {struct platform_device *pdev;
@@ -193,11 +195,17 @@ void __exit hdmi_phy_driver_unregister(void);#ifdef CONFIG_COMMON_CLK int hdmi_pll_8960_init (struct platform_device *pdev); +int hdmi_pll_8996_init (struct platform_device *pdev);#else int hdmi_pll_8960_init (struct platform_device *pdev); {return -ENODEV ; } + +int hdmi_pll_8996_init (struct platform_device *pdev) +{ +return -ENODEV ; +}#endif /*
drivers/gpu/drm/msm/hdmi/hdmi_phy.c +5 -0
@@ -127,6 +127,9 @@ static int hdmi_phy_pll_init(struct platform_device *pdev,case MSM_HDMI_PHY_8960 : ret =hdmi_pll_8960_init (pdev);break ; +case MSM_HDMI_PHY_8996 : + ret =hdmi_pll_8996_init (pdev); +break ;/* * we don't have PLL support for these, don't report an error for now */
@@ -200,6 +203,8 @@ static const struct of_device_id hdmi_phy_dt_match[] = { .data = &hdmi_phy_8960_cfg }, { .compatible = "qcom,hdmi-phy-8x74", .data = &hdmi_phy_8x74_cfg }, + { .compatible = "qcom,hdmi-phy-8996", + .data = &hdmi_phy_8996_cfg }, {} };
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c new file +766 -0
766 lines not on this page · raw message
Signature · 7 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v2 13/13 dt-bindings: msm/hdmi: Add HDMI PHY bindings
In reply to Archit TanejaAdd HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
--- .../devicetree/bindings/display/msm/hdmi.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/display/msm/hdmi.txt +38 -1
@@ -11,6 +11,7 @@ Required properties: - reg: Physical base address and length of the controller's registers - reg-names: "core_physical" - interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: device clocks See ../clocks/clock-bindings.txt for details. - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
@@ -18,6 +19,7 @@ Required properties: - qcom,hdmi-tx-hpd-gpio: hpd pin - core-vdda-supply: phandle to supply regulator - hdmi-mux-supply: phandle to mux regulator +- qcom,hdmi-phy: phandle to HDMI PHY device node Optional properties: - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
@@ -27,6 +29,27 @@ Optional properties: - pinctrl-0: the default pinctrl state (active) - pinctrl-1: the "sleep" pinctrl state +HDMI PHY: +Required properties: +- compatible: Could be the following + * "qcom,hdmi-phy-8x60" + * "qcom,hdmi-phy-8960" + * "qcom,hdmi-phy-8x74" + * "qcom,hdmi-phy-8996" +- reg: Physical base address and length of the registers of the PHY sub blocks. +- reg-names: The names of register regions. The following regions are required: + * "hdmi_pll" + * "hdmi_phy" + For HDMI PHY on msm8996, these additional register regions are required: + * "hdmi_tx_l0" + * "hdmi_tx_l1" + * "hdmi_tx_l3" + * "hdmi_tx_l4" +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- core-vdda-supply: phandle to vdda regulator device node + Example: / {
@@ -35,7 +58,7 @@ Example: hdmi: qcom,hdmi-tx-8960@4a00000 { compatible = "qcom,hdmi-tx-8960"; reg-names = "core_physical"; - reg = <0x04a00000 0x1000>; + reg = <0x04a00000 0x2f0>; interrupts = <GIC_SPI 79 0>; power-domains = <&mmcc MDSS_GDSC>; clock-names =
@@ -54,5 +77,19 @@ Example: pinctrl-names = "default", "sleep"; pinctrl-0 = <&hpd_active &ddc_active &cec_active>; pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + qcom,hdmi-phy = <&hdmi_phy>; + }; + + hdmi_phy: qcom,hdmi-phy-8960@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg-names = "hdmi_phy", + "hdmi_pll"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = "slave_iface_clk"; + clocks = <&mmcc HDMI_S_AHB_CLK>; + core-vdda-supply = <&pm8921_hdmi_mvs>; }; };
Signature · 7 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Rob Herring
maintainerRe: [PATCH v2 13/13] dt-bindings: msm/hdmi: Add HDMI PHY bindings
Quoted 25 lines · Archit Taneja
Add HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- .../devicetree/bindings/display/msm/hdmi.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -11,6 +11,7 @@ Required properties: - reg: Physical base address and length of the controller's registers - reg-names: "core_physical" - interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: device clocks See ../clocks/clock-bindings.txt for details. - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
Documentation/devicetree/bindings/display/msm/hdmi.txt Required properties: · line 22
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -18,6 +19,7 @@ Required properties: - qcom,hdmi-tx-hpd-gpio: hpd pin - core-vdda-supply: phandle to supply regulator - hdmi-mux-supply: phandle to mux regulator +- qcom,hdmi-phy: phandle to HDMI PHY device node
Why not use the generic phy binding?
Documentation/devicetree/bindings/display/msm/hdmi.txt Optional properties: · line 37
Quoted 13 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +6
-0Optional properties: - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin@@ -27,6 +29,27 @@ Optional properties: - pinctrl-0: the default pinctrl state (active) - pinctrl-1: the "sleep" pinctrl state +HDMI PHY: +Required properties: +- compatible: Could be the following + * "qcom,hdmi-phy-8x60" + * "qcom,hdmi-phy-8960" + * "qcom,hdmi-phy-8x74"
No wildcards please. Where's 8994?
Quoted 19 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +15
-0+ * "qcom,hdmi-phy-8996" +- reg: Physical base address and length of the registers of the PHY sub blocks. +- reg-names: The names of register regions. The following regions are required: + * "hdmi_pll" + * "hdmi_phy" + For HDMI PHY on msm8996, these additional register regions are required: + * "hdmi_tx_l0" + * "hdmi_tx_l1" + * "hdmi_tx_l3" + * "hdmi_tx_l4" +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- core-vdda-supply: phandle to vdda regulator device node + Example: / {
Documentation/devicetree/bindings/display/msm/hdmi.txt Example: · line 58
Quoted 1 line
Documentation/devicetree/bindings/display/msm/hdmi.txt +0
-0@@ -35,7 +58,7 @@ Example: hdmi: qcom,hdmi-tx-8960@4a00000 {
Node names should be generic, so just "hdmi".
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-1compatible = "qcom,hdmi-tx-8960"; reg-names = "core_physical"; - reg = <0x04a00000 0x1000>; + reg = <0x04a00000 0x2f0>; interrupts = <GIC_SPI 79 0>; power-domains = <&mmcc MDSS_GDSC>; clock-names =
Documentation/devicetree/bindings/display/msm/hdmi.txt Example: · line 84
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +5
-0@@ -54,5 +77,19 @@ Example: pinctrl-names = "default", "sleep"; pinctrl-0 = <&hpd_active &ddc_active &cec_active>; pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + qcom,hdmi-phy = <&hdmi_phy>; + }; + + hdmi_phy: qcom,hdmi-phy-8960@4a00400 {
ditto. phy@...
Quoted 15 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +9
-0+ compatible = "qcom,hdmi-phy-8960"; + reg-names = "hdmi_phy", + "hdmi_pll"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = "slave_iface_clk"; + clocks = <&mmcc HDMI_S_AHB_CLK>; + core-vdda-supply = <&pm8921_hdmi_mvs>; }; };Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 13/13] dt-bindings: msm/hdmi: Add HDMI PHY bindings
Quoted 24 lines · Rob Herring
Quoted 23 lines · Archit Taneja
Add HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- .../devicetree/bindings/display/msm/hdmi.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -11,6 +11,7 @@ Required properties: - reg: Physical base address and length of the controller's registers - reg-names: "core_physical" - interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: device clocks See ../clocks/clock-bindings.txt for details.
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Required properties: · line 22
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin@@ -18,6 +19,7 @@ Required properties: - qcom,hdmi-tx-hpd-gpio: hpd pin - core-vdda-supply: phandle to supply regulator - hdmi-mux-supply: phandle to mux regulator +- qcom,hdmi-phy: phandle to HDMI PHY device nodeWhy not use the generic phy binding?
You'd asked about this in the first version of this patch. You probably missed reading my reply. Partially my fault since I missed out putting the "In-Reply-to" when posting this set. I've mentioned the reason again here:
The PHY in the HDMI and DSI blocks can't be implemented using the common phy framework. The PHY blocks have a PLL sub-block within them which acts as a pixel clock source for the display processor block.
This dependency causes the need to split the phy power on sequence into 2 parts (one to enable resources to enable the PLL, and the other to enable the phy itself), which the phy framework can't do. That's the main reason not to use it. There are some more complex use cases for DSI PHY (drive two PHYs with the same DSI PLL) which the phy framework can't support.
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +0
-0Optional properties: - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin@@ -27,6 +29,27 @@ Optional properties: - pinctrl-0: the default pinctrl state (active) - pinctrl-1: the "sleep" pinctrl state
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Optional properties: · line 37
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +6
-0+HDMI PHY: +Required properties: +- compatible: Could be the following + * "qcom,hdmi-phy-8x60" + * "qcom,hdmi-phy-8960" + * "qcom,hdmi-phy-8x74"No wildcards please. Where's 8994?
I'll remove the wildcards. 8994 PHY isn't supported by the driver at the moment. I could keep the 8994 compatible string, the driver will bail out with an error. But that's something we already do for 8x74 since it doesn't have full PHY support either.
Quoted 34 lines
Quoted 20 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +15
-0+ * "qcom,hdmi-phy-8996" +- reg: Physical base address and length of the registers of the PHY sub blocks. +- reg-names: The names of register regions. The following regions are required: + * "hdmi_pll" + * "hdmi_phy" + For HDMI PHY on msm8996, these additional register regions are required: + * "hdmi_tx_l0" + * "hdmi_tx_l1" + * "hdmi_tx_l3" + * "hdmi_tx_l4" +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- core-vdda-supply: phandle to vdda regulator device node + Example: / {Documentation/devicetree/bindings/display/msm/hdmi.txt Example: · line 58
Quoted 1 line
Documentation/devicetree/bindings/display/msm/hdmi.txt +0
-0@@ -35,7 +58,7 @@ Example: hdmi: qcom,hdmi-tx-8960@4a00000 {Node names should be generic, so just "hdmi".
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-1compatible = "qcom,hdmi-tx-8960"; reg-names = "core_physical"; - reg = <0x04a00000 0x1000>; + reg = <0x04a00000 0x2f0>; interrupts = <GIC_SPI 79 0>; power-domains = <&mmcc MDSS_GDSC>; clock-names =@@ -54,5 +77,19 @@ Example: pinctrl-names = "default", "sleep"; pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Example: · line 84
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +5
-0pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + qcom,hdmi-phy = <&hdmi_phy>; + }; + + hdmi_phy: qcom,hdmi-phy-8960@4a00400 {ditto. phy@...
I'll fix these.
Thanks,
Archit
Signature · 5 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Rob Herring
maintainerRe: [PATCH v2 13/13] dt-bindings: msm/hdmi: Add HDMI PHY bindings
Quoted 47 lines · Archit Taneja
Quoted 29 lines · Rob Herring
Quoted 27 lines · Archit Taneja
Add HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- .../devicetree/bindings/display/msm/hdmi.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -11,6 +11,7 @@ Required properties: - reg: Physical base address and length of the controller's registers - reg-names: "core_physical" - interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: device clocks See ../clocks/clock-bindings.txt for details. - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pinQuoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Required properties: · line 22
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -18,6 +19,7 @@ Required properties: - qcom,hdmi-tx-hpd-gpio: hpd pin - core-vdda-supply: phandle to supply regulator - hdmi-mux-supply: phandle to mux regulator +- qcom,hdmi-phy: phandle to HDMI PHY device nodeWhy not use the generic phy binding?
You'd asked about this in the first version of this patch. You probably missed reading my reply. Partially my fault since I missed out putting the "In-Reply-to" when posting this set. I've mentioned the reason again here:
Quoted 4 lines
The PHY in the HDMI and DSI blocks can't be implemented using the common phy framework. The PHY blocks have a PLL sub-block within them which acts as a pixel clock source for the display processor block.
That sounds like a problem with the common phy framework, not the DT binding. Nothing says you have to use the common phy f/w if you use the phy binding. I say that as the binding maintainer. As a kernel developer, I would say fix the common phy framework to handle this case. However, I don't think anything prevents the phy driver from registering both a phy and a clock.
Quoted 6 lines
This dependency causes the need to split the phy power on sequence into 2 parts (one to enable resources to enable the PLL, and the other to enable the phy itself), which the phy framework can't do. That's the main reason not to use it. There are some more complex use cases for DSI PHY (drive two PHYs with the same DSI PLL) which the phy framework can't support.
Doesn't the phy framework already support the former? It has power on and init calls. Personally, I find the split there ill-defined.
Quoted 17 lines
Quoted 6 lines
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +0
-0Optional properties: - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin@@ -27,6 +29,27 @@ Optional properties: - pinctrl-0: the default pinctrl state (active) - pinctrl-1: the "sleep" pinctrl stateQuoted 9 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Optional properties: · line 37
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +6
-0+HDMI PHY: +Required properties: +- compatible: Could be the following + * "qcom,hdmi-phy-8x60" + * "qcom,hdmi-phy-8960" + * "qcom,hdmi-phy-8x74"No wildcards please. Where's 8994?
Quoted 4 lines
I'll remove the wildcards. 8994 PHY isn't supported by the driver at the moment. I could keep the 8994 compatible string, the driver will bail out with an error. But that's something we already do for 8x74 since it doesn't have full PHY support either.
You can document it later if you want. I just asked 'cause I knew the 8994 had one.
Rob
Re: [PATCH v2 13/13] dt-bindings: msm/hdmi: Add HDMI PHY bindings
Quoted 53 lines · Rob Herring
Quoted 47 lines · Archit Taneja
Quoted 29 lines · Rob Herring
Quoted 27 lines · Archit Taneja
Add HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- .../devicetree/bindings/display/msm/hdmi.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -11,6 +11,7 @@ Required properties: - reg: Physical base address and length of the controller's registers - reg-names: "core_physical" - interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: device clocks See ../clocks/clock-bindings.txt for details. - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pinQuoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Required properties: · line 22
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -18,6 +19,7 @@ Required properties: - qcom,hdmi-tx-hpd-gpio: hpd pin - core-vdda-supply: phandle to supply regulator - hdmi-mux-supply: phandle to mux regulator +- qcom,hdmi-phy: phandle to HDMI PHY device nodeWhy not use the generic phy binding?
You'd asked about this in the first version of this patch. You probably missed reading my reply. Partially my fault since I missed out putting the "In-Reply-to" when posting this set. I've mentioned the reason again here:
Quoted 4 lines
The PHY in the HDMI and DSI blocks can't be implemented using the common phy framework. The PHY blocks have a PLL sub-block within them which acts as a pixel clock source for the display processor block.
Quoted 6 lines
That sounds like a problem with the common phy framework, not the DT binding. Nothing says you have to use the common phy f/w if you use the phy binding. I say that as the binding maintainer. As a kernel developer, I would say fix the common phy framework to handle this case. However, I don't think anything prevents the phy driver from registering both a phy and a clock.
Okay. For some reason, I thought it would be wrong to use the same common phy bindings but use our own phy driver.
I will convert the bindings to the generic phy binding.
Quoted 10 lines
Quoted 7 lines
This dependency causes the need to split the phy power on sequence into 2 parts (one to enable resources to enable the PLL, and the other to enable the phy itself), which the phy framework can't do. That's the main reason not to use it. There are some more complex use cases for DSI PHY (drive two PHYs with the same DSI PLL) which the phy framework can't support.
Doesn't the phy framework already support the former? It has power on and init calls. Personally, I find the split there ill-defined.
I always assumed that the init/exit ops were something that you would call just once (during probe/remove) and then forget about it. I only now noticed that init and power_on are often paired together (as are power_off and exit). I went through the common phy framework code in more detail, but I realized I would face the following issue:
I was looking for the sequence:
1. enable PHY resources (enables clocks/regulators/pm_runtime_get_sync)
2. set_rate/enable the PLL clock provided by PHY
3. enable PHY (configure some PHY registers)
I can achieve this using the common phy framework if I tie step 1) to phy_power_on(), and step 3) to phy_init(). The other way round won't work because phy_init() seems to disable runtime pm as it exits.
If I use the phy framework in its current state, I'll end up stuffing the phy ops and use them in a weird way just to make sure my PHY works.
Copying Kishon if he has any opinions.
Quoted 18 lines
Quoted 18 lines
Quoted 16 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Optional properties: · line 37
Quoted 13 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +6
-0Optional properties: - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin@@ -27,6 +29,27 @@ Optional properties: - pinctrl-0: the default pinctrl state (active) - pinctrl-1: the "sleep" pinctrl state +HDMI PHY: +Required properties: +- compatible: Could be the following + * "qcom,hdmi-phy-8x60" + * "qcom,hdmi-phy-8960" + * "qcom,hdmi-phy-8x74"No wildcards please. Where's 8994?
Quoted 7 lines
Quoted 4 lines
I'll remove the wildcards. 8994 PHY isn't supported by the driver at the moment. I could keep the 8994 compatible string, the driver will bail out with an error. But that's something we already do for 8x74 since it doesn't have full PHY support either.
You can document it later if you want. I just asked 'cause I knew the 8994 had one.
Okay.
Thanks,
Archit
Signature · 5 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 13/13] dt-bindings: msm/hdmi: Add HDMI PHY bindings
Hi Archit,
Quoted 76 lines · Archit Taneja
Quoted 53 lines · Rob Herring
Quoted 47 lines · Archit Taneja
Quoted 29 lines · Rob Herring
Quoted 27 lines · Archit Taneja
Add HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- .../devicetree/bindings/display/msm/hdmi.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -11,6 +11,7 @@ Required properties: - reg: Physical base address and length of the controller's registers - reg-names: "core_physical" - interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: device clocks See ../clocks/clock-bindings.txt for details. - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pinQuoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Required properties: · line 22
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -18,6 +19,7 @@ Required properties: - qcom,hdmi-tx-hpd-gpio: hpd pin - core-vdda-supply: phandle to supply regulator - hdmi-mux-supply: phandle to mux regulator +- qcom,hdmi-phy: phandle to HDMI PHY device nodeWhy not use the generic phy binding?
You'd asked about this in the first version of this patch. You probably missed reading my reply. Partially my fault since I missed out putting the "In-Reply-to" when posting this set. I've mentioned the reason again here:
Quoted 4 lines
The PHY in the HDMI and DSI blocks can't be implemented using the common phy framework. The PHY blocks have a PLL sub-block within them which acts as a pixel clock source for the display processor block.
Quoted 6 lines
That sounds like a problem with the common phy framework, not the DT binding. Nothing says you have to use the common phy f/w if you use the phy binding. I say that as the binding maintainer. As a kernel developer, I would say fix the common phy framework to handle this case. However, I don't think anything prevents the phy driver from registering both a phy and a clock.
Okay. For some reason, I thought it would be wrong to use the same common phy bindings but use our own phy driver.
I will convert the bindings to the generic phy binding.
Quoted 8 lines
Quoted 7 lines
This dependency causes the need to split the phy power on sequence into 2 parts (one to enable resources to enable the PLL, and the other to enable the phy itself), which the phy framework can't do. That's the main reason not to use it. There are some more complex use cases for DSI PHY (drive two PHYs with the same DSI PLL) which the phy framework can't support.
Quoted 5 lines
Quoted 2 lines
Doesn't the phy framework already support the former? It has power on and init calls. Personally, I find the split there ill-defined.
I always assumed that the init/exit ops were something that you would call just once (during probe/remove) and then forget about it. I only
right, the phy ops were intended to be used that way. However because of different sequence requirements for different controllers, that's not followed always.
Quoted 7 lines
now noticed that init and
power_onare often paired together (as arepower_offand exit). I went through the common phy framework code in more detail, but I realized I would face the following issue:I was looking for the sequence:
1. enable PHY resources (enables clocks/regulators/pm_runtime_get_sync)
get_sync is invoked by the phy core during phy_init and phy_power_on (it was done basically to access registers that have to be configured during init and power on). regulator is enabled during phy_power_on and clocks (opt func clocks) should be enable during runtime callbacks in the driver (main clock is enabled as part of get_sync).
Quoted 2 lines
2. set_rate/enable the PLL clock provided by PHY
If the PHY is the source of clock, then the PHY should also be modeled as clock provider. (see rockchip-usb PHY)
Quoted 2 lines
3. enable PHY (configure some PHY registers)
the general configuration of the PHY should go in phy_init (e.g any calibration settings) and registers to power_on the PHY should go in phy_power_on.
Thanks
Kishon
Re: [PATCH v2 13/13] dt-bindings: msm/hdmi: Add HDMI PHY bindings
Hi Kishon,
Quoted 104 lines · Kishon Vijay Abraham I
Hi Archit,
Quoted 76 lines · Archit Taneja
Quoted 53 lines · Rob Herring
Quoted 47 lines · Archit Taneja
Quoted 29 lines · Rob Herring
Quoted 27 lines · Archit Taneja
Add HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- .../devicetree/bindings/display/msm/hdmi.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -11,6 +11,7 @@ Required properties: - reg: Physical base address and length of the controller's registers - reg-names: "core_physical" - interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: device clocks See ../clocks/clock-bindings.txt for details. - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pinQuoted 8 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt Required properties: · line 22
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/hdmi.txt +1
-0@@ -18,6 +19,7 @@ Required properties: - qcom,hdmi-tx-hpd-gpio: hpd pin - core-vdda-supply: phandle to supply regulator - hdmi-mux-supply: phandle to mux regulator +- qcom,hdmi-phy: phandle to HDMI PHY device nodeWhy not use the generic phy binding?
You'd asked about this in the first version of this patch. You probably missed reading my reply. Partially my fault since I missed out putting the "In-Reply-to" when posting this set. I've mentioned the reason again here:
Quoted 4 lines
The PHY in the HDMI and DSI blocks can't be implemented using the common phy framework. The PHY blocks have a PLL sub-block within them which acts as a pixel clock source for the display processor block.
Quoted 6 lines
That sounds like a problem with the common phy framework, not the DT binding. Nothing says you have to use the common phy f/w if you use the phy binding. I say that as the binding maintainer. As a kernel developer, I would say fix the common phy framework to handle this case. However, I don't think anything prevents the phy driver from registering both a phy and a clock.
Okay. For some reason, I thought it would be wrong to use the same common phy bindings but use our own phy driver.
I will convert the bindings to the generic phy binding.
Quoted 8 lines
Quoted 7 lines
This dependency causes the need to split the phy power on sequence into 2 parts (one to enable resources to enable the PLL, and the other to enable the phy itself), which the phy framework can't do. That's the main reason not to use it. There are some more complex use cases for DSI PHY (drive two PHYs with the same DSI PLL) which the phy framework can't support.
Quoted 5 lines
Quoted 2 lines
Doesn't the phy framework already support the former? It has power on and init calls. Personally, I find the split there ill-defined.
I always assumed that the init/exit ops were something that you would call just once (during probe/remove) and then forget about it. I only
right, the phy ops were intended to be used that way. However because of different sequence requirements for different controllers, that's not followed always.
Quoted 7 lines
now noticed that init and
power_onare often paired together (as arepower_offand exit). I went through the common phy framework code in more detail, but I realized I would face the following issue:I was looking for the sequence:
1. enable PHY resources (enables clocks/regulators/pm_runtime_get_sync)
get_syncis invoked by the phy core duringphy_initandphy_power_on(it was done basically to access registers that have to be configured during init and power on). regulator is enabled duringphy_power_onand clocks (opt func clocks) should be enable during runtime callbacks in the driver (main clock is enabled as part ofget_sync).Quoted 2 lines
2. set_rate/enable the PLL clock provided by PHY
Quoted 7 lines
If the PHY is the source of clock, then the PHY should also be modeled as clock provider. (see rockchip-usb PHY)
Quoted 2 lines
3. enable PHY (configure some PHY registers)
the general configuration of the PHY should go in
phy_init(e.g any calibration settings) and registers topower_onthe PHY should go inphy_power_on.
Thanks for the input. I currently have a custom hdmi phy driver, which is a clock provider too. The PLL clock provided by the PHY can't be configured (clk_set_rate, enabe etc.) unless we enable some of the PHY interface clocks and other resources (enabled via pm_runtime_get_sync). These resources need to be left on for the clock to be configured successfully. The only way I can think of mapping my code with the phy ops that satisfies the above requirements will result in the following sequence:
...phy_power_on(phy);
clk_set_rate(pll);clk_prepare_enable(pll);
phy_init(phy);
...
This would be a bit of a misuse. To make things more complicated, some of the PHY register need to be configured in a sequence which also contains PLL registers. So, instead of these being in phy_init/phy_power_on, they have to be in the PLL's clock ops, which sort of makes things even more vague.
I would go with my custom hdmi phy implementation for now using generic phy bindings, but I'll try to investigate more on what can be done to get this running using the common phy f/w.
Thanks,
Archit
Signature · 5 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel