support hi3xxx soc
Subsystems (5)
v2 cover support hi3xxx soc
Changelog:
v2:
1. Reuse mux & divider driver. So append CLK_MUX_HIWORD_MASK & CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
2. Fix system timer running too fast because wrong divider is choosen.
3. Remove .init_irq in DT machine descriptor.
PATCH v2 1/6 ARM: debug: support debug ll on hisilicon soc
Support UART0 debug ll on hisilicon Hi3620 SoC.
--- arch/arm/Kconfig.debug | 15 +++++++++++++++ arch/arm/include/debug/hisilicon.S | 30 ++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm/include/debug/hisilicon.S
arch/arm/Kconfig.debug +15 -0
@@ -251,6 +251,20 @@ choice Say Y here if you want kernel low-level debugging support on i.MX6Q/DL. + config DEBUG_HI3620_UART + bool "Hisilicon HI3620 Debug UART" + depends on ARCH_HI3xxx + help + Say Y here if you want kernel low-level debugging support + on HI3620 UART. + + config DEBUG_HI3716_UART + bool "Hisilicon Hi3716 Debug UART" + depends on ARCH_HI3xxx + help + Say Y here if you want kernel low-level debugging support + on HI3716 UART. + config DEBUG_MMP_UART2 bool "Kernel low-level debugging message via MMP UART2" depends on ARCH_MMP
@@ -623,6 +637,7 @@ config DEBUG_LL_INCLUDE default "debug/cns3xxx.S" if DEBUG_CNS3XXX default "debug/exynos.S" if DEBUG_EXYNOS_UART default "debug/highbank.S" if DEBUG_HIGHBANK_UART + default "debug/hisilicon.S" if DEBUG_HI3620_UART || DEBUG_HI3716_UART default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \
arch/arm/include/debug/hisilicon.S new file +30 -0
@@ -0,0 +1,30 @@ +/* + * Early serial output macro for Hisilicon SoC + * + * Copyright (C) 2012-2013 Hisilicon Technologies Co., Ltd. + * Copyright (C) 2012-2013 Linaro Ltd. + * + * Author: Haojian Zhuang <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#if defined(CONFIG_DEBUG_HI3620_UART) +#define HS_UART_PHYS_BASE 0xfcb00000 +#define HS_UART_VIRT_BASE 0xfeb00000 +#elif defined(CONFIG_DEBUG_HI3716_UART) +#define HS_UART_PHYS_BASE 0xf8b00000 +#define HS_UART_VIRT_BASE 0xfeb00000 +#endif + +#if defined(CONFIG_DEBUG_HI3620_UART) || defined(CONFIG_DEBUG_HI3716_UART) + .macro addruart,rp,rv,tmp + ldr \rp, =HS_UART_PHYS_BASE + ldr \rv, =HS_UART_VIRT_BASE + .endm + +#include <asm/hardware/debug-pl01x.S> + +#endif
Signature · 1 line
1.8.1.2
Arnd Bergmann
maintainerPATCH v2 1/6 ARM: debug: support debug ll on hisilicon soc
Quoted 3 lines · On Tuesday 04 June 2013 23:05:12 Haojian Zhuang wrote:
Support UART0 debug ll on hisilicon Hi3620 SoC.
Signed-off-by Haojian Zhuang <[email protected]>
PATCH v2 2/6 clk: mux: add CLK_MUX_HIWORD_MASK
In reply to Haojian ZhuangThere's a HIWORD mask field in Hisilicon Hi3620 clock mux register. This field must be set while update the clk mux register. In order to reuse the clk-mux driver, append the CLK_MUX_HIWORD_MASK field into mux->flags.
--- drivers/clk/clk-mux.c | 8 ++++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 10 insertions(+)
drivers/clk/clk-mux.c +8 -0
@@ -70,6 +70,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) {struct clk_mux *mux =to_clk_mux (hw);u32 val; +u8 width =0 ;unsigned long flags =0 ;if (mux->table)
@@ -89,6 +90,13 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) val =readl (mux->reg); val &= ~(mux->mask << mux->shift); val |= index << mux->shift; +if (mux->flags &CLK_MUX_HIWORD_MASK ) { + width =fls (mux->mask) -ffs (mux->mask) +1 ; +if (width + mux->shift >16 ) +pr_warn ("mux value exceeds LOWORD field\n" ); +else + val |= mux->mask << (mux->shift +16 ); + }writel (val, mux->reg);if (mux->lock)
include/linux/clk-provider.h +2 -0
@@ -299,6 +299,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,* Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) +* CLK_MUX_HIWORD_MASK - register contains high 16-bit as mask field */ struct clk_mux {struct clk_hw hw;
@@ -312,6 +313,7 @@ struct clk_mux {#define CLK_MUX_INDEX_ONE BIT(0)#define CLK_MUX_INDEX_BIT BIT(1) +#define CLK_MUX_HIWORD_MASK BIT(2)extern const struct clk_ops clk_mux_ops;
Signature · 1 line
1.8.1.2
PATCH v2 3/6 clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
In reply to Haojian ZhuangIn Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver.
--- drivers/clk/clk-divider.c | 6 ++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 8 insertions(+)
drivers/clk/clk-divider.c +6 -0
@@ -220,6 +220,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, val =readl (divider->reg); val &= ~(div_mask (divider) << divider->shift); val |= value << divider->shift; +if (divider->flags &CLK_DIVIDER_HIWORD_MASK ) { +if (divider->width + divider->shift >16 ) +pr_warn ("divider value exceeds LOWORD field\n" ); +else + val |=div_mask (divider) << (divider->shift +16 ); + }writel (val, divider->reg);if (divider->lock)
include/linux/clk-provider.h +2 -0
@@ -257,6 +257,7 @@ struct clk_div_table {* Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). +* CLK_DIVIDER_HIWORD_MASK - register contains high 16-bit as mask field */ struct clk_divider {struct clk_hw hw;
@@ -271,6 +272,7 @@ struct clk_divider {#define CLK_DIVIDER_ONE_BASED BIT(0)#define CLK_DIVIDER_POWER_OF_TWO BIT(1)#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3)extern const struct clk_ops clk_divider_ops; struct clk *clk_register_divider(struct device *dev, const char *name,
Signature · 1 line
1.8.1.2
PATCH v2 3/6 clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
Quoted 4 lines · Haojian Zhuang
In Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver.
Signed-off-by Haojian Zhuang <[email protected]>
I don't understand this...
Quoted 1 line
+ *
CLK_DIVIDER_HIWORD_MASK- register contains high 16-bit as mask field
Could you be a bit more verbose here on what this actually means, so other users of this flag will realize if they need to set it?
In other cases in the clk subsystem where masks and shifts are used, the position and number of bits are stated, rather than a single flag indicating some 16 bits.
Yours,
Linus Walleij
PATCH v2 3/6 clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
Quoted 9 lines · Linus Walleij
Quoted 4 lines · Haojian Zhuang
In Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver.
Signed-off-by Haojian Zhuang <[email protected]>I don't understand this...
The mux or divider register in Hi3620 is 32-bit. The lower 16-bit is used to configure mux or divider, and the higher 16-bit is used to set mask of the mux or divier.
If I need to set b01 in mux/divider register, I also need to set (b11 << 16) for HIWORD mask in the same register. The reason to set (b11 << 16) is two bits are changed in the mux/divider register.
Quoted 6 lines
Quoted 2 lines
+ *
CLK_DIVIDER_HIWORD_MASK- register contains high 16-bit as mask fieldCould you be a bit more verbose here on what this actually means, so other users of this flag will realize if they need to set it?
I didn't find a better name for this flag. :(
Quoted 4 lines
In other cases in the clk subsystem where masks and shifts are used, the position and number of bits are stated, rather than a single flag indicating some 16 bits.
Those masks are different from mine because those're used to calculate which bits should be set or clear.
Regards
Haojian
PATCH v2 3/6 clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
In reply to Haojian ZhuangHi Haojian,
as Linus suggested, a bit of commentary for your side :-)
The same also applies to the similar changes to the mux clock.
Interestingly the gates on the hisilicon follow another paradigm altogether, where on the Rockchip they also use this mask-mechanism.
Am Dienstag, 4. Juni 2013, 17:05:14 schrieb Haojian Zhuang:
Quoted 14 lines
In Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver.
Signed-off-by Haojian Zhuang <[email protected]>--- drivers/clk/clk-divider.c | 6 ++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 8 insertions(+)drivers/clk/clk-divider.c +0
-0
drivers/clk/clk-divider.c static int clk_divider_set_rate(struct clk_hw *hw, · line 221
Quoted 2 lines
drivers/clk/clk-divider.c +0
-0@@ -220,6 +220,12 @@ static int clk_divider_set_rate(struct clk_hw *hw,unsigned long rate, val =readl (divider->reg); val &= ~(div_mask (divider) << divider->shift);
Do you really need to read the register value on the HiSilicon before changing it?
On the Rockchip side, the mask is used just for just this, to indicate the bits that are set in the lower part, so there there really is no separate read necessary when changing bits.
drivers/clk/clk-divider.c static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, · line 225
Quoted 4 lines
drivers/clk/clk-divider.c +3
-0val |= value << divider->shift; +if (divider->flags &CLK_DIVIDER_HIWORD_MASK ) { +if (divider->width + divider->shift >16 ) +pr_warn ("divider value exceeds LOWORD field\n" );
This can be checked in the clock setup. If shift and mask are exceeding the low word there is something seriously wrong with the setup data and the clock shouldn't be created at all. This also saves the conditional on every set operation.
Quoted 19 lines
drivers/clk/clk-divider.c +3
-0+else + val |=div_mask (divider) << (divider->shift +16 ); + }writel (val, divider->reg);if (divider->lock)include/linux/clk-provider.h +1
-0@@ -257,6 +257,7 @@ struct clk_div_table {* Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). +* CLK_DIVIDER_HIWORD_MASK - register contains high 16-bit as mask field */ struct clk_divider {struct clk_hw hw;
include/linux/clk-provider.h struct clk_divider { · line 275
Quoted 4 lines
include/linux/clk-provider.h +1
-0@@ -271,6 +272,7 @@ struct clk_divider {#define CLK_DIVIDER_ONE_BASED BIT(0)#define CLK_DIVIDER_POWER_OF_TWO BIT(1)#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3)
I like your naming a lot better than mine :-)
Heiko
PATCH v2 3/6 clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
Quoted 20 lines · Heiko St?bner
Hi Haojian,
as Linus suggested, a bit of commentary for your side :-)
The same also applies to the similar changes to the mux clock.
Interestingly the gates on the hisilicon follow another paradigm altogether, where on the Rockchip they also use this mask-mechanism.
Am Dienstag, 4. Juni 2013, 17:05:14 schrieb Haojian Zhuang:
Quoted 9 lines
In Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver.
Signed-off-by Haojian Zhuang <[email protected]>--- drivers/clk/clk-divider.c | 6 ++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 8 insertions(+)
Quoted 10 lines
drivers/clk/clk-divider.c static int clk_divider_set_rate(struct clk_hw *hw, · line 221
Quoted 7 lines
drivers/clk/clk-divider.c +0
-0@@ -220,6 +220,12 @@ static int clk_divider_set_rate(struct clk_hw *hw,unsigned long rate, val =readl (divider->reg); val &= ~(div_mask (divider) << divider->shift);Do you really need to read the register value on the HiSilicon before changing it?
Because there's a mask field in the register, it could work without reading. My purpose is only to do less change in common code.
Quoted 11 lines
On the Rockchip side, the mask is used just for just this, to indicate the bits that are set in the lower part, so there there really is no separate read necessary when changing bits.
drivers/clk/clk-divider.c static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, · line 225
Quoted 4 lines
drivers/clk/clk-divider.c +3
-0val |= value << divider->shift; +if (divider->flags &CLK_DIVIDER_HIWORD_MASK ) { +if (divider->width + divider->shift >16 ) +pr_warn ("divider value exceeds LOWORD field\n" );
Quoted 4 lines
This can be checked in the clock setup. If shift and mask are exceeding the low word there is something seriously wrong with the setup data and the clock shouldn't be created at all. This also saves the conditional on every set operation.
OK.
Quoted 19 lines
Quoted 19 lines
drivers/clk/clk-divider.c +3
-0+else + val |=div_mask (divider) << (divider->shift +16 ); + }writel (val, divider->reg);if (divider->lock)include/linux/clk-provider.h +1
-0@@ -257,6 +257,7 @@ struct clk_div_table {* Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). +* CLK_DIVIDER_HIWORD_MASK - register contains high 16-bit as mask field */ struct clk_divider {
Quoted 8 lines
include/linux/clk-provider.h struct clk_divider { · line 275
Quoted 6 lines
include/linux/clk-provider.h +1
-0struct clk_hw hw;@@ -271,6 +272,7 @@ struct clk_divider {#define CLK_DIVIDER_ONE_BASED BIT(0)#define CLK_DIVIDER_POWER_OF_TWO BIT(1)#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3)I like your naming a lot better than mine :-)
OK. How about I sent the next version. And you can base on mine version. I'll append your comments & logic in my version. And I'll split your patches into three that are gate, mux and divider.
Regards
Haojian
Quoted 3 lines
Heiko
PATCH v2 3/6 clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
Am Samstag, 8. Juni 2013, 05:17:16 schrieb Haojian Zhuang:
Quoted 86 lines · Heiko St?bner
Quoted 27 lines
Hi Haojian,
as Linus suggested, a bit of commentary for your side :-)
The same also applies to the similar changes to the mux clock.
Interestingly the gates on the hisilicon follow another paradigm altogether, where on the Rockchip they also use this mask-mechanism.
Am Dienstag, 4. Juni 2013, 17:05:14 schrieb Haojian Zhuang:
Quoted 17 lines
In Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver.
Signed-off-by Haojian Zhuang <[email protected]>---
drivers/clk/clk-divider.c | 6 ++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 8 insertions(+)drivers/clk/clk-divider.c +0
-0@@ -220,6 +220,12 @@ static int clk_divider_set_rate(struct clk_hw *hw,unsigned long rate, val =readl (divider->reg);Quoted 4 lines
drivers/clk/clk-divider.c static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, · line 221
Quoted 1 line
drivers/clk/clk-divider.c +0
-0val &= ~(div_mask (divider) << divider->shift);Do you really need to read the register value on the HiSilicon before changing it?
Because there's a mask field in the register, it could work without reading. My purpose is only to do less change in common code.
Quoted 6 lines
On the Rockchip side, the mask is used just for just this, to indicate the bits that are set in the lower part, so there there really is no separate read necessary when changing bits.
Quoted 2 lines
drivers/clk/clk-divider.c +0
-0val |= value << divider->shift;Quoted 8 lines
drivers/clk/clk-divider.c static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, · line 225
Quoted 3 lines
drivers/clk/clk-divider.c +3
-0+if (divider->flags &CLK_DIVIDER_HIWORD_MASK ) { +if (divider->width + divider->shift >16 ) +pr_warn ("divider value exceeds LOWORD field\n" );This can be checked in the clock setup. If shift and mask are exceeding the low word there is something seriously wrong with the setup data and the clock shouldn't be created at all. This also saves the conditional on every set operation.
OK.
Quoted 33 lines
Quoted 33 lines
drivers/clk/clk-divider.c +3
-0+else + val |=div_mask (divider) << (divider->shift +16 ); + }writel(val, divider->reg); if (divider->lock)include/linux/clk-provider.h +1
-0@@ -257,6 +257,7 @@ struct clk_div_table { * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). + * CLK_DIVIDER_HIWORD_MASK - register contains high 16-bit as maskfield
*/
struct
clk_divider{struct clk_hw hw;include/linux/clk-provider.h +0
-0@@ -271,6 +272,7 @@ struct clk_divider {#define CLK_DIVIDER_ONE_BASED BIT(0)#define CLK_DIVIDER_POWER_OF_TWO BIT(1)#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
Quoted 7 lines
Quoted 3 lines
include/linux/clk-provider.h struct clk_divider { · line 275
Quoted 1 line
include/linux/clk-provider.h +1
-0+#define CLK_DIVIDER_HIWORD_MASK BIT(3)I like your naming a lot better than mine :-)
OK. How about I sent the next version. And you can base on mine version. I'll append your comments & logic in my version. And I'll split your patches into three that are gate, mux and divider.
sure, go ahead, but would say without the unecessary read we talked about above.
Heiko
PATCH v2 4/6 clk: hi3xxx: add clock support
In reply to Haojian ZhuangAdd clock support with device tree on Hisilicon SoC.
--- .../devicetree/bindings/clock/hisilicon.txt | 66 ++++ drivers/clk/Makefile | 1 + drivers/clk/clk-hi3xxx.c | 401 +++++++++++++++++++++ 3 files changed, 468 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hisilicon.txt create mode 100644 drivers/clk/clk-hi3xxx.c
Documentation/devicetree/bindings/clock/hisilicon.txt new file +66 -0
@@ -0,0 +1,66 @@ +Device Tree Clock bindings for arch-hi3xxx + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties for mux clocks: + - compatible : Shall be "hisilicon,hi3620-clk-mux". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,clkmux-reg : array of mux register offset & mask bits + - hisilicon,clkmux-table : array of mux select bits + +Required properties for Hi3620 gate clocks: + - compatible : Shall be "hisilicon,hi3620-clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,hi3620-clkgate : array of enable register offset & enable bits + - hisilicon,hi3620-clkreset : array of reset register offset & enable bits + +Required properties for clock divider: + - compatible : Shall be "hisilicon,hi3620-clk-div". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - #hisilicon,clkdiv-table-cells : the number of parameters after phandle in + hisilicon,clkdiv-table property. + - hisilicon,clkdiv-table : list of value that are used to configure clock + divider. They're value of phandle, index & divider value. + - hisilicon,clkdiv : array of divider register offset & mask bits. + +Required properties for gate clocks: + - compatible : Shall be "hisilicon,clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,clkgate-inverted : bool value. True means that set-to-disable. + +For example: + timclk1: clkgate at 38 { + compatible = "hisilicon,clk-gate"; + #clock-cells = <0>; + clocks = <&refclk_timer1>; + clock-output-names = "timclk1"; + hisilicon,clkgate-inverted; + hisilicon,clkgate = <0 18>; + }; + + dtable: clkdiv at 0 { + #hisilicon,clkdiv-table-cells = <2>; + }; + + div_cfgaxi: clkdiv at 2 { + compatible = "hisilicon,hi3620-clk-div"; + #clock-cells = <0>; + clocks = <&div_shareaxi>; + clock-output-names = "cfgAXI_div"; + hisilicon,clkdiv-table = <&dtable 0x01 2>; + hisilicon,clkdiv = <0x100 0x60>; + };
drivers/clk/Makefile +1 -0
@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-composite.o # SoCs specific obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o +obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3xxx.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_ARCH_MXS) += mxs/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
drivers/clk/clk-hi3xxx.c new file +401 -0
401 lines not on this page · raw message
Signature · 1 line
1.8.1.2
PATCH v2 5/6 ARM: hi3xxx: add board support with device tree
In reply to Haojian ZhuangAdd board support with device tree for Hisilicon Hi36xx/Hi37xx platform.
--- .../bindings/arm/hisilicon/hisilicon.txt | 10 +++++ arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-hi3xxx/Kconfig | 13 +++++++ arch/arm/mach-hi3xxx/Makefile | 5 +++ arch/arm/mach-hi3xxx/hi3xxx.c | 44 ++++++++++++++++++++++ 6 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 arch/arm/mach-hi3xxx/Kconfig create mode 100644 arch/arm/mach-hi3xxx/Makefile create mode 100644 arch/arm/mach-hi3xxx/hi3xxx.c
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt new file +10 -0
@@ -0,0 +1,10 @@ +Hisilicon Platforms Device Tree Bindings +---------------------------------------------------- + +Hi3716 Development Board +Required root node properties: + - compatible = "hisilicon,hi3716-dkb"; + +Hi4511 Board +Required root node properties: + - compatible = "hisilicon,hi3620-hi4511";
arch/arm/Kconfig +2 -0
@@ -936,6 +936,8 @@ source "arch/arm/mach-footbridge/Kconfig" source "arch/arm/mach-gemini/Kconfig" +source "arch/arm/mach-hi3xxx/Kconfig" + source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-integrator/Kconfig"
arch/arm/Makefile +1 -0
@@ -147,6 +147,7 @@ machine-$(CONFIG_ARCH_DOVE) += dove machine-$(CONFIG_ARCH_EBSA110) += ebsa110 machine-$(CONFIG_ARCH_EP93XX) += ep93xx machine-$(CONFIG_ARCH_GEMINI) += gemini +machine-$(CONFIG_ARCH_HI3xxx) += hi3xxx machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_INTEGRATOR) += integrator machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
arch/arm/mach-hi3xxx/Kconfig new file +13 -0
@@ -0,0 +1,13 @@ +config ARCH_HI3xxx + bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select CACHE_L2X0 + select CACHE_PL310 + select CLKSRC_OF + select PINCTRL + select PINCTRL_SINGLE + select SERIAL_AMBA_PL011 + select SERIAL_AMBA_PL011_CONSOLE + help + Support for Hisilicon Hi36xx/Hi37xx processor family
arch/arm/mach-hi3xxx/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# Makefile for Hisilicon Hi36xx/Hi37xx processors line +# + +obj-y += hi3xxx.o
arch/arm/mach-hi3xxx/hi3xxx.c new file +44 -0
44 lines not on this page · raw message
Signature · 1 line
1.8.1.2
Arnd Bergmann
maintainerPATCH v2 5/6 ARM: hi3xxx: add board support with device tree
arch/arm/mach-hi3xxx/hi3xxx.c line 26
Quoted 5 lines · On Tuesday 04 June 2013 23:05:16 Haojian Zhuang wrote:
arch/arm/mach-hi3xxx/hi3xxx.c new file +5
-0+static void __init hi3xxx_timer_init (void ) +{ +of_clk_init (NULL ); +clocksource_of_init (); +}
I plan to make this the default, so maybe we will be able to get rid of this function soon. Right now it is still needed, as we only call clocksource_of_init() but not of_clk_init().
arch/arm/mach-hi3xxx/hi3xxx.c line 31
Quoted 4 lines
arch/arm/mach-hi3xxx/hi3xxx.c new file +4
-0+static void __init hs_init (void ) +{ +of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); +}
However, this is the default already. You can remove.
arch/arm/mach-hi3xxx/hi3xxx.c line 44
Quoted 12 lines
arch/arm/mach-hi3xxx/hi3xxx.c new file +12
-0+static const char *hs_compat[]__initdata = { +"hisilicon,hi3620-hi4511" , +NULL , +}; + +DT_MACHINE_START (HI3xxx,"Hisilicon Hi36xx/Hi37xx (Flattened Device Tree)" ) +/* Maintainer: Haojian Zhuang <[email protected]> */ + .map_io = debug_ll_io_init, + .init_time = hi3xxx_timer_init, + .init_machine = hs_init, + .dt_compat = hs_compat, +MACHINE_END
Same for debug_ll_io_init. You can remove the map_io and init_machine lines here.
With those gone,
Arnd
PATCH v2 5/6 ARM: hi3xxx: add board support with device tree
Quoted 12 lines · Arnd Bergmann
arch/arm/mach-hi3xxx/hi3xxx.c line 26
Quoted 5 lines · On Tuesday 04 June 2013 23:05:16 Haojian Zhuang wrote:
arch/arm/mach-hi3xxx/hi3xxx.c new file +5
-0+static void __init hi3xxx_timer_init (void ) +{ +of_clk_init (NULL ); +clocksource_of_init (); +}I plan to make this the default, so maybe we will be able to get rid of this function soon. Right now it is still needed, as we only call
clocksource_of_init()but notof_clk_init().
But my timer driver accesses clk. So I need to call of_clk_init() before clocksource_of_init(). Up to now, of_clk_init() isn't called by default.
Quoted 7 lines
arch/arm/mach-hi3xxx/hi3xxx.c line 31
Quoted 4 lines
arch/arm/mach-hi3xxx/hi3xxx.c new file +4
-0+static void __init hs_init (void ) +{ +of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); +}However, this is the default already. You can remove.
I'll update it.
Quoted 7 lines
Quoted 7 lines
arch/arm/mach-hi3xxx/hi3xxx.c new file +7
-0+static const char *hs_compat[]__initdata = { +"hisilicon,hi3620-hi4511" , +NULL , +}; + +DT_MACHINE_START (HI3xxx,"Hisilicon Hi36xx/Hi37xx (Flattened Device Tree)" ) +/* Maintainer: Haojian Zhuang <[email protected]> */
Quoted 8 lines
arch/arm/mach-hi3xxx/hi3xxx.c line 44
Quoted 5 lines
arch/arm/mach-hi3xxx/hi3xxx.c new file +5
-0+ .map_io = debug_ll_io_init, + .init_time = hi3xxx_timer_init, + .init_machine = hs_init, + .dt_compat = hs_compat, +MACHINE_END Same for
debug_ll_io_init. You can remove themap_ioandinit_machinelines here.
I'll update it.
Quoted 6 lines
With those gone,
Acked-by Arnd Bergmann <[email protected]>Arnd
Thanks
Haojian
Arnd Bergmann
maintainerPATCH v2 5/6 ARM: hi3xxx: add board support with device tree
Quoted 13 lines · On Wednesday 05 June 2013 11:04:27 Haojian Zhuang wrote:
Quoted 12 lines · Arnd Bergmann
arch/arm/mach-hi3xxx/hi3xxx.c line 26
Quoted 5 lines · On Tuesday 04 June 2013 23:05:16 Haojian Zhuang wrote:
arch/arm/mach-hi3xxx/hi3xxx.c new file +5
-0+static void __init hi3xxx_timer_init (void ) +{ +of_clk_init (NULL ); +clocksource_of_init (); +}I plan to make this the default, so maybe we will be able to get rid of this function soon. Right now it is still needed, as we only call
clocksource_of_init()but notof_clk_init().
Quoted 2 lines
But my timer driver accesses clk. So I need to call
of_clk_init()beforeclocksource_of_init(). Up to now,of_clk_init()isn't called by default.
Yes, I know. I mean we should change the common code to call of_clk_init by default, and do that before calling clocksource_of_init().
Arnd
PATCH v2 6/6 ARM: hi3xxx: enable hi4511 with device tree
In reply to Haojian ZhuangEnable Hisilicon Hi4511 development platform with device tree support.
--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/hi3620.dtsi | 1169 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/hi4511.dts | 738 ++++++++++++++++++++++ arch/arm/configs/multi_v7_defconfig | 1 + 4 files changed, 1909 insertions(+) create mode 100644 arch/arm/boot/dts/hi3620.dtsi create mode 100644 arch/arm/boot/dts/hi4511.dts
arch/arm/boot/dts/Makefile +1 -0
@@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ exynos5440-ssdk5440.dtb +dtb-$(CONFIG_ARCH_HI3xxx) += hi4511.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
arch/arm/boot/dts/hi3620.dtsi new file +1169 -0
1,169 lines not on this page · raw message
arch/arm/boot/dts/hi4511.dts new file +738 -0
738 lines not on this page · raw message
arch/arm/configs/multi_v7_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_MACH_ARMADA_370=y CONFIG_ARCH_SIRF=y CONFIG_MACH_ARMADA_XP=y CONFIG_ARCH_HIGHBANK=y +CONFIG_ARCH_HI3xxx=y CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_WM8850=y
Signature · 1 line
1.8.1.2
Arnd Bergmann
maintainerPATCH v2 6/6 ARM: hi3xxx: enable hi4511 with device tree
Quoted 3 lines · On Tuesday 04 June 2013 23:05:17 Haojian Zhuang wrote:
Enable Hisilicon Hi4511 development platform with device tree support.
Signed-off-by Haojian Zhuang <[email protected]>
Quoted 7 lines
arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/hi3620.dtsi | 1169 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/hi4511.dts | 738 ++++++++++++++++++++++ arch/arm/configs/multi_v7_defconfig | 1 + 4 files changed, 1909 insertions(+) create mode 100644 arch/arm/boot/dts/hi3620.dtsi create mode 100644 arch/arm/boot/dts/hi4511.dts
I received the patch in private mail, but apparently the linux-arm-kernel list rejected it. It's probably too large, can you send out separate patches for the two files next time?
Arnd
PATCH v2 6/6 ARM: hi3xxx: enable hi4511 with device tree
Quoted 16 lines · Arnd Bergmann
Quoted 3 lines · On Tuesday 04 June 2013 23:05:17 Haojian Zhuang wrote:
Enable Hisilicon Hi4511 development platform with device tree support.
Signed-off-by Haojian Zhuang <[email protected]>Acked-by Arnd Bergmann <[email protected]>Quoted 7 lines
arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/hi3620.dtsi | 1169 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/hi4511.dts | 738 ++++++++++++++++++++++ arch/arm/configs/multi_v7_defconfig | 1 + 4 files changed, 1909 insertions(+) create mode 100644 arch/arm/boot/dts/hi3620.dtsi create mode 100644 arch/arm/boot/dts/hi4511.dts
Quoted 5 lines
I received the patch in private mail, but apparently the linux-arm-kernel list rejected it. It's probably too large, can you send out separate patches for the two files next time?
Arnd
OK. I'll split it into two files in next time.
Regards
Haojian
PATCH v3 5/6 ARM: hi3xxx: add board support with device tree
In reply to Haojian ZhuangAdd board support with device tree for Hisilicon Hi36xx/Hi37xx platform.
Changelog:
v3:
1. Remove .map_io() in DT machine descriptor. Since debug_ll_io_init() is called by default.
2. Remove .init_machine() in DT machine descriptor. Since of_platform_populate() is called by default in DT mode.
v2:
1. Remove .init_irq() in DT machine descriptor. Since irqchip_init() is called by default in DT mode.
--- .../bindings/arm/hisilicon/hisilicon.txt | 10 ++++++ arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 1 + arch/arm/mach-hi3xxx/Kconfig | 13 ++++++++ arch/arm/mach-hi3xxx/Makefile | 5 +++ arch/arm/mach-hi3xxx/hi3xxx.c | 37 ++++++++++++++++++++++ 6 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 arch/arm/mach-hi3xxx/Kconfig create mode 100644 arch/arm/mach-hi3xxx/Makefile create mode 100644 arch/arm/mach-hi3xxx/hi3xxx.c
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt new file +10 -0
@@ -0,0 +1,10 @@ +Hisilicon Platforms Device Tree Bindings +---------------------------------------------------- + +Hi3716 Development Board +Required root node properties: + - compatible = "hisilicon,hi3716-dkb"; + +Hi4511 Board +Required root node properties: + - compatible = "hisilicon,hi3620-hi4511";
arch/arm/Kconfig +2 -0
@@ -936,6 +936,8 @@ source "arch/arm/mach-footbridge/Kconfig" source "arch/arm/mach-gemini/Kconfig" +source "arch/arm/mach-hi3xxx/Kconfig" + source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-integrator/Kconfig"
arch/arm/Makefile +1 -0
@@ -147,6 +147,7 @@ machine-$(CONFIG_ARCH_DOVE) += dove machine-$(CONFIG_ARCH_EBSA110) += ebsa110 machine-$(CONFIG_ARCH_EP93XX) += ep93xx machine-$(CONFIG_ARCH_GEMINI) += gemini +machine-$(CONFIG_ARCH_HI3xxx) += hi3xxx machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_INTEGRATOR) += integrator machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
arch/arm/mach-hi3xxx/Kconfig new file +13 -0
@@ -0,0 +1,13 @@ +config ARCH_HI3xxx + bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select CACHE_L2X0 + select CACHE_PL310 + select CLKSRC_OF + select PINCTRL + select PINCTRL_SINGLE + select SERIAL_AMBA_PL011 + select SERIAL_AMBA_PL011_CONSOLE + help + Support for Hisilicon Hi36xx/Hi37xx processor family
arch/arm/mach-hi3xxx/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# Makefile for Hisilicon Hi36xx/Hi37xx processors line +# + +obj-y += hi3xxx.o
arch/arm/mach-hi3xxx/hi3xxx.c new file +37 -0
@@ -0,0 +1,37 @@ +/* +* (Hisilicon's Hi36xx/Hi37xx SoC based) flattened device tree enabled machine +* +* Copyright (c) 2012-2013 Hisilicon Ltd. +* Copyright (c) 2012-2013 Linaro Ltd. +* +* Author: Haojian Zhuang <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/irqchip.h> +#include <linux/of_platform.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +static void __init hi3xxx_timer_init (void ) +{ +of_clk_init (NULL ); +clocksource_of_init (); +} + +static const char *hs_compat[]__initdata = { +"hisilicon,hi3620-hi4511" , +NULL , +}; + +DT_MACHINE_START (HI3xxx,"Hisilicon Hi36xx/Hi37xx (Flattened Device Tree)" ) +/* Maintainer: Haojian Zhuang <[email protected]> */ + .init_time = hi3xxx_timer_init, + .dt_compat = hs_compat, +MACHINE_END
Signature · 1 line
1.8.1.2