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mmc: tegra: properly disable card clock

PATCH Applied Lucas Stach 6 participants 10 messages Feb 29, 2016 – Mar 17, 2016 3 messages not in the archive

Subsystems (3)
MMC, SD and SDIO Tegra architecture support Secure digital host controller interface (SDHCI) driver
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Lucas Stach

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#0 lore raw

PATCH 1/2 mmc: tegra: properly disable card clock

The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing out. This breaks proper cutting of the card clock. Fix it by directly calling the correct sdhci function.

Fixes a8e326a911d3 "mmc: tegra: implement module external clock change"
Signed-off-by Lucas Stach <[email protected]>
---
 drivers/mmc/host/sdhci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/mmc/host/sdhci-tegra.c +1 -1
index 212d51f..46a6bd1 100644
@@ -194,7 +194,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	unsigned long host_clk;
 
 	if (!clock)
-		return;
+		return sdhci_set_clock(host, clock);;
 
 	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
 	clk_set_rate(pltfm_host->clk, host_clk);
Signature · 1 line
2.5.0

A message that is not in the archive (sent off-list or not yet received): 1456779385-18996-1-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org

#2 lore raw

PATCH 2/2 mmc: tegra: implement memcomp pad calibration

The Tegra30+ SDMMC module has memcomp pads that are used to automatically find and set the correct drive strength settings to the sdmmc pads. The calibration needs to be manually kicked off when the card signal voltage is changed, after the card clock is supplied again.

Signed-off-by Lucas Stach <[email protected]>

---
This commit allows signal voltage changes on my Tegar30 Beaver to succeed, making UHS-I modes work.

---
 drivers/mmc/host/sdhci-tegra.c | 47 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)
drivers/mmc/host/sdhci-tegra.c +44 -3
index 46a6bd1..9971732 100644
@@ -12,6 +12,7 @@
  *
  */
 
+#include "linux/delay.h"
 #include <linux/err.h>
 #include <linux/module.h>
 #include <linux/init.h>

@@ -42,12 +43,17 @@
 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300	0x20
 #define SDHCI_MISC_CTRL_ENABLE_DDR50		0x200
 
+#define SDHCI_TEGRA_AUTO_CAL_CONFIG		0x1e4
+#define SDHCI_AUTO_CAL_START			BIT(31)
+#define SDHCI_AUTO_CAL_ENABLE			BIT(29)
+
 #define NVQUIRK_FORCE_SDHCI_SPEC_200	BIT(0)
 #define NVQUIRK_ENABLE_BLOCK_GAP_DET	BIT(1)
 #define NVQUIRK_ENABLE_SDHCI_SPEC_300	BIT(2)
 #define NVQUIRK_ENABLE_SDR50		BIT(3)
 #define NVQUIRK_ENABLE_SDR104		BIT(4)
 #define NVQUIRK_ENABLE_DDR50		BIT(5)
+#define NVQUIRK_HAS_PADCALIB		BIT(6)
 
 struct sdhci_tegra_soc_data {
 	const struct sdhci_pltfm_data *pdata;

@@ -58,6 +64,7 @@ struct sdhci_tegra {
 	const struct sdhci_tegra_soc_data *soc_data;
 	struct gpio_desc *power_gpio;
 	bool ddr_signaling;
+	bool pad_calib_required;
 };
 
 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)

@@ -165,6 +172,9 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
 		clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
 	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 
+	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
+		tegra_host->pad_calib_required = true;
+
 	tegra_host->ddr_signaling = false;
 }
 

@@ -187,6 +197,17 @@ static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
+static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
+{
+	u32 val;
+
+	mdelay(1);
+
+	val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
+	val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
+	sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
+}
+
 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

@@ -200,7 +221,12 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	clk_set_rate(pltfm_host->clk, host_clk);
 	host->max_clk = clk_get_rate(pltfm_host->clk);
 
-	return sdhci_set_clock(host, clock);
+	sdhci_set_clock(host, clock);
+
+	if (tegra_host->pad_calib_required) {
+		tegra_sdhci_pad_autocalib(host);
+		tegra_host->pad_calib_required = false;
+	}
 }
 
 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,

@@ -270,6 +296,16 @@ static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
 	return mmc_send_tuning(host->mmc, opcode, NULL);
 }
 
+static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_tegra *tegra_host = pltfm_host->priv;
+	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
+
+	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
+		tegra_host->pad_calib_required = true;
+}
+
 static const struct sdhci_ops tegra_sdhci_ops = {
 	.get_ro     = tegra_sdhci_get_ro,
 	.read_w     = tegra_sdhci_readw,

@@ -279,6 +315,7 @@ static const struct sdhci_ops tegra_sdhci_ops = {
 	.reset      = tegra_sdhci_reset,
 	.platform_execute_tuning = tegra_sdhci_execute_tuning,
 	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
+	.voltage_switch = tegra_sdhci_voltage_switch,
 	.get_max_clock = tegra_sdhci_get_max_clock,
 };
 

@@ -312,7 +349,8 @@ static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
 	.pdata = &sdhci_tegra30_pdata,
 	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
 		    NVQUIRK_ENABLE_SDR50 |
-		    NVQUIRK_ENABLE_SDR104,
+		    NVQUIRK_ENABLE_SDR104 |
+		    NVQUIRK_HAS_PADCALIB,
 };
 
 static const struct sdhci_ops tegra114_sdhci_ops = {

@@ -325,6 +363,7 @@ static const struct sdhci_ops tegra114_sdhci_ops = {
 	.reset      = tegra_sdhci_reset,
 	.platform_execute_tuning = tegra_sdhci_execute_tuning,
 	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
+	.voltage_switch = tegra_sdhci_voltage_switch,
 	.get_max_clock = tegra_sdhci_get_max_clock,
 };
 

@@ -347,7 +386,8 @@ static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
 	.pdata = &sdhci_tegra114_pdata,
 	.nvquirks = NVQUIRK_ENABLE_SDR50 |
 		    NVQUIRK_ENABLE_DDR50 |
-		    NVQUIRK_ENABLE_SDR104,
+		    NVQUIRK_ENABLE_SDR104 |
+		    NVQUIRK_HAS_PADCALIB,
 };
 
 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {

@@ -402,6 +442,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
 		goto err_alloc_tegra_host;
 	}
 	tegra_host->ddr_signaling = false;
+	tegra_host->pad_calib_required = false;
 	tegra_host->soc_data = soc_data;
 	pltfm_host->priv = tegra_host;
Signature · 1 line
2.5.0
maintainer Acked-by on v1 2/2
#3 lore raw

Re: [PATCH 2/2] mmc: tegra: implement memcomp pad calibration

Quoted 11 lines · Lucas Stach

The Tegra30+ SDMMC module has memcomp pads that are used to automatically find and set the correct drive strength settings to the sdmmc pads. The calibration needs to be manually kicked off when the card signal voltage is changed, after the card clock is supplied again.

Signed-off-by Lucas Stach <[email protected]>

---
This commit allows signal voltage changes on my Tegar30 Beaver to succeed, making UHS-I modes work.
---

Doesn't apply cleanly, but otherwise looks OK.

Acked-by Adrian Hunter <[email protected]>
Applied
#4 lore raw

Re: [PATCH 2/2] mmc: tegra: implement memcomp pad calibration

In reply to Lucas Stach
Quoted 7 lines · Lucas Stach

The Tegra30+ SDMMC module has memcomp pads that are used to automatically find and set the correct drive strength settings to the sdmmc pads. The calibration needs to be manually kicked off when the card signal voltage is changed, after the card clock is supplied again.

Signed-off-by Lucas Stach <[email protected]>

Thanks applied for next, with a minor trivial fixup to resolve the conflict when applying.

Kind regards
Uffe

Quoted 155 lines

---
This commit allows signal voltage changes on my Tegar30 Beaver to succeed, making UHS-I modes work.

---
 drivers/mmc/host/sdhci-tegra.c | 47 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)
drivers/mmc/host/sdhci-tegra.c +44 -4
index 46a6bd1..9971732 100644
@@ -12,6 +12,7 @@
  *
  */
 
+#include "linux/delay.h"
 #include <linux/err.h>
 #include <linux/module.h>
 #include <linux/init.h>

@@ -42,12 +43,17 @@
 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300  0x20
 #define SDHCI_MISC_CTRL_ENABLE_DDR50           0x200
 
+#define SDHCI_TEGRA_AUTO_CAL_CONFIG            0x1e4
+#define SDHCI_AUTO_CAL_START                   BIT(31)
+#define SDHCI_AUTO_CAL_ENABLE                  BIT(29)
+
 #define NVQUIRK_FORCE_SDHCI_SPEC_200   BIT(0)
 #define NVQUIRK_ENABLE_BLOCK_GAP_DET   BIT(1)
 #define NVQUIRK_ENABLE_SDHCI_SPEC_300  BIT(2)
 #define NVQUIRK_ENABLE_SDR50           BIT(3)
 #define NVQUIRK_ENABLE_SDR104          BIT(4)
 #define NVQUIRK_ENABLE_DDR50           BIT(5)
+#define NVQUIRK_HAS_PADCALIB           BIT(6)
 
 struct sdhci_tegra_soc_data {
        const struct sdhci_pltfm_data *pdata;

@@ -58,6 +64,7 @@ struct sdhci_tegra {
        const struct sdhci_tegra_soc_data *soc_data;
        struct gpio_desc *power_gpio;
        bool ddr_signaling;
+       bool pad_calib_required;
 };
 
 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)

@@ -165,6 +172,9 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
                clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
        sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 
+       if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
+               tegra_host->pad_calib_required = true;
+
        tegra_host->ddr_signaling = false;
 }
 

@@ -187,6 +197,17 @@ static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
+static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
+{
+       u32 val;
+
+       mdelay(1);
+
+       val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
+       val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
+       sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
+}
+
 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 {
        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

@@ -200,7 +221,12 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
        clk_set_rate(pltfm_host->clk, host_clk);
        host->max_clk = clk_get_rate(pltfm_host->clk);
 
-       return sdhci_set_clock(host, clock);
+       sdhci_set_clock(host, clock);
+
+       if (tegra_host->pad_calib_required) {
+               tegra_sdhci_pad_autocalib(host);
+               tegra_host->pad_calib_required = false;
+       }
 }
 
 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,

@@ -270,6 +296,16 @@ static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
        return mmc_send_tuning(host->mmc, opcode, NULL);
 }
 
+static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+       struct sdhci_tegra *tegra_host = pltfm_host->priv;
+       const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
+
+       if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
+               tegra_host->pad_calib_required = true;
+}
+
 static const struct sdhci_ops tegra_sdhci_ops = {
        .get_ro     = tegra_sdhci_get_ro,
        .read_w     = tegra_sdhci_readw,

@@ -279,6 +315,7 @@ static const struct sdhci_ops tegra_sdhci_ops = {
        .reset      = tegra_sdhci_reset,
        .platform_execute_tuning = tegra_sdhci_execute_tuning,
        .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
+       .voltage_switch = tegra_sdhci_voltage_switch,
        .get_max_clock = tegra_sdhci_get_max_clock,
 };
 

@@ -312,7 +349,8 @@ static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
        .pdata = &sdhci_tegra30_pdata,
        .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
                    NVQUIRK_ENABLE_SDR50 |
-                   NVQUIRK_ENABLE_SDR104,
+                   NVQUIRK_ENABLE_SDR104 |
+                   NVQUIRK_HAS_PADCALIB,
 };
 
 static const struct sdhci_ops tegra114_sdhci_ops = {

@@ -325,6 +363,7 @@ static const struct sdhci_ops tegra114_sdhci_ops = {
        .reset      = tegra_sdhci_reset,
        .platform_execute_tuning = tegra_sdhci_execute_tuning,
        .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
+       .voltage_switch = tegra_sdhci_voltage_switch,
        .get_max_clock = tegra_sdhci_get_max_clock,
 };
 

@@ -347,7 +386,8 @@ static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
        .pdata = &sdhci_tegra114_pdata,
        .nvquirks = NVQUIRK_ENABLE_SDR50 |
                    NVQUIRK_ENABLE_DDR50 |
-                   NVQUIRK_ENABLE_SDR104,
+                   NVQUIRK_ENABLE_SDR104 |
+                   NVQUIRK_HAS_PADCALIB,
 };
 
 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {

@@ -402,6 +442,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
                goto err_alloc_tegra_host;
        }
        tegra_host->ddr_signaling = false;
+       tegra_host->pad_calib_required = false;
        tegra_host->soc_data = soc_data;
        pltfm_host->priv = tegra_host;
 
--

2.5.0

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#5 lore raw

Re: [PATCH 2/2] mmc: tegra: implement memcomp pad calibration

Quoted 11 lines · Ulf Hansson
Quoted 7 lines · Lucas Stach

The Tegra30+ SDMMC module has memcomp pads that are used to automatically find and set the correct drive strength settings to the sdmmc pads. The calibration needs to be manually kicked off when the card signal voltage is changed, after the card clock is supplied again.

Signed-off-by Lucas Stach <[email protected]>

Thanks applied for next, with a minor trivial fixup to resolve the conflict when applying.

I noticed this one also caused a compile error, so I did one more additional trivial rebase to fix it.

You should probably have look at my next branch, to make sure I haven't screwed up.

Kind regards
Uffe

Quoted 159 lines

Kind regards
Uffe

Quoted 155 lines

---
This commit allows signal voltage changes on my Tegar30 Beaver to succeed, making UHS-I modes work.

---
 drivers/mmc/host/sdhci-tegra.c | 47 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)
drivers/mmc/host/sdhci-tegra.c +44 -4
index 46a6bd1..9971732 100644
@@ -12,6 +12,7 @@
  *
  */
 
+#include "linux/delay.h"
 #include <linux/err.h>
 #include <linux/module.h>
 #include <linux/init.h>

@@ -42,12 +43,17 @@
 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300  0x20
 #define SDHCI_MISC_CTRL_ENABLE_DDR50           0x200
 
+#define SDHCI_TEGRA_AUTO_CAL_CONFIG            0x1e4
+#define SDHCI_AUTO_CAL_START                   BIT(31)
+#define SDHCI_AUTO_CAL_ENABLE                  BIT(29)
+
 #define NVQUIRK_FORCE_SDHCI_SPEC_200   BIT(0)
 #define NVQUIRK_ENABLE_BLOCK_GAP_DET   BIT(1)
 #define NVQUIRK_ENABLE_SDHCI_SPEC_300  BIT(2)
 #define NVQUIRK_ENABLE_SDR50           BIT(3)
 #define NVQUIRK_ENABLE_SDR104          BIT(4)
 #define NVQUIRK_ENABLE_DDR50           BIT(5)
+#define NVQUIRK_HAS_PADCALIB           BIT(6)
 
 struct sdhci_tegra_soc_data {
        const struct sdhci_pltfm_data *pdata;

@@ -58,6 +64,7 @@ struct sdhci_tegra {
        const struct sdhci_tegra_soc_data *soc_data;
        struct gpio_desc *power_gpio;
        bool ddr_signaling;
+       bool pad_calib_required;
 };
 
 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)

@@ -165,6 +172,9 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
                clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
        sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 
+       if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
+               tegra_host->pad_calib_required = true;
+
        tegra_host->ddr_signaling = false;
 }
 

@@ -187,6 +197,17 @@ static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
+static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
+{
+       u32 val;
+
+       mdelay(1);
+
+       val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
+       val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
+       sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
+}
+
 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 {
        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

@@ -200,7 +221,12 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
        clk_set_rate(pltfm_host->clk, host_clk);
        host->max_clk = clk_get_rate(pltfm_host->clk);
 
-       return sdhci_set_clock(host, clock);
+       sdhci_set_clock(host, clock);
+
+       if (tegra_host->pad_calib_required) {
+               tegra_sdhci_pad_autocalib(host);
+               tegra_host->pad_calib_required = false;
+       }
 }
 
 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,

@@ -270,6 +296,16 @@ static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
        return mmc_send_tuning(host->mmc, opcode, NULL);
 }
 
+static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+       struct sdhci_tegra *tegra_host = pltfm_host->priv;
+       const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
+
+       if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
+               tegra_host->pad_calib_required = true;
+}
+
 static const struct sdhci_ops tegra_sdhci_ops = {
        .get_ro     = tegra_sdhci_get_ro,
        .read_w     = tegra_sdhci_readw,

@@ -279,6 +315,7 @@ static const struct sdhci_ops tegra_sdhci_ops = {
        .reset      = tegra_sdhci_reset,
        .platform_execute_tuning = tegra_sdhci_execute_tuning,
        .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
+       .voltage_switch = tegra_sdhci_voltage_switch,
        .get_max_clock = tegra_sdhci_get_max_clock,
 };
 

@@ -312,7 +349,8 @@ static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
        .pdata = &sdhci_tegra30_pdata,
        .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
                    NVQUIRK_ENABLE_SDR50 |
-                   NVQUIRK_ENABLE_SDR104,
+                   NVQUIRK_ENABLE_SDR104 |
+                   NVQUIRK_HAS_PADCALIB,
 };
 
 static const struct sdhci_ops tegra114_sdhci_ops = {

@@ -325,6 +363,7 @@ static const struct sdhci_ops tegra114_sdhci_ops = {
        .reset      = tegra_sdhci_reset,
        .platform_execute_tuning = tegra_sdhci_execute_tuning,
        .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
+       .voltage_switch = tegra_sdhci_voltage_switch,
        .get_max_clock = tegra_sdhci_get_max_clock,
 };
 

@@ -347,7 +386,8 @@ static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
        .pdata = &sdhci_tegra114_pdata,
        .nvquirks = NVQUIRK_ENABLE_SDR50 |
                    NVQUIRK_ENABLE_DDR50 |
-                   NVQUIRK_ENABLE_SDR104,
+                   NVQUIRK_ENABLE_SDR104 |
+                   NVQUIRK_HAS_PADCALIB,
 };
 
 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {

@@ -402,6 +442,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
                goto err_alloc_tegra_host;
        }
        tegra_host->ddr_signaling = false;
+       tegra_host->pad_calib_required = false;
        tegra_host->soc_data = soc_data;
        pltfm_host->priv = tegra_host;
 
--

2.5.0

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maintainer Acked-by on v1 1/2
#6 lore raw
In reply to Lucas Stach
Quoted 17 lines · Lucas Stach

The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing out. This breaks proper cutting of the card clock. Fix it by directly calling the correct sdhci function.

Fixes a8e326a911d3 "mmc: tegra: implement module external clock change"
Signed-off-by Lucas Stach <[email protected]>
---
 drivers/mmc/host/sdhci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/mmc/host/sdhci-tegra.c +0 -0
index 212d51f..46a6bd1 100644

drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) · line 200

Quoted 8 lines
drivers/mmc/host/sdhci-tegra.c +1 -1
@@ -194,7 +194,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	unsigned long host_clk;
 
 	if (!clock)
-		return;
+		return sdhci_set_clock(host, clock);;
 
 	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
 	clk_set_rate(pltfm_host->clk, host_clk);
Acked-by Adrian Hunter <[email protected]>
Applied
#7 lore raw
In reply to Lucas Stach
Quoted 7 lines · Lucas Stach

The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing out. This breaks proper cutting of the card clock. Fix it by directly calling the correct sdhci function.

Fixes a8e326a911d3 "mmc: tegra: implement module external clock change"
Signed-off-by Lucas Stach <[email protected]>

Thanks, applied for fixes!

Kind regards
Uffe

Quoted 24 lines
---
 drivers/mmc/host/sdhci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/mmc/host/sdhci-tegra.c +1 -2
index 212d51f..46a6bd1 100644
@@ -194,7 +194,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
        unsigned long host_clk;
 
        if (!clock)
-               return;
+               return sdhci_set_clock(host, clock);;
 
        host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
        clk_set_rate(pltfm_host->clk, host_clk);
--

2.5.0

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#9 lore raw
Quoted 11 lines · Ulf Hansson
Quoted 7 lines · Lucas Stach

The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing out. This breaks proper cutting of the card clock. Fix it by directly calling the correct sdhci function.

Fixes a8e326a911d3 "mmc: tegra: implement module external clock change"
Signed-off-by Lucas Stach <[email protected]>

Thanks, applied for fixes!

Unfortunate I failed to send this in a PR to Linus within the 4.5 rc cycle, apologize for the inconvenience!
Instead I have this queued for 4.6 and I have added a stable tag to it.

[...]

Kind regards
Uffe

maintainer
#10 lore raw
In reply to Lucas Stach
Quoted 16 lines · Lucas Stach

The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing out. This breaks proper cutting of the card clock. Fix it by directly calling the correct sdhci function.

Fixes a8e326a911d3 "mmc: tegra: implement module external clock change"
Signed-off-by Lucas Stach <[email protected]>
---
 drivers/mmc/host/sdhci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/mmc/host/sdhci-tegra.c +0 -0
index 212d51f..46a6bd1 100644

drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) · line 197

Quoted 5 lines
drivers/mmc/host/sdhci-tegra.c +1 -1
@@ -194,7 +194,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	unsigned long host_clk;
 
 	if (!clock)
-		return;
+		return sdhci_set_clock(host, clock);;

Looks like the above adds an unnecessary additional semi-colon.

Ulf, are you able to correct, or do you want a patch?

Cheers
Jon

A message that is not in the archive (sent off-list or not yet received): [email protected]

#12 lore raw
Quoted 20 lines · Jon Hunter
Quoted 18 lines · Lucas Stach

The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing out. This breaks proper cutting of the card clock. Fix it by directly calling the correct sdhci function.

Fixes a8e326a911d3 "mmc: tegra: implement module external clock change"
Signed-off-by Lucas Stach <[email protected]>
---
 drivers/mmc/host/sdhci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/mmc/host/sdhci-tegra.c +0 -0
index 212d51f..46a6bd1 100644
@@ -194,7 +194,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
      unsigned long host_clk;
Quoted 7 lines

drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) · line 197

Quoted 3 lines
drivers/mmc/host/sdhci-tegra.c +1 -1
      if (!clock)
-             return;
+             return sdhci_set_clock(host, clock);;

Looks like the above adds an unnecessary additional semi-colon.

Ulf, are you able to correct, or do you want a patch?

Thanks for spotting this, I have amended the commit. No patch needed.

Thanks!

Kind regards
Uffe