Patch "dmaengine: dw: fix cyclic transfer setup" has been added to the 4.4-stable tree

This is a note to let you know that I've just added the patch titled

dmaengine: dw: fix cyclic transfer setup

to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
dmaengine-dw-fix-cyclic-transfer-setup.patch
and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Mans Rullgard <[email protected]>
Date: Mon, 11 Jan 2016 13:04:28 +0000
Subject: dmaengine: dw: fix cyclic transfer setup

From: Mans Rullgard <[email protected]>

commit df3bb8a0e619d501cd13334c3e0586edcdcbc716 upstream.

Commit 61e183f83069 ("dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume") moved some channel initialisation to a new function which must be called before starting a transfer.

This updates dw_dma_cyclic_start() to use dwc_dostart() like the other modes, thus ensuring dwc_initialize() gets called and removing some code duplication.

---
 drivers/dma/dw/core.c |   23 +----------------------
 1 file changed, 1 insertion(+), 22 deletions(-)

@@ -1245,7 +1245,6 @@ static void dwc_free_chan_resources(stru
 int dw_dma_cyclic_start(struct dma_chan *chan)
 {
 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-	struct dw_dma		*dw = to_dw_dma(dwc->chan.device);
 	unsigned long		flags;
 
 	if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {

@@ -1254,27 +1253,7 @@ int dw_dma_cyclic_start(struct dma_chan
 	}
 
 	spin_lock_irqsave(&dwc->lock, flags);
-
-	/* Assert channel is idle */
-	if (dma_readl(dw, CH_EN) & dwc->mask) {
-		dev_err(chan2dev(&dwc->chan),
-			"%s: BUG: Attempted to start non-idle channel\n",
-			__func__);
-		dwc_dump_chan_regs(dwc);
-		spin_unlock_irqrestore(&dwc->lock, flags);
-		return -EBUSY;
-	}
-
-	dma_writel(dw, CLEAR.ERROR, dwc->mask);
-	dma_writel(dw, CLEAR.XFER, dwc->mask);
-
-	/* Setup DMAC channel registers */
-	channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
-	channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
-	channel_writel(dwc, CTL_HI, 0);
-
-	channel_set_bit(dw, CH_EN, dwc->mask);
-
+	dwc_dostart(dwc, dwc->cdesc->desc[0]);
 	spin_unlock_irqrestore(&dwc->lock, flags);
 
 	return 0;

Patches currently in stable-queue which might be from [email protected] are

queue-4.4/dmaengine-dw-fix-cyclic-transfer-callbacks.patch queue-4.4/dmaengine-dw-fix-cyclic-transfer-setup.patch queue-4.4/dmaengine-dw-disable-block-irqs-for-non-cyclic-xfer.patch