x86/fpu: Revert earlier patch of Disable AVX when eagerfpu is off
PATCH v2 1/1 x86/fpu: Revert earlier patch of Disable AVX when eagerfpu is off
Because AVX is not stated in CR0 TS bit description, it was mistakenly believed to be not supported for lazy context switch. This turns out to be false. The earlier patch should be reverted.
Reference [1]:
Intel Software Developer's Manual Vol. 3A, Sec. 2.5 Control Registers:
TS Task Switched bit (bit 3 of CR0) -- Allows the saving of the x87 FPU/ MMX/SSE/SSE2/SSE3/SSSE3/SSE4 context on a task switch to be delayed until an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is actually executed by the new task.
Reference [2]:
Intel Software Developer's Manual Vol. 2A, Sec. 2.4 Instruction Exception Specification. AVX instructions refer to exceptions by classes that include #NM "Device Not Available" exception for lazy context switch.
Original patch:
commit 394db20ca240741a08d472173db13d6f6a6e5a28 ("x86/fpu: Disable AVX
when eagerfpu is off")
--- arch/x86/include/asm/fpu/xstate.h | 9 ++++----- arch/x86/kernel/fpu/init.c | 6 ------ 2 files changed, 4 insertions(+), 11 deletions(-)
arch/x86/include/asm/fpu/xstate.h +4 -5
@@ -20,16 +20,15 @@/* Supported features which support lazy state saving */ #define XFEATURE_MASK_LAZY (XFEATURE_MASK_FP | \ - XFEATURE_MASK_SSE) - -/* Supported features which require eager state saving */ -#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | \ - XFEATURE_MASK_BNDCSR | \ + XFEATURE_MASK_SSE | \ XFEATURE_MASK_YMM | \ XFEATURE_MASK_OPMASK | \ XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM) +/* Supported features which require eager state saving */ +#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR) +/* All currently supported features */ #define XCNTXT_MASK (XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER)
arch/x86/kernel/fpu/init.c +0 -6
@@ -300,12 +300,6 @@ u64 __init fpu__get_supported_xfeatures_mask(void)static void __init fpu__clear_eager_fpu_features (void ) {setup_clear_cpu_cap (X86_FEATURE_MPX ); -setup_clear_cpu_cap (X86_FEATURE_AVX ); -setup_clear_cpu_cap (X86_FEATURE_AVX2 ); -setup_clear_cpu_cap (X86_FEATURE_AVX512F ); -setup_clear_cpu_cap (X86_FEATURE_AVX512PF ); -setup_clear_cpu_cap (X86_FEATURE_AVX512ER ); -setup_clear_cpu_cap (X86_FEATURE_AVX512CD ); }/*
Signature · 1 line
1.9.1
tip-bot for Yu-cheng Yu
merge bot[tip:x86/urgent] x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off")
x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off")
Commit-ID: a65050c6f17e52442716138d48d0a47301a8344b Gitweb: http://git.kernel.org/tip/a65050c6f17e52442716138d48d0a47301a8344b Author: Yu-cheng Yu <[email protected]> AuthorDate: Wed, 9 Mar 2016 16:28:54 -0800 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 10 Mar 2016 10:15:58 +0100
x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off")
Leonid Shatz noticed that the SDM interpretation of the following recent commit:
394db20ca240741 ("x86/fpu: Disable AVX when eagerfpu is off")
... is incorrect and that the original behavior of the FPU code was correct.
Because AVX is not stated in CR0 TS bit description, it was mistakenly believed to be not supported for lazy context switch. This turns out to be false:
Intel Software Developer's Manual Vol. 3A, Sec. 2.5 Control Registers:
'TS Task Switched bit (bit 3 of CR0) -- Allows the saving of the x87 FPU/
MMX/SSE/SSE2/SSE3/SSSE3/SSE4 context on a task switch to be delayed until an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is actually executed by the new task.'
Intel Software Developer's Manual Vol. 2A, Sec. 2.4 Instruction Exception Specification:
'AVX instructions refer to exceptions by classes that include #NM
"Device Not Available" exception for lazy context switch.'
So revert the commit.
--- arch/x86/include/asm/fpu/xstate.h | 9 ++++----- arch/x86/kernel/fpu/init.c | 6 ------ 2 files changed, 4 insertions(+), 11 deletions(-)
arch/x86/include/asm/fpu/xstate.h +4 -5
@@ -20,16 +20,15 @@/* Supported features which support lazy state saving */ #define XFEATURE_MASK_LAZY (XFEATURE_MASK_FP | \ - XFEATURE_MASK_SSE) - -/* Supported features which require eager state saving */ -#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | \ - XFEATURE_MASK_BNDCSR | \ + XFEATURE_MASK_SSE | \ XFEATURE_MASK_YMM | \ XFEATURE_MASK_OPMASK | \ XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM) +/* Supported features which require eager state saving */ +#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR) +/* All currently supported features */ #define XCNTXT_MASK (XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER)
arch/x86/kernel/fpu/init.c +0 -6
@@ -302,12 +302,6 @@ u64 __init fpu__get_supported_xfeatures_mask(void)static void __init fpu__clear_eager_fpu_features (void ) {setup_clear_cpu_cap (X86_FEATURE_MPX ); -setup_clear_cpu_cap (X86_FEATURE_AVX ); -setup_clear_cpu_cap (X86_FEATURE_AVX2 ); -setup_clear_cpu_cap (X86_FEATURE_AVX512F ); -setup_clear_cpu_cap (X86_FEATURE_AVX512PF ); -setup_clear_cpu_cap (X86_FEATURE_AVX512ER ); -setup_clear_cpu_cap (X86_FEATURE_AVX512CD ); }/*