x86/perf/intel/uncore: remove ev_sel_ext bit support for PCU
Subsystems (2)
PATCH 1/1 x86/perf/intel/uncore: remove ev_sel_ext bit support for PCU
From: Kan Liang <[email protected]>
The ev_sel_ext in PCU_MSR_PMON_CTL is locked. So there could be #GP if writing that bit to 1. Also there is no public events which use the bit. This patch removes ev_sel_ext bit support for PCU.
Signed-off-by Kan Liang <[email protected]>
--- arch/x86/events/intel/uncore_snbep.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)
arch/x86/events/intel/uncore_snbep.c +2 -5
@@ -46,7 +46,6 @@ (SNBEP_PMON_CTL_EV_SEL_MASK | \ SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ SNBEP_PMON_CTL_EDGE_DET | \ - SNBEP_PMON_CTL_EV_SEL_EXT | \ SNBEP_PMON_CTL_INVERT | \ SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
@@ -148,7 +147,6 @@/* IVBEP PCU */ #define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ (SNBEP_PMON_CTL_EV_SEL_MASK | \ - SNBEP_PMON_CTL_EV_SEL_EXT | \ SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ SNBEP_PMON_CTL_EDGE_DET | \ SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
@@ -258,7 +256,6 @@SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \SNBEP_PMON_CTL_EDGE_DET | \SNBEP_CBO_PMON_CTL_TID_EN | \ -SNBEP_PMON_CTL_EV_SEL_EXT | \SNBEP_PMON_CTL_INVERT | \KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \ SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
@@ -472,7 +469,7 @@ static struct attribute *snbep_uncore_cbox_formats_attr[] = { };static struct attribute *snbep_uncore_pcu_formats_attr[] = { - &format_attr_event_ext.attr, + &format_attr_event.attr, &format_attr_occ_sel.attr, &format_attr_edge.attr, &format_attr_inv.attr,
@@ -1313,7 +1310,7 @@ static struct attribute *ivbep_uncore_cbox_formats_attr[] = { };static struct attribute *ivbep_uncore_pcu_formats_attr[] = { - &format_attr_event_ext.attr, + &format_attr_event.attr, &format_attr_occ_sel.attr, &format_attr_edge.attr, &format_attr_thresh5.attr,
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2.5.0
tip-bot for Kan Liang
merge bot[tip:perf/urgent] perf/x86/intel/uncore: Remove ev_sel_ext bit support for PCU
perf/x86/intel/uncore: Remove ev_sel_ext bit support for PCU
Commit-ID: cb2252522aaff572f28dc6613307e1e0e62496cd Gitweb: http://git.kernel.org/tip/cb2252522aaff572f28dc6613307e1e0e62496cd Author: Kan Liang <[email protected]> AuthorDate: Sun, 20 Mar 2016 11:58:21 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 21 Mar 2016 11:16:19 +0100
perf/x86/intel/uncore: Remove ev_sel_ext bit support for PCU
The ev_sel_ext in PCU_MSR_PMON_CTL is locked on some CPU models, so despite it being documented in the SDM, if we write 1 to that bit then we can get a #GP fault.
Which #GP the perf fuzzer happily triggered in Peter Zijlstra's testing.
Also, there are no public events which use that bit, so remove ev_sel_ext bit support for PCU.
Reported-by Peter Zijlstra <[email protected]>
Signed-off-by Kan Liang <[email protected]>
Acked-by Peter Zijlstra <[email protected]>
Cc Alexander Shishkin <[email protected]>
Cc Arnaldo Carvalho de Melo <[email protected]>
Cc David Ahern <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Linus Torvalds <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Stephane Eranian <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Vince Weaver <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
--- arch/x86/events/intel/uncore_snbep.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)
arch/x86/events/intel/uncore_snbep.c +2 -5
@@ -46,7 +46,6 @@ (SNBEP_PMON_CTL_EV_SEL_MASK | \ SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ SNBEP_PMON_CTL_EDGE_DET | \ - SNBEP_PMON_CTL_EV_SEL_EXT | \ SNBEP_PMON_CTL_INVERT | \ SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
@@ -148,7 +147,6 @@/* IVBEP PCU */ #define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ (SNBEP_PMON_CTL_EV_SEL_MASK | \ - SNBEP_PMON_CTL_EV_SEL_EXT | \ SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ SNBEP_PMON_CTL_EDGE_DET | \ SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
@@ -258,7 +256,6 @@SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \SNBEP_PMON_CTL_EDGE_DET | \SNBEP_CBO_PMON_CTL_TID_EN | \ -SNBEP_PMON_CTL_EV_SEL_EXT | \SNBEP_PMON_CTL_INVERT | \KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \ SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
@@ -472,7 +469,7 @@ static struct attribute *snbep_uncore_cbox_formats_attr[] = { };static struct attribute *snbep_uncore_pcu_formats_attr[] = { - &format_attr_event_ext.attr, + &format_attr_event.attr, &format_attr_occ_sel.attr, &format_attr_edge.attr, &format_attr_inv.attr,
@@ -1313,7 +1310,7 @@ static struct attribute *ivbep_uncore_cbox_formats_attr[] = { };static struct attribute *ivbep_uncore_pcu_formats_attr[] = { - &format_attr_event_ext.attr, + &format_attr_event.attr, &format_attr_occ_sel.attr, &format_attr_edge.attr, &format_attr_thresh5.attr,