Additional IPQ4019 platform support

This should have been bumped to 100 when the extra pins were added in the original pinctrl patch

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/pinctrl/qcom/pinctrl-ipq4019.c +1 -1

index b5d81ce..cb5f0a8 100644
@@ -414,7 +414,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
 	.nfunctions = ARRAY_SIZE(ipq4019_functions),
 	.groups = ipq4019_groups,
 	.ngroups = ARRAY_SIZE(ipq4019_groups),
-	.ngpios = 70,
+	.ngpios = 100,
 };
 
 static int ipq4019_pinctrl_probe(struct platform_device *pdev)

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

This should have been bumped to 100 when the extra pins were added in the original pinctrl patch

CC [email protected]

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

Without this, we would fail to set the mode to gpio if trying to configure for that mode

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/pinctrl/qcom/pinctrl-ipq4019.c +1 -1

index cb5f0a8..cb9f16a 100644
@@ -237,7 +237,7 @@ DECLARE_QCA_GPIO_PINS(99);
 		.pins = gpio##id##_pins,		\
 		.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins),	\
 		.funcs = (int[]){			\
-			qca_mux_NA, /* gpio mode */	\
+			qca_mux_gpio, /* gpio mode */	\
 			qca_mux_##f1,			\
 			qca_mux_##f2,			\
 			qca_mux_##f3,			\

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Without this, we would fail to set the mode to gpio if trying to configure for that mode

CC [email protected]

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

For this SoC the register offsets changed from previous versions to be separated by a larger amount.

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/pinctrl/qcom/pinctrl-ipq4019.c +5 -5

index cb9f16a..b68ae42 100644
@@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
 			qca_mux_##f14			\
 		},				        \
 		.nfuncs = 15,				\
-		.ctl_reg = 0x1000 + 0x10 * id,		\
-		.io_reg = 0x1004 + 0x10 * id,		\
-		.intr_cfg_reg = 0x1008 + 0x10 * id,	\
-		.intr_status_reg = 0x100c + 0x10 * id,	\
-		.intr_target_reg = 0x400 + 0x4 * id,	\
+		.ctl_reg = 0x0 + 0x1000 * id,		\
+		.io_reg = 0x4 + 0x1000 * id,		\
+		.intr_cfg_reg = 0x8 + 0x1000 * id,	\
+		.intr_status_reg = 0xc + 0x1000 * id,	\
+		.intr_target_reg = 0x8 + 0x1000 * id,	\
 		.mux_bit = 2,			\
 		.pull_bit = 0,			\
 		.drv_bit = 6,			\

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

For this SoC the register offsets changed from previous versions to be separated by a larger amount.

CC [email protected]

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

When this was added not all the remaining defines were switched over to use enums, so let's complete that process here

Reported-by Stephen Boyd <[email protected]>

Signed-off-by Matthew McClintock <[email protected]>

---

Drivers for these don't exist yet so we will add them as fixed clocks so we don't BUG() if we change clocks that reference these clocks.

Signed-off-by Matthew McClintock <[email protected]>

---

Update the compatible string to align with driver

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +0 -0

index 4726924..60bb2f98 100644
@@ -4,9 +4,8 @@ Qualcomm Krait Processor Sub-system (KPSS) Watchdog
 Required properties :

Quoted 4 lines · Matthew McClintock

Update the compatible string to align with driver

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

I had a patch similar to this before
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325235.html

Update the compatible string to align with driver

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +0 -0

index 4726924..60bb2f98 100644

Commit 0dfd582e026a ("watchdog: qcom: use timer devicetree binding") moved to use the watchdog as a subset timer register block. Some devices have the watchdog completely standalone with slightly different register offsets as well so let's account for the differences here.

Signed-off-by Matthew McClintock <[email protected]>

---
 drivers/watchdog/qcom-wdt.c | 69 ++++++++++++++++++++++++++++++++-------------
 1 file changed, 49 insertions(+), 20 deletions(-)

drivers/watchdog/qcom-wdt.c +5 -3

index 20563cc..e46f18d 100644
@@ -19,17 +19,37 @@
 #include <linux/platform_device.h>
 #include <linux/watchdog.h>
 
-#define WDT_RST		0x38
-#define WDT_EN		0x40
-#define WDT_BITE_TIME	0x5C
+enum wdt_reg {
+	WDT_RST,
+	WDT_EN,
+	WDT_BITE_TIME,
+};

drivers/watchdog/qcom-wdt.c +34 -17

+	[WDT_BITE_TIME] = 0x14,
+};
 
 struct qcom_wdt {
 	struct watchdog_device	wdd;
 	struct clk		*clk;
 	unsigned long		rate;
 	void __iomem		*base;
+	const u32		*layout;
 };
 
+static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
+{
+	return wdt->base + wdt->layout[reg];
+}
+
 static inline
 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
 {

@@ -40,10 +60,10 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
 {
 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-	writel(0, wdt->base + WDT_EN);
-	writel(1, wdt->base + WDT_RST);
-	writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME);
-	writel(1, wdt->base + WDT_EN);
+	writel(0, wdt_addr(wdt, WDT_EN));
+	writel(1, wdt_addr(wdt, WDT_RST));
+	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
+	writel(1, wdt_addr(wdt, WDT_EN));
 	return 0;
 }
 

@@ -51,7 +71,7 @@ static int qcom_wdt_stop(struct watchdog_device *wdd)
 {
 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-	writel(0, wdt->base + WDT_EN);
+	writel(0, wdt_addr(wdt, WDT_EN));
 	return 0;
 }
 

@@ -59,7 +79,7 @@ static int qcom_wdt_ping(struct watchdog_device *wdd)
 {
 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-	writel(1, wdt->base + WDT_RST);
+	writel(1, wdt_addr(wdt, WDT_RST));
 	return 0;
 }
 

@@ -82,10 +102,10 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
 	 */
 	timeout = 128 * wdt->rate / 1000;
 
-	writel(0, wdt->base + WDT_EN);
-	writel(1, wdt->base + WDT_RST);
-	writel(timeout, wdt->base + WDT_BITE_TIME);
-	writel(1, wdt->base + WDT_EN);
+	writel(0, wdt_addr(wdt, WDT_EN));
+	writel(1, wdt_addr(wdt, WDT_RST));
+	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
+	writel(1, wdt_addr(wdt, WDT_EN));
 
 	/*
 	 * Actually make sure the above sequence hits hardware before sleeping.

@@ -112,14 +132,29 @@ static const struct watchdog_info qcom_wdt_info = {
 	.identity	= KBUILD_MODNAME,
 };
 
+static const struct of_device_id qcom_wdt_of_table[] = {
+	{ .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
+	{ .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
+	{ .compatible = "qcom,kpss-standalone", .data = &reg_offset_data_kpss},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
+
 static int qcom_wdt_probe(struct platform_device *pdev)
 {
 	struct qcom_wdt *wdt;
 	struct resource *res;
 	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *match;
 	u32 percpu_offset;
 	int ret;
 
+	match = of_match_node(qcom_wdt_of_table, np);
+	if (!match) {
+		dev_err(&pdev->dev, "Unsupported QCOM WDT module\n");
+		return -ENODEV;
+	}
+
 	wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
 	if (!wdt)
 		return -ENOMEM;

@@ -170,6 +205,7 @@ static int qcom_wdt_probe(struct platform_device *pdev)
 	wdt->wdd.min_timeout = 1;
 	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
 	wdt->wdd.parent = &pdev->dev;
+	wdt->layout = match->data;
 
 	/*
 	 * If 'timeout-sec' unspecified in devicetree, assume a 30 second

@@ -202,13 +238,6 @@ static int qcom_wdt_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id qcom_wdt_of_table[] = {
-	{ .compatible = "qcom,kpss-timer" },
-	{ .compatible = "qcom,scss-timer" },
-	{ },
-};
-MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
-
 static struct platform_driver qcom_watchdog_driver = {
 	.probe	= qcom_wdt_probe,
 	.remove	= qcom_wdt_remove,

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Quoted 14 lines

drivers/watchdog/qcom-wdt.c +10 -3

-#define WDT_RST		0x38
-#define WDT_EN		0x40
-#define WDT_BITE_TIME	0x5C
+enum wdt_reg {
+	WDT_RST,
+	WDT_EN,
+	WDT_BITE_TIME,
+};
+
+static const u32 reg_offset_data_apcs_tmr[] = {
+	[WDT_RST] = 0x38,
+	[WDT_EN] = 0x40,
+	[WDT_BITE_TIME] = 0x5C,

drivers/watchdog/qcom-wdt.c line 36

Quoted 5 lines

drivers/watchdog/qcom-wdt.c +5 -0

+};
+
+static const u32 reg_offset_data_kpss[] = {
+	[WDT_RST] = 0x4,
+	[WDT_EN] = 0x8,

Does this work ? In the datasheet I have in front of me (APQ8064), the watchdog at this address uses different bits. At address 0x40 (eg GSS_A5_APCS_WDT0_EN),

bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is undefined.

Or does "qcom,kpss-standalone" refer to some other watchdog ?

Quoted 16 lines · Guenter Roeck

Quoted 14 lines

drivers/watchdog/qcom-wdt.c +10 -3

-#define WDT_RST		0x38
-#define WDT_EN		0x40
-#define WDT_BITE_TIME	0x5C
+enum wdt_reg {
+	WDT_RST,
+	WDT_EN,
+	WDT_BITE_TIME,
+};
+
+static const u32 reg_offset_data_apcs_tmr[] = {
+	[WDT_RST] = 0x38,
+	[WDT_EN] = 0x40,
+	[WDT_BITE_TIME] = 0x5C,

Quoted 8 lines

drivers/watchdog/qcom-wdt.c line 36

Quoted 5 lines

drivers/watchdog/qcom-wdt.c +5 -0

+};
+
+static const u32 reg_offset_data_kpss[] = {
+	[WDT_RST] = 0x4,
+	[WDT_EN] = 0x8,

Does this work ? In the datasheet I have in front of me (APQ8064), the watchdog at this address uses different bits. At address 0x40 (eg GSS_A5_APCS_WDT0_EN),

0x40 is acps_tmr, and looks fine.

Quoted 3 lines

bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is undefined.

I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts.

Quoted 1 line

Or does "qcom,kpss-standalone" refer to some other watchdog ?

APQ8064 would be the apcs_tmr block variant which is unchanged. MSM8916 as well as IPQ4019 would use the new kpss variant.

I went with block names I found internally here, but I will be the first to admit I am terrible at names. The old block name for APQ was CPU0_ACPS_TMR (where really the watchdog is a subset of a timer block), and on the IPQ4019 it’s called APCS_KPSS_WDT and it’s really just a watchdog block.

I kept the same driver because the register’s currently in use were compatible. By the way, I tested this on an IPQ806x and IPQ4019 both new and old blocks.

Quoted 7 lines

Quoted 4 lines

bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is undefined.

I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts.

That is from the APQ8064 datasheet.

Quoted 5 lines · Guenter Roeck

Quoted 5 lines

Quoted 4 lines

bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is undefined.

Quoted 3 lines

Quoted 2 lines

I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts.

That is from the APQ8064 datasheet.

So taken from the timer offset 0x0208A000 I just have a generic counter register CPU0_APCS_GPT0_CNT at 0x8

What doc are you looking at?

Quoted 5 lines

So taken from the timer offset 0x0208A000 I just have a generic counter register CPU0_APCS_GPT0_CNT at 0x8

What doc are you looking at?

"Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Description"

It is available for download from the Qualcomm web site.

See chapter 12.10.3, "Watchdog timer registers". The register block is at 0x28882000. Registers are almost the same, except for the offset and the definition of the bits in the enable register.

LPASS is "Low Power Audio Subsystem". Maybe it has its own watchdog.

For certain parts and some versions of TZ, TZ will reset the chip when a BARK is triggered even though it was not configured here. So by default let's configure this BARK time as well.

Quoted 4 lines · Matthew McClintock

For certain parts and some versions of TZ, TZ will reset the chip when a BARK is triggered even though it was not configured here. So by default let's configure this BARK time as well.

Why isn't TZ configuring the bark time to what it wants? I'm lost why we have to do this for them.

Quoted 7 lines · Stephen Boyd

Quoted 4 lines · Matthew McClintock

For certain parts and some versions of TZ, TZ will reset the chip when a BARK is triggered even though it was not configured here. So by default let's configure this BARK time as well.

Quoted 2 lines

Why isn't TZ configuring the bark time to what it wants? I'm lost why we have to do this for them.

So it was done like this to ensure we had a valid upgrade. The bootloader is using the watchdog to ensure the system is bootable and if not it will revert back to the working images.

Bottom line is, for some versions of TZ out there, if we enable watchdog coming out of boot the bark time is already configured by the boot loader and TZ is configured to intercept this interrupt and do some register saving (for crashdump) and we end up getting a watchdog reset during boot.

It’s even a little more complex, because in order for the TZ to save the registers you need to pad the BITE time a bit higher than the BARK time, but I was leaving that for another day.

Quoted 10 lines

Quoted 3 lines

Why isn't TZ configuring the bark time to what it wants? I'm lost why we have to do this for them.

So it was done like this to ensure we had a valid upgrade. The bootloader is using the watchdog to ensure the system is bootable and if not it will revert back to the working images.

Bottom line is, for some versions of TZ out there, if we enable watchdog coming out of boot the bark time is already configured by the boot loader and TZ is configured to intercept this interrupt and do some register saving (for crashdump) and we end up getting a watchdog reset during boot.

It’s even a little more complex, because in order for the TZ to save the registers you need to pad the BITE time a bit higher than the BARK time, but I was leaving that for another day.

Sounds like an op[timal target for using pretimeout ?

For certain parts and some versions of TZ, TZ will reset the chip when a BARK is triggered even though it was not configured here. So by default let's configure this BARK time as well.

Signed-off-by Matthew McClintock <[email protected]>

---
  drivers/watchdog/qcom-wdt.c | 5 +++++
  1 file changed, 5 insertions(+)

drivers/watchdog/qcom-wdt.c +5 -0

index e46f18d..53f57c3 100644
@@ -22,18 +22,21 @@
  enum wdt_reg {
  	WDT_RST,
  	WDT_EN,
+	WDT_BARK_TIME,
  	WDT_BITE_TIME,
  };
 
  static const u32 reg_offset_data_apcs_tmr[] = {
  	[WDT_RST] = 0x38,
  	[WDT_EN] = 0x40,
+	[WDT_BARK_TIME] = 0x4C,
  	[WDT_BITE_TIME] = 0x5C,
  };
 
  static const u32 reg_offset_data_kpss[] = {
  	[WDT_RST] = 0x4,
  	[WDT_EN] = 0x8,
+	[WDT_BARK_TIME] = 0x10,
  	[WDT_BITE_TIME] = 0x14,
  };
 

@@ -62,6 +65,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
 
  	writel(0, wdt_addr(wdt, WDT_EN));
  	writel(1, wdt_addr(wdt, WDT_RST));
+	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
  	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
  	writel(1, wdt_addr(wdt, WDT_EN));
  	return 0;

@@ -104,6 +108,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
 
  	writel(0, wdt_addr(wdt, WDT_EN));
  	writel(1, wdt_addr(wdt, WDT_RST));
+	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
  	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
  	writel(1, wdt_addr(wdt, WDT_EN));
 

Update the compatible string to add new device tree binding

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +0 -0

index 60bb2f98..45b37cf 100644

Quoted 14 lines · Matthew McClintock

Update the compatible string to add new device tree binding

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +

1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +0 -0

index 60bb2f98..45b37cf 100644
@@ -6,6 +6,7 @@ Required properties :
 

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt Required properties : · line 9

Quoted 3 lines

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +1 -0

 			"qcom,kpss-timer"
 			"qcom,scss-timer"
+			"qcom,kpss-standalone"

What SoC(s) is this in. Use SoC specific compatible strings please.

Quoted 16 lines · Rob Herring

Quoted 14 lines · Matthew McClintock

Update the compatible string to add new device tree binding

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +

1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +0 -0

index 60bb2f98..45b37cf 100644
@@ -6,6 +6,7 @@ Required properties :
 

Quoted 5 lines

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt Required properties : · line 9

Quoted 3 lines

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +1 -0

                     "qcom,kpss-timer"
                     "qcom,scss-timer"
+                    "qcom,kpss-standalone"

What SoC(s) is this in. Use SoC specific compatible strings please.

So ipq4019 wins the race because we are the first to try to enable watchdog for this block?

qcom,kpss-ipq4019 ?

Quoted 16 lines · Rob Herring

Quoted 14 lines · Matthew McClintock

Update the compatible string to add new device tree binding

CC [email protected]

Signed-off-by Matthew McClintock <[email protected]>

---
Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +

1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +0 -0

index 60bb2f98..45b37cf 100644
@@ -6,6 +6,7 @@ Required properties :
 

Quoted 5 lines

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt Required properties : · line 9

Quoted 3 lines

Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +1 -0

 			"qcom,kpss-timer"
 			"qcom,scss-timer"
+			"qcom,kpss-standalone"

What SoC(s) is this in. Use SoC specific compatible strings please.

So ipq4019 wins the race because we are the first to try to enable watchdog for this block?

qcom,kpss-ipq4019 ?

Quoted 7 lines

Quoted 2 lines

What SoC(s) is this in. Use SoC specific compatible strings please.

So ipq4019 wins the race because we are the first to try to enable watchdog for this block?

qcom,kpss-ipq4019 ?

It is a dedicated watchdog block, isn't it ? "qcom,kpss-ipq4019" would not refer to a specific block. Devicetree maintainers may have a better idea, but it seems to me that there should be 'wdt' or 'watchdog' in the property name.

Add cpufreq driver for ipq4019 SoC. This driver simply instantiates cpufreq-dt.

Signed-off-by Matthew McClintock <[email protected]>

---
 drivers/cpufreq/Kconfig.arm       |  9 +++++++++
 drivers/cpufreq/Makefile          |  1 +
 drivers/cpufreq/ipq4019-cpufreq.c | 35 +++++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100644 drivers/cpufreq/ipq4019-cpufreq.c

Quoted 10 lines · Matthew McClintock

Add cpufreq driver for ipq4019 SoC. This driver simply instantiates cpufreq-dt.

Signed-off-by Matthew McClintock <[email protected]>

---

drivers/cpufreq/Kconfig.arm       |  9 +++++++++
drivers/cpufreq/Makefile          |  1 +
drivers/cpufreq/ipq4019-cpufreq.c | 35 +++++++++++++++++++++++++++++++++++
3 files changed, 45 insertions(+)

create mode 100644 drivers/cpufreq/ipq4019-cpufreq.c

I have just sent a patchset and cc'd you:
"[PATCH 0/3] cpufreq: dt: Create platform device from generic code"

and so this patch may get replaced now.

This adds some operating points for cpu frequeny scaling

Signed-off-by Matthew McClintock <[email protected]>

---

This adds some operating points for cpu frequeny scaling

Signed-off-by Matthew McClintock <[email protected]>