sunxi: Add INITIAL_USB_SCAN_DELAY Kconfig option
Subsystems (3)
PATCH 1/3 sunxi: Add INITIAL_USB_SCAN_DELAY Kconfig option
Some boards have on board usb devices which need longer then the USB spec's 1 second to connect from board powerup. Add a config option which when non 0 adds an extra delay before the first usb bus scan.
--- arch/arm/mach-sunxi/usb_phy.c | 7 +++++++ board/sunxi/Kconfig | 9 +++++++++ 2 files changed, 16 insertions(+)
arch/arm/mach-sunxi/usb_phy.c +7 -0
@@ -85,6 +85,8 @@ static struct sunxi_usb_phy {#endif }; +static int initial_usb_scan_delay =CONFIG_INITIAL_USB_SCAN_DELAY ; +static int get_vbus_gpio (int index) {switch (index) {
@@ -269,6 +271,11 @@ void sunxi_usb_phy_power_on(int index) {struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; +if (initial_usb_scan_delay) { +mdelay (initial_usb_scan_delay); + initial_usb_scan_delay =0 ; + } + phy->power_on_count++;if (phy->power_on_count !=1 )return ;
board/sunxi/Kconfig +9 -0
@@ -312,6 +312,15 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. +config INITIAL_USB_SCAN_DELAY + int "delay initial usb scan by x ms to allow builtin devices to init" + default 0 + ---help--- + Some boards have on board usb devices which need longer then the + USB spec's 1 second to connect from board powerup. Set this config + option to a non 0 value to add an extra delay before the first usb + bus scan. + config USB0_VBUS_PIN string "Vbus enable pin for usb0 (otg)" default ""
Signature · 1 line
2.7.2
PATCH 2/3 sunxi: Set DCDC1 to 3.3V on the Sinovoip BPI M3
This is the value used in the fex file of the manufacturer images, and also the DCDC1 default. Sometimes lower values are used to save battery power, but that does not apply to a SBC.
--- configs/Sinovoip_BPI_M3_defconfig | 1 - 1 file changed, 1 deletion(-)
configs/Sinovoip_BPI_M3_defconfig +0 -1
@@ -12,5 +12,4 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP_DCDC1_VOLT=3000 CONFIG_AXP_DCDC5_VOLT=1200
Signature · 1 line
2.7.2
PATCH 2/3 sunxi: Set DCDC1 to 3.3V on the Sinovoip BPI M3
Quoted 5 lines · Hans de Goede
This is the value used in the fex file of the manufacturer images, and also the DCDC1 default. Sometimes lower values are used to save battery power, but that does not apply to a SBC.
Signed-off-by Hans de Goede <[email protected]>
PATCH 3/3 sunxi: Enable usb ports on the Sinovoip BPI M3
In reply to Hans de GoedeDLDO3 is used to provide Port-D power and PD is used for the usb-hub / sata-5v enable pins. The 2.5V comes from the schematic and matches the factory image fex file.
--- arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 8 ++++++++ configs/Sinovoip_BPI_M3_defconfig | 9 +++++++++ 2 files changed, 17 insertions(+)
arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts +8 -0
@@ -57,8 +57,16 @@ }; }; +&ehci0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usb_otg { + status = "okay"; +};
configs/Sinovoip_BPI_M3_defconfig +9 -0
@@ -5,6 +5,11 @@ CONFIG_DRAM_TYPE=7 CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y +CONFIG_INITIAL_USB_SCAN_DELAY=500 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH11" +CONFIG_USB1_VBUS_PIN="PD24" CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -13,3 +18,7 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_AXP_DCDC5_VOLT=1200 +CONFIG_AXP_DLDO3_VOLT=2500 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_HOST=y +CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
Signature · 1 line
2.7.2
PATCH 3/3 sunxi: Enable usb ports on the Sinovoip BPI M3
Quoted 3 lines · Hans de Goede
DLDO3 is used to provide Port-D power and PD is used for the usb-hub / sata-5v enable pins. The 2.5V comes from the schematic and matches the factory image fex file.
Is the dts update being sync'd from the kernel?
If yes:
Quoted 1 line
Signed-off-by Hans de Goede <[email protected]>
If you also want to mention the kernel sync in the commit message, you can also retain the ack (of course).
PATCH 3/3 sunxi: Enable usb ports on the Sinovoip BPI M3
Hi,
Quoted 6 lines · Ian Campbell
Quoted 3 lines · Hans de Goede
DLDO3 is used to provide Port-D power and PD is used for the usb-hub / sata-5v enable pins. The 2.5V comes from the schematic and matches the factory image fex file.
Is the dts update being sync'd from the kernel?
Erm, no actually, the A83t USB support for the kernel is not entirely ready, so we've some very minimal nodes in u-boot's a83t.dtsi for now, which will get replaced with the real deal when we sync in the future.
The only thing u-boot cares about are controller base address and the compatible string, and there is no discussion about those, which is why I merged ChenYu's .dtsi patches with the minimal nodes, this commit just enables these nodes in the M3 dts.
I do expect the eventual kernel m3.dts changes to be pretty much identical.
Quoted 8 lines
If yes:
Quoted 1 line
Signed-off-by Hans de Goede <[email protected]>Acked-by Ian Campbell <[email protected]>If you also want to mention the kernel sync in the commit message, you can also retain the ack (of course).
Regards,
Hans
PATCH 3/3 sunxi: Enable usb ports on the Sinovoip BPI M3
Quoted 16 lines · Hans de Goede
Hi,
Quoted 7 lines · Ian Campbell
Quoted 4 lines · Hans de Goede
DLDO3 is used to provide Port-D power and PD is used for the usb-hub / sata-5v enable pins. The 2.5V comes from the schematic and matches the factory image fex file.
Is the dts update being sync'd from the kernel?
Erm, no actually, the A83t USB support for the kernel is not entirely ready, so we've some very minimal nodes in u-boot's
a83t.dtsifor now,
which will get replaced with the real deal when we sync in the future.
Quoted 4 lines
The only thing u-boot cares about are controller base address and the compatible string, and there is no discussion about those, which is why I merged ChenYu's .dtsi patches with the minimal nodes, this commit just enables these nodes in the M3 dts.
Ah, ok. Is it worth mentioning that in the commit log for clarity (think of someone doing a resync with the kernel and getting confused by the non-kernel bits)?
Maybe the commit message on the orignal addition makes it unnecessary? If you think that's the case then you can keep my Ack.
Ian.
PATCH 3/3 sunxi: Enable usb ports on the Sinovoip BPI M3
Hi,
Quoted 17 lines · Ian Campbell
Quoted 16 lines · Hans de Goede
Hi,
Quoted 7 lines · Ian Campbell
Quoted 4 lines · Hans de Goede
DLDO3 is used to provide Port-D power and PD is used for the usb-hub / sata-5v enable pins. The 2.5V comes from the schematic and matches the factory image fex file.
Is the dts update being sync'd from the kernel?
Erm, no actually, the A83t USB support for the kernel is not entirely ready, so we've some very minimal nodes in u-boot's
a83t.dtsifor now,
which will get replaced with the real deal when we sync in the future.
Quoted 8 lines
Quoted 4 lines
The only thing u-boot cares about are controller base address and the compatible string, and there is no discussion about those, which is why I merged ChenYu's .dtsi patches with the minimal nodes, this commit just enables these nodes in the M3 dts.
Ah, ok. Is it worth mentioning that in the commit log for clarity (think of someone doing a resync with the kernel and getting confused by the non-kernel bits)?
Ack, I've added the following paragraph to the commit msg now:
"The dts changes are the minimal changes needed for u-boot to pick-up the usb host controllers. The upstream kernel does not (yet) have usb host support."
Regards,
Hans
PATCH 1/3 sunxi: Add INITIAL_USB_SCAN_DELAY Kconfig option
In reply to Hans de GoedeQuoted 1 line · Hans de Goede
Some boards have on board usb devices which need longer then the USB
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^than
(and in the Kconfig too)
Quoted 4 lines
spec's 1 second to connect from board powerup. Add a config option which when non 0 adds an extra delay before the first usb bus scan.
Signed-off-by Hans de Goede <[email protected]>
Apart from that: