Patch "perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere" has been added to the 4.4-stable tree
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This is a note to let you know that I've just added the patch titled
perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
0005-perf-x86-intel-Fix-PEBS-data-source-interpretation-o.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
5e3f4cbd906c178510dccfed1131b007c96255ffMon Sep 17 00:00:00 2001
From: Andi Kleen <[email protected]>
Date: Tue, 1 Mar 2016 14:25:24 -0800
Subject: perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere
From: Andi Kleen <[email protected]>
commit 5e3f4cbd906c178510dccfed1131b007c96255ff upstream.
Jiri reported some time ago that some entries in the PEBS data source table in perf do not agree with the SDM. We investigated and the bits changed for Sandy Bridge, but the SDM was not updated.
perf already implements the bits correctly for Sandy Bridge and later. This patch patches it up for Nehalem and Westmere.
--- arch/x86/kernel/cpu/perf_event.h | 2 ++ arch/x86/kernel/cpu/perf_event_intel.c | 2 ++ arch/x86/kernel/cpu/perf_event_intel_ds.c | 11 ++++++++++- 3 files changed, 14 insertions(+), 1 deletion(-)
arch/x86/kernel/cpu/perf_event.h +2 -0
@@ -908,6 +908,8 @@ void intel_pmu_lbr_init_hsw(void);void intel_pmu_lbr_init_skl (void ); +void intel_pmu_pebs_data_source_nhm (void ); +int intel_pmu_setup_lbr_filter (struct perf_event *event);void intel_pt_interrupt (void );
arch/x86/kernel/cpu/perf_event_intel.c +2 -0
@@ -3336,6 +3336,7 @@ __init int intel_pmu_init(void) intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND ] = X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); +intel_pmu_pebs_data_source_nhm ();x86_add_quirk (intel_nehalem_quirk);pr_cont ("Nehalem events, " );
@@ -3398,6 +3399,7 @@ __init int intel_pmu_init(void) intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND ] = X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); +intel_pmu_pebs_data_source_nhm ();pr_cont ("Westmere events, " );break ;
arch/x86/kernel/cpu/perf_event_intel_ds.c +10 -1
@@ -51,7 +51,8 @@ union intel_x86_pebs_dse {#define OP_LH (P(OP, LOAD) | P(LVL, HIT))#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) -static const u64 pebs_data_source[] = { +/* Version for Sandy Bridge and later */ +static u64 pebs_data_source[] = {P (OP ,LOAD ) |P (LVL ,MISS ) |P (LVL ,L3 ) |P (SNOOP ,NA ),/* 0x00:ukn L3 */ OP_LH |P (LVL ,L1 ) |P (SNOOP ,NONE ),/* 0x01: L1 local */ OP_LH |P (LVL ,LFB ) |P (SNOOP ,NONE ),/* 0x02: LFB hit */
@@ -70,6 +71,14 @@ static const u64 pebs_data_source[] = { OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */ }; +/* Patch up minor differences in the bits */ +void __init intel_pmu_pebs_data_source_nhm (void ) +{ + pebs_data_source[0x05 ] =OP_LH |P (LVL ,L3 ) |P (SNOOP ,HIT ); + pebs_data_source[0x06 ] =OP_LH |P (LVL ,L3 ) |P (SNOOP ,HITM ); + pebs_data_source[0x07 ] =OP_LH |P (LVL ,L3 ) |P (SNOOP ,HITM ); +} +static u64 precise_store_data (u64 status) {union intel_x86_pebs_dse dse;
Patches currently in stable-queue which might be from [email protected] are
queue-4.4/0005-perf-x86-intel-Fix-PEBS-data-source-interpretation-o.patch queue-4.4/x86-apic-fix-suspicious-rcu-usage-in-smp_trace_call_function_interrupt.patch queue-4.4/perf-tools-dont-stop-pmu-parsing-on-alias-parse-error.patch queue-4.4/x86-pci-mark-broadwell-ep-home-agent-pcu-as-having-non-compliant-bars.patch queue-4.4/0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch queue-4.4/pci-disable-io-mem-decoding-for-devices-with-non-compliant-bars.patch