Patch "perf/x86/intel: Use PAGE_SIZE for PEBS buffer size on Core2" has been added to the 4.4-stable tree

This is a note to let you know that I've just added the patch titled

perf/x86/intel: Use PAGE_SIZE for PEBS buffer size on Core2

to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch

and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Jiri Olsa <[email protected]>
Date: Tue, 1 Mar 2016 20:03:52 +0100
Subject: perf/x86/intel: Use PAGE_SIZE for PEBS buffer size on Core2

From: Jiri Olsa <[email protected]>

commit 3135a66b768c5ee84c8a98b21d0330dc1c1234b4 upstream.

Using PAGE_SIZE buffers makes the WRMSR to PERF_GLOBAL_CTRL in intel_pmu_enable_all() mysteriously hang on Core2. As a workaround, we don't do this.

The hard lockup is easily triggered by running 'perf test attr' repeatedly. Most of the time it gets stuck on sample session with small periods.

  # perf test attr -vv
  14: struct perf_event_attr setup                             :
  --- start ---
  ...
    'PERF_TEST_ATTR=/tmp/tmpuEKz3B /usr/bin/perf record -o /tmp/tmpuEKz3B/perf.data -c 123 kill >/dev/null 2>&1' ret 1

---
 arch/x86/kernel/cpu/perf_event.h          |    1 +
 arch/x86/kernel/cpu/perf_event_intel_ds.c |   13 +++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

@@ -591,6 +591,7 @@ struct x86_pmu {
 			pebs_active	:1,
 			pebs_broken	:1;
 	int		pebs_record_size;
+	int		pebs_buffer_size;
 	void		(*drain_pebs)(struct pt_regs *regs);
 	struct event_constraint *pebs_constraints;
 	void		(*pebs_aliases)(struct perf_event *event);

@@ -269,7 +269,7 @@ static int alloc_pebs_buffer(int cpu)
 	if (!x86_pmu.pebs)
 		return 0;
 
-	buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
+	buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
 	if (unlikely(!buffer))
 		return -ENOMEM;
 

@@ -286,7 +286,7 @@ static int alloc_pebs_buffer(int cpu)
 		per_cpu(insn_buffer, cpu) = ibuffer;
 	}
 
-	max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
+	max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
 
 	ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 	ds->pebs_index = ds->pebs_buffer_base;

@@ -1296,6 +1296,7 @@ void __init intel_ds_init(void)
 
 	x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
 	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
+	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
 	if (x86_pmu.pebs) {
 		char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
 		int format = x86_pmu.intel_cap.pebs_format;

@@ -1304,6 +1305,14 @@ void __init intel_ds_init(void)
 		case 0:
 			printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
 			x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
+			/*
+			 * Using >PAGE_SIZE buffers makes the WRMSR to
+			 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
+			 * mysteriously hang on Core2.
+			 *
+			 * As a workaround, we don't do this.
+			 */
+			x86_pmu.pebs_buffer_size = PAGE_SIZE;
 			x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
 			break;
 

Patches currently in stable-queue which might be from [email protected] are

queue-4.4/0003-perf-x86-intel-Fix-PEBS-warning-by-only-restoring-ac.patch queue-4.4/0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch queue-4.4/perf-x86-intel-add-definition-for-pt-pmi-bit.patch queue-4.4/perf-tools-fix-python-extension-build.patch queue-4.4/perf-core-fix-perf_sched_count-derailment.patch queue-4.4/0001-perf-x86-pebs-Add-workaround-for-broken-OVFL-status-.patch