perf/x86/intel: Fix wrong lbr_sel_mask
Subsystems (2)
PATCH 1/1 perf/x86/intel: Fix wrong lbr_sel_mask
From: Kan Liang <[email protected]>
This patch fixes an issue which starts from
'commit b16a5b52eb90 ("perf/x86: Add option to disable reading branch flags/cycles")'. In this patch, lbr_sel_mask is used to mask the lbr_select. But LBR_SEL_MASK doesn't include the bit for LBR_CALL_STACK. So LBR call stack will never be set in lbr_select.
This patch corrects the LBR_SEL_MASK by including all valid bits in LBR_SELECT. Also, the LBR_CALL_STACK bit is different as other bit in LBR_SELECT. It does not operate in suppress mode, so it needs to be specially handled in intel_pmu_setup_hw_lbr_filter.
--- arch/x86/events/intel/lbr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
arch/x86/events/intel/lbr.c +4 -2
@@ -64,7 +64,7 @@ static enum {#define LBR_PLM (LBR_KERNEL | LBR_USER) -#define LBR_SEL_MASK 0x1ff/* valid bits in LBR_SELECT */ +#define LBR_SEL_MASK 0x3ff/* valid bits in LBR_SELECT */ #define LBR_NOT_SUPP -1/* LBR filter not supported */ #define LBR_IGN 0/* ignored */
@@ -621,8 +621,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)* The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate * in suppress mode. So LBR_SELECT should be set to * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) +* But the 10th bit LBR_CALL_STACK does not operate +* in suppress mode. */ - reg->config = mask ^ x86_pmu.lbr_sel_mask; + reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK ); if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) && (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
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2.5.0
tip-bot for Kan Liang
merge bot[tip:perf/core] perf/x86/intel: Fix incorrect lbr_sel_mask value
perf/x86/intel: Fix incorrect lbr_sel_mask value
Commit-ID: cf3beb7c90a8efa16a06b26634cddddc92bb819c Gitweb: http://git.kernel.org/tip/cf3beb7c90a8efa16a06b26634cddddc92bb819c Author: Kan Liang <[email protected]> AuthorDate: Thu, 21 Apr 2016 02:30:10 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 28 Apr 2016 10:32:43 +0200
perf/x86/intel: Fix incorrect lbr_sel_mask value
This patch fixes a bug which was introduced by:
b16a5b52eb90 ("perf/x86: Add option to disable reading branch flags/cycles")
In this patch, lbr_sel_mask is used to mask the lbr_select. But LBR_SEL_MASK doesn't include the bit for LBR_CALL_STACK. So LBR call stack will never be set in lbr_select.
This patch corrects the LBR_SEL_MASK by including all valid bits in LBR_SELECT. Also, the LBR_CALL_STACK bit is different as other bit in LBR_SELECT. It does not operate in suppress mode, so it needs to be specially handled in intel_pmu_setup_hw_lbr_filter.
--- arch/x86/events/intel/lbr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
arch/x86/events/intel/lbr.c +4 -2
@@ -63,7 +63,7 @@ static enum {#define LBR_PLM (LBR_KERNEL | LBR_USER) -#define LBR_SEL_MASK 0x1ff/* valid bits in LBR_SELECT */ +#define LBR_SEL_MASK 0x3ff/* valid bits in LBR_SELECT */ #define LBR_NOT_SUPP -1/* LBR filter not supported */ #define LBR_IGN 0/* ignored */
@@ -610,8 +610,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)* The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate * in suppress mode. So LBR_SELECT should be set to * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) +* But the 10th bit LBR_CALL_STACK does not operate +* in suppress mode. */ - reg->config = mask ^ x86_pmu.lbr_sel_mask; + reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK ); if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) && (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&