irqchip: Support Aspeed IRQ controller
Subsystems (3)
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Joel Stanley
maintainerv2 cover irqchip: Support Aspeed IRQ controller
Hello All,
This adds support for the IRQ controller found in the Aspeed ast2400 and ast2500 BMC SoCs.
It's been tested on the ast2400 in an OpenPower Palmetto system, and on the ast2500-edk developer kit.
V2 has a fix for the compatible string in the device tree bindings.
Cheers,
Joel
Benjamin Herrenschmidt (1):
irqchip: Add irq controller for Aspeed
Joel Stanley (1):
doc/devicetree: Add Aspeed VIC bindings
.../interrupt-controller/aspeed,ast2400-vic.txt | 24 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aspeed-vic.c | 238 +++++++++++++++++++++ 3 files changed, 263 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt create mode 100644 drivers/irqchip/irq-aspeed-vic.c
Signature · 1 line
2.8.1
Joel Stanley
maintainerPATCH v2 1/2 doc/devicetree: Add Aspeed VIC bindings
---
v2:
Fix device tree binding example, thanks Baruch and Arnd for pointing this out
.../interrupt-controller/aspeed,ast2400-vic.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +24 -0
@@ -0,0 +1,24 @@ +Aspeed Vectored Interrupt Controller + +These bindings are for the Aspeed AST2400 interrupt controller register layout. +The SoC has an legacy register layout, but this driver does not support that +mode of operation. + +Required properties: + +- compatible : should be "aspeed,ast2400-vic". + +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- valid-sources : bitmask of valid irq sources + +Example: + + vic: interrupt-controller { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = < 0xffffffff 0x0007ffff>; + reg = <0x1e6c0080 0x80>; + };
Signature · 1 line
2.8.1
Rob Herring
maintainerPATCH v2 1/2 doc/devicetree: Add Aspeed VIC bindings
Quoted 18 lines · Joel Stanley
Signed-off-by Joel Stanley <[email protected]>---
v2:
Fix device tree binding example, thanks Baruch and Arnd for pointing this out.../interrupt-controller/aspeed,ast2400-vic.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txtDocumentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +3
-0@@ -0,0 +1,24 @@ +Aspeed Vectored Interrupt Controller + +These bindings are for the Aspeed AST2400 interrupt controller register layout.
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt line 13
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +10
-0+The SoC has an legacy register layout, but this driver does not support that +mode of operation. + +Required properties: + +- compatible : should be "aspeed,ast2400-vic". + +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1.
No need for level vs. edge flags?
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt line 14
Quoted 1 line
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +1
-0+- valid-sources : bitmask of valid irq sources
Drop this. Either all interrupt controllers need this or none of them do. The valid sources are the ones described in the DT.
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt line 18
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +4
-0+ +Example: + + vic: interrupt-controller {
Needs a unit address.
Quoted 13 lines
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +6
-0+ compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = < 0xffffffff 0x0007ffff>; + reg = <0x1e6c0080 0x80>; + };Signature · 6 lines
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PATCH v2 1/2 doc/devicetree: Add Aspeed VIC bindings
Quoted 5 lines · Rob Herring
Quoted 3 lines
+- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an+? interrupt source. The value shall be 1.
No need for level vs. edge flags?
That's an open question. Most interrupts are fixed. A handful of GPIOs can be configured either way. For now I am relying on uboot setting up the right config for them and I read it back at boot time, but we could make it part of the binding I suppose.
Quoted 4 lines
Quoted 1 line
+- valid-sources : bitmask of valid irq sources
Drop this. Either all interrupt controllers need this or none of? them do. The valid sources are the ones described in the DT.
Looking at the code (I wrote that ages ago), this is only used for:
? - Failing map on an unsupported source, so we could drop it
? - Counting the number of sources in order to optimize the ? ? revmap size allocation. We could unconditionally allocate ? ? 64, I don't see a big deal here.
So yes Joel, feel free to just ditch this.
Quoted 20 lines
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt line 18
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +4
-0+ +Example: + + vic: interrupt-controller {Needs a unit address.
Quoted 13 lines
+????? compatible = "aspeed,ast2400-vic";
+????? interrupt-controller;
+????? #interrupt-cells = <1>;
+????? valid-sources = <0xffffffff0x0007ffff>;
+????? reg = <0x1e6c00800x80>;
+ };
--?
2.8.1
?
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Rob Herring
maintainerPATCH v2 1/2 doc/devicetree: Add Aspeed VIC bindings
Quoted 11 lines · Benjamin Herrenschmidt
Quoted 5 lines · Rob Herring
Quoted 3 lines
+- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1.No need for level vs. edge flags?
That's an open question. Most interrupts are fixed. A handful of GPIOs can be configured either way. For now I am relying on uboot setting up the right config for them and I read it back at boot time, but we could make it part of the binding I suppose.
It is almost standard to just use 2 cells here even if reserved for future use. Especially since the IP block seems to have registers to control that.
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
+- valid-sources : bitmask of valid irq sources
Drop this. Either all interrupt controllers need this or none of them do. The valid sources are the ones described in the DT.
Looking at the code (I wrote that ages ago), this is only used for:
I'm guessing it came from the VIC binding. I never really liked the property, but not enough to worry about it.
Rob
Joel Stanley
maintainerPATCH v2 1/2 doc/devicetree: Add Aspeed VIC bindings
Quoted 9 lines · Rob Herring
Quoted 7 lines · Benjamin Herrenschmidt
Quoted 5 lines · Rob Herring
Quoted 3 lines
+- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1.No need for level vs. edge flags?
Quoted 8 lines
Quoted 4 lines
That's an open question. Most interrupts are fixed. A handful of GPIOs can be configured either way. For now I am relying on uboot setting up the right config for them and I read it back at boot time, but we could make it part of the binding I suppose.
It is almost standard to just use 2 cells here even if reserved for future use. Especially since the IP block seems to have registers to control that.
Yep, makes sense. I've added this to the bindings document.
I was trying to use the second cell in our driver:
static struct irq_domain_ops avic_dom_ops = {
.map = avic_map,
.xlate = irq_domain_xlate_twocell,
}; So we have irq_domain_xlate_twocell to parse the device tree and
grabs the type property from the second cell.
In avic_map we set the irq handler:
if (vic->edge_sources[sidx] & sbit) {
/* TODO: Check aginst type from dt and warn if not edge */
irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
} else {
/* TODO: Check aginst type from dt and warn if not level */
irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
}However, we don't have the type here, so we can't use it to check that we're setting the correct edge/level callback (or use it to set the register in the future if we want to use the device tree to override the bootloader settings).
I had a look at some other drivers and they don't seem to use the dt property when mapping the irq. What am I missing here?
Cheers,
Joel
Rob Herring
maintainerPATCH v2 1/2 doc/devicetree: Add Aspeed VIC bindings
Quoted 41 lines · Joel Stanley
Quoted 9 lines · Rob Herring
Quoted 7 lines · Benjamin Herrenschmidt
Quoted 5 lines · Rob Herring
Quoted 3 lines
+- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1.No need for level vs. edge flags?
Quoted 8 lines
Quoted 4 lines
That's an open question. Most interrupts are fixed. A handful of GPIOs can be configured either way. For now I am relying on uboot setting up the right config for them and I read it back at boot time, but we could make it part of the binding I suppose.
It is almost standard to just use 2 cells here even if reserved for future use. Especially since the IP block seems to have registers to control that.
Yep, makes sense. I've added this to the bindings document.
I was trying to use the second cell in our driver:
static struct irq_domain_ops avic_dom_ops = { .map = avic_map, .xlate = irq_domain_xlate_twocell, };So we have
irq_domain_xlate_twocellto parse the device tree and
grabs the type property from the second cell.In
avic_mapwe set the irq handler:if (vic->edge_sources[sidx] & sbit) { /* TODO: Check aginst type from dt and warn if not edge */ irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq); } else { /* TODO: Check aginst type from dt and warn if not level */ irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq); }
Quoted 7 lines
However, we don't have the type here, so we can't use it to check that we're setting the correct edge/level callback (or use it to set the register in the future if we want to use the device tree to override the bootloader settings).
I had a look at some other drivers and they don't seem to use the dt property when mapping the irq. What am I missing here?
The type will be set by the irqdomain core when the mapping is created and this should result in irq_set_type() being called on your irqchip. The map function doesn't need to deal with type.
Rob
Joel Stanley
maintainerPATCH v2 2/2 irqchip: Add irq controller for Aspeed
In reply to Joel StanleyFrom: Benjamin Herrenschmidt <[email protected]>
--- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aspeed-vic.c | 238 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 239 insertions(+) create mode 100644 drivers/irqchip/irq-aspeed-vic.c
drivers/irqchip/Makefile +1 -0
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o +obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
drivers/irqchip/irq-aspeed-vic.c new file +238 -0
238 lines not on this page · raw message
Signature · 1 line
2.8.1
Joel Stanley
maintainerv3 cover irqchip: Support Aspeed IRQ controller
In reply to Joel StanleyHello All,
This adds support for the IRQ controller found in the Aspeed ast2400 and ast2500 BMC SoCs.
It's been tested on the ast2400 in an OpenPower Palmetto system, and on the ast2500-edk developer kit.
V2 has a fix for the compatible string in the device tree bindings.
V3 drops the valid-sources bitmasks and adds a unit address to the example in the bindings
Cheers,
Joel
Benjamin Herrenschmidt (1):
irqchip: Add irq controller for Aspeed
Joel Stanley (1):
doc/devicetree: Add Aspeed VIC bindings
.../interrupt-controller/aspeed,ast2400-vic.txt | 22 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aspeed-vic.c | 230 +++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt create mode 100644 drivers/irqchip/irq-aspeed-vic.c
Signature · 1 line
2.8.1
Joel Stanley
maintainerPATCH v3 1/2 doc/devicetree: Add Aspeed VIC bindings
--- .../interrupt-controller/aspeed,ast2400-vic.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt new file +22 -0
@@ -0,0 +1,22 @@ +Aspeed Vectored Interrupt Controller + +These bindings are for the Aspeed AST2400 interrupt controller register layout. +The SoC has an legacy register layout, but this driver does not support that +mode of operation. + +Required properties: + +- compatible : should be "aspeed,ast2400-vic". + +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. + +Example: + + vic: interrupt-controller at 1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x1e6c0080 0x80>; + };
Signature · 1 line
2.8.1
Joel Stanley
maintainerPATCH v3 2/2 irqchip: Add irq controller for Aspeed
In reply to Joel StanleyFrom: Benjamin Herrenschmidt <[email protected]>
--- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aspeed-vic.c | 230 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 231 insertions(+) create mode 100644 drivers/irqchip/irq-aspeed-vic.c
drivers/irqchip/Makefile +1 -0
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o +obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
drivers/irqchip/irq-aspeed-vic.c new file +230 -0
230 lines not on this page · raw message
Signature · 1 line
2.8.1
v3 cover irqchip: Support Aspeed IRQ controller
In reply to Joel StanleyHey Joel, Ben,
Quoted 23 lines · Joel Stanley
Hello All,
This adds support for the IRQ controller found in the Aspeed ast2400 and ast2500 BMC SoCs.
It's been tested on the ast2400 in an OpenPower Palmetto system, and on the ast2500-edk developer kit.
V2 has a fix for the compatible string in the device tree bindings.
V3 drops the valid-sources bitmasks and adds a unit address to the example in the bindings
Cheers,
Joel
Benjamin Herrenschmidt (1):
irqchip: Add irq controller for AspeedJoel Stanley (1):
doc/devicetree: Add Aspeed VIC bindings
Quoted 6 lines
.../interrupt-controller/aspeed,ast2400-vic.txt | 22 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aspeed-vic.c | 230 +++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt create mode 100644 drivers/irqchip/irq-aspeed-vic.c
Series applied to irqchip/aspeed. I'll only rebase it if you tell me to. :-)
Should be in -next the next time it gets built.
thx,
Jason.