Patch "drm/i915/bdw: Add missing delay during L3 SQC credit programming" has been added to the 4.4-stable tree

This is a note to let you know that I've just added the patch titled

drm/i915/bdw: Add missing delay during L3 SQC credit programming

to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-i915-bdw-add-missing-delay-during-l3-sqc-credit-programming.patch
and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Imre Deak <[email protected]>
Date: Tue, 3 May 2016 15:54:19 +0300
Subject: drm/i915/bdw: Add missing delay during L3 SQC credit programming
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From: Imre Deak <[email protected]>

commit d6a862fe8c48229ba342648bcd535b2404724603 upstream.

BSpec requires us to wait ~100 clocks before re-enabling clock gating, so make sure we do this.

---
 drivers/gpu/drm/i915/intel_pm.c |    6 ++++++
 1 file changed, 6 insertions(+)

@@ -6620,6 +6620,12 @@ static void broadwell_init_clock_gating(
 	misccpctl = I915_READ(GEN7_MISCCPCTL);
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 	I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+	/*
+	 * Wait at least 100 clocks before re-enabling clock gating. See
+	 * the definition of L3SQCREG1 in BSpec.
+	 */
+	POSTING_READ(GEN8_L3SQCREG1);
+	udelay(1);
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 
 	/*

Patches currently in stable-queue which might be from [email protected] are

queue-4.4/drm-i915-bdw-add-missing-delay-during-l3-sqc-credit-programming.patch