Patch "drm/i915/psr: Try to program link training times correctly" has been added to the 4.5-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
drm/i915/psr: Try to program link training times correctly
to the 4.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-psr-try-to-program-link-training-times-correctly.patch
and it can be found in the queue-4.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
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03b7b5f983091bca17e9c163832fcde56971d7d1Mon Sep 17 00:00:00 2001
From: Daniel Vetter <[email protected]>
Date: Wed, 18 May 2016 18:47:11 +0200
Subject: drm/i915/psr: Try to program link training times correctly
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From: Daniel Vetter <[email protected]>
commit 03b7b5f983091bca17e9c163832fcde56971d7d1 upstream.
The default of 0 is 500us of link training, but that's not enough for some platforms. Decoding this correctly means we're using 2.5ms of link training on these platforms, which fixes flickering issues associated with enabling PSR.
v2: Unbotch the math a bit.
v3: Drop debug hunk.
v4: Improve commit message.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95176
--- drivers/gpu/drm/i915/intel_psr.c | 57 ++++++++++++++++++++++++++++++++------- 1 file changed, 48 insertions(+), 9 deletions(-)
drivers/gpu/drm/i915/intel_psr.c +48 -9
@@ -275,19 +275,58 @@ static void hsw_psr_enable_source(struct* with the 5 or 6 idle patterns. */ uint32_t idle_frames =max (6 , dev_priv->vbt.psr.idle_frames); -uint32_t val =0x0 ; +uint32_t val =EDP_PSR_ENABLE ; + + val |= max_sleep_time <<EDP_PSR_MAX_SLEEP_TIME_SHIFT ; + val |= idle_frames <<EDP_PSR_IDLE_FRAME_SHIFT ;if (IS_HASWELL (dev)) val |=EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES ; -I915_WRITE (EDP_PSR_CTL , val | - max_sleep_time <<EDP_PSR_MAX_SLEEP_TIME_SHIFT | - idle_frames <<EDP_PSR_IDLE_FRAME_SHIFT | -EDP_PSR_ENABLE ); - -if (dev_priv->psr.psr2_support) -I915_WRITE (EDP_PSR2_CTL ,EDP_PSR2_ENABLE | -EDP_SU_TRACK_ENABLE |EDP_PSR2_TP2_TIME_100 ); +if (dev_priv->vbt.psr.tp1_wakeup_time >5 ) + val |= EDP_PSR_TP1_TIME_2500us; +else if (dev_priv->vbt.psr.tp1_wakeup_time >1 ) + val |= EDP_PSR_TP1_TIME_500us; +else if (dev_priv->vbt.psr.tp1_wakeup_time >0 ) + val |= EDP_PSR_TP1_TIME_100us; +else + val |= EDP_PSR_TP1_TIME_0us; + +if (dev_priv->vbt.psr.tp2_tp3_wakeup_time >5 ) + val |= EDP_PSR_TP2_TP3_TIME_2500us; +else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time >1 ) + val |= EDP_PSR_TP2_TP3_TIME_500us; +else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time >0 ) + val |= EDP_PSR_TP2_TP3_TIME_100us; +else + val |= EDP_PSR_TP2_TP3_TIME_0us; + +if (intel_dp_source_supports_hbr2 (intel_dp) && +drm_dp_tps3_supported (intel_dp->dpcd)) + val |=EDP_PSR_TP1_TP3_SEL ; +else + val |=EDP_PSR_TP1_TP2_SEL ; + +I915_WRITE (EDP_PSR_CTL , val); + +if (!dev_priv->psr.psr2_support) +return ; + +/* FIXME: selective update is probably totally broken because it doesn't +* mesh at all with our frontbuffer tracking. And the hw alone isn't +* good enough. */ + val =EDP_PSR2_ENABLE |EDP_SU_TRACK_ENABLE ; + +if (dev_priv->vbt.psr.tp2_tp3_wakeup_time >5 ) + val |=EDP_PSR2_TP2_TIME_2500 ; +else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time >1 ) + val |=EDP_PSR2_TP2_TIME_500 ; +else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time >0 ) + val |=EDP_PSR2_TP2_TIME_100 ; +else + val |=EDP_PSR2_TP2_TIME_50 ; + +I915_WRITE (EDP_PSR2_CTL , val); }static bool intel_psr_match_conditions (struct intel_dp *intel_dp)
Patches currently in stable-queue which might be from [email protected] are
queue-4.5/drm-i915-fix-races-on-fbdev.patch queue-4.5/drm-i915-fbdev-fix-num_connector-references-in-intel_fb_initial_config.patch queue-4.5/drm-i915-psr-try-to-program-link-training-times-correctly.patch queue-4.5/drm-fb_helper-fix-references-to-dev-mode_config.num_connector.patch queue-4.5/drm-atomic-verify-connector-funcs-null-when-clearing-states.patch