arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

PATCH New Chin Liang See 2 participants 8 messages Aug 3, 2016 – Aug 7, 2016

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/socfpga architecture

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Chin Liang See

author

2016-08-03 15:17 UTC #0 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Add base address header file for Stratix10 SoC

Signed-off-by Chin Liang See <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +48 -0

new file mode 100755
index 0000000..411518d
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Signature · 1 line

2.2.2

Marek Vasut

Applied

2016-08-04 05:34 UTC #1 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Quoted 6 lines · Chin Liang See

Add base address header file for Stratix10 SoC
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>

Applied to the 01-arria10 branch , since this patch is useless in mainline as-is .

btw do you ever plan to finish the Arria10 support in mainline ?

Quoted 60 lines

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +48 -0

new file mode 100755
index 0000000..411518d
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Signature · 2 lines

Best regards,
Marek Vasut

Chin Liang See

author

2016-08-04 15:08 UTC #2 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Hi Marek,

Quoted 10 lines · Marek Vasut

Quoted 6 lines · Chin Liang See
Add base address header file for Stratix10 SoC
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
Applied to the 01-arria10 branch , since this patch is useless in mainline as-is .

Cool and thanks. This is the patch for S10 SOCVP and I am validating my development code now.

Can we split this as another branch? Once its working with S10 SOCVP, this shall be part of mainline.

Quoted 3 lines

btw do you ever plan to finish the Arria10 support in mainline ?

Definitely and getting Ley Foon's help for this.

Thanks
Chin Liang

Quoted 65 lines

Quoted 63 lines

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48
++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100755 arch/arm/mach

(quoted diff) +0 -1

-socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +48 -0

new file mode 100755
index 0000000..411518d
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Marek Vasut

2016-08-04 15:27 UTC #3 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Quoted 1 line · Chin Liang See

Hi Marek,

Hi,

Quoted 9 lines · Marek Vasut

Quoted 8 lines · Chin Liang See
Quoted 6 lines
Add base address header file for Stratix10 SoC
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>

Quoted 8 lines

Quoted 2 lines
Applied to the 01-arria10 branch , since this patch is useless in mainline as-is .
Cool and thanks. This is the patch for S10 SOCVP and I am validating my development code now.
Can we split this as another branch? Once its working with S10 SOCVP, this shall be part of mainline.

I can put it into stratix branch, but I don't want to add it into mainline as it's dead code for now.

Quoted 5 lines

Quoted 3 lines
btw do you ever plan to finish the Arria10 support in mainline ?
Definitely and getting Ley Foon's help for this.

Cool.

btw is anyone from Altera (now part of Intel :)) going to ELCE ?

Quoted 68 lines

Thanks
Chin Liang

Quoted 65 lines

Quoted 63 lines

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48
++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100755 arch/arm/mach

(quoted diff) +0 -1

-socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +48 -0

new file mode 100755
index 0000000..411518d
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Signature · 2 lines

Best regards,
Marek Vasut

Chin Liang See

author

2016-08-04 15:32 UTC #4 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Quoted 21 lines · Marek Vasut

Quoted 1 line · Chin Liang See
Hi Marek,
Hi,
Quoted 16 lines · Marek Vasut
Quoted 10 lines · Chin Liang See
Quoted 6 lines
Add base address header file for Stratix10 SoC
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
Applied to the 01-arria10 branch , since this patch is useless in mainline as-is .
Cool and thanks. This is the patch for S10 SOCVP and I am validating my
development code now.

Quoted 6 lines

Quoted 3 lines
Can we split this as another branch? Once its working with S10 SOCVP,
this shall be part of mainline.
I can put it into stratix branch, but I don't want to add it into mainline as it's dead code for now.

Cool and yah, we shall do it once its running on SOCVP. Let us know if you wish to play with it too.

Quoted 10 lines

Quoted 6 lines
Quoted 4 lines
btw do you ever plan to finish the Arria10 support in mainline ?
Definitely and getting Ley Foon's help for this.
Cool.
btw is anyone from Altera (now part of Intel :)) going to ELCE ?

Haha.. u are familiar with the tagline :) While ELCE, not for me. Maybe for Dinh?

Thanks
Chin Liang

Quoted 91 lines

Quoted 89 lines
Thanks
Chin Liang
Quoted 85 lines
Quoted 83 lines
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48
++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100755 arch/arm/mach
(quoted diff) +0 -1
-socfpga/include/mach/base_addr_s10.h
arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +11 -0
new file mode 100755
index 0000000..411518d
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS			0xff80000
0
+#define SOCFPGA_EMAC1_ADDRESS 0xff80200
0
+#define SOCFPGA_EMAC2_ADDRESS 0xff80400
0
+#define SOCFPGA_SDMMC_ADDRESS 0xff80800
0
arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +5 -0
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc0200
0
+#define SOCFPGA_UART1_ADDRESS 0xffc0210
0
arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +8 -0
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc0320
0
+#define SOCFPGA_GPIO1_ADDRESS 0xffc0330
0
arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +3 -0
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd0020
0
+#define SOCFPGA_L4WD0_ADDRESS 0xffd0030
0
+#define SOCFPGA_L4WD0_ADDRESS 0xffd0040
0
+#define SOCFPGA_L4WD0_ADDRESS 0xffd0050
0
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd100
00
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd110
00
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd120
00
arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +4 -0
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda200
0
+#define SOCFPGA_SPIS1_ADDRESS 0xffda300
0
+#define SOCFPGA_SPIM0_ADDRESS 0xffda400
0
+#define SOCFPGA_SPIM1_ADDRESS 0xffda500
0
+#define SOCFPGA_OCRAM_ADDRESS 0xffe0000
0
arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +2 -0
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Marek Vasut

2016-08-04 15:50 UTC #5 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Quoted 26 lines · Chin Liang See

Quoted 25 lines · Marek Vasut
Quoted 1 line · Chin Liang See
Hi Marek,
Hi,
Quoted 19 lines · Marek Vasut
Quoted 10 lines · Chin Liang See
Quoted 6 lines
Add base address header file for Stratix10 SoC
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
Applied to the 01-arria10 branch , since this patch is useless in mainline as-is .
Cool and thanks. This is the patch for S10 SOCVP and I am validating my
development code now.
Can we split this as another branch? Once its working with S10 SOCVP,
this shall be part of mainline.

Quoted 5 lines

Quoted 2 lines
I can put it into stratix branch, but I don't want to add it into mainline as it's dead code for now.
Cool and yah, we shall do it once its running on SOCVP. Let us know if you wish to play with it too.

I have enough stuff to play with for now, is the SoCVP documented somewhere already in case I got bored ?

Quoted 5 lines

Quoted 5 lines
Quoted 5 lines
Quoted 4 lines
btw do you ever plan to finish the Arria10 support in mainline ?

Quoted 7 lines

Quoted 5 lines
Quoted 1 line
Definitely and getting Ley Foon's help for this.
Cool.
btw is anyone from Altera (now part of Intel :)) going to ELCE ?
Haha.. u are familiar with the tagline :) While ELCE, not for me.

That sucks. What about Ley ?

Quoted 1 line

Maybe for Dinh?

I hope so :)

Signature · 2 lines

Best regards,
Marek Vasut

Chin Liang See

author

2016-08-07 13:59 UTC #6 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Quoted 31 lines · Marek Vasut

Quoted 30 lines · Chin Liang See
Quoted 28 lines · Marek Vasut
Quoted 1 line · Chin Liang See
Hi Marek,
Hi,
Quoted 13 lines · Marek Vasut
Quoted 11 lines · Chin Liang See
Quoted 6 lines
Add base address header file for Stratix10 SoC
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
Applied to the 01-arria10 branch , since this patch is useless in
mainline as-is .
Quoted 7 lines
Cool and thanks. This is the patch for S10 SOCVP and I am validating my
development code now.
Can we split this as another branch? Once its working with S10 SOCVP,
this shall be part of mainline.
I can put it into stratix branch, but I don't want to add it into mainline as it's dead code for now.

Quoted 6 lines

Quoted 3 lines
Cool and yah, we shall do it once its running on SOCVP. Let us know if
you wish to play with it too.
I have enough stuff to play with for now, is the SoCVP documented somewhere already in case I got bored ?

A good source of reference is located at
https://www.altera.com/en_US/pdfs/literature/ug/ug-s10-vp.pdf

Have fun :)
Chin Liang

Marek Vasut

2016-08-07 20:20 UTC #7 lore raw

PATCH 1/1 arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Quoted 36 lines · Chin Liang See

Quoted 35 lines · Marek Vasut
Quoted 33 lines · Chin Liang See
Quoted 22 lines · Marek Vasut
Quoted 1 line · Chin Liang See
Hi Marek,
Hi,
Quoted 17 lines · Marek Vasut
Quoted 11 lines · Chin Liang See
Quoted 6 lines
Add base address header file for Stratix10 SoC
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
Applied to the 01-arria10 branch , since this patch is useless in
mainline as-is .
Cool and thanks. This is the patch for S10 SOCVP and I am validating my
development code now.
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Can we split this as another branch? Once its working with S10 SOCVP,
this shall be part of mainline.
I can put it into stratix branch, but I don't want to add it into mainline as it's dead code for now.
Cool and yah, we shall do it once its running on SOCVP. Let us know if
you wish to play with it too.

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I have enough stuff to play with for now, is the SoCVP documented somewhere already in case I got bored ?
A good source of reference is located at
https://www.altera.com/en_US/pdfs/literature/ug/ug-s10-vp.pdf

Thanks. The whole text looks like it requires windows (?) to run the executables (.exe) files and also shell (to run the .sh files). Oh dear. It seems the software is also pretty up to date, 2014 was a good year :)

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Best regards,
Marek Vasut