Patch "EDAC: Correct channel count limit" has been added to the 4.4-stable tree
Subsystems (2)
This is a note to let you know that I've just added the patch titled
EDAC: Correct channel count limit
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
edac-correct-channel-count-limit.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
bba142957e04c400440d2df83c1b3b2dfc42e220Mon Sep 17 00:00:00 2001
From: Borislav Petkov <[email protected]>
Date: Fri, 10 Jun 2016 10:28:38 +0200
Subject: EDAC: Correct channel count limit
From: Borislav Petkov <[email protected]>
commit bba142957e04c400440d2df83c1b3b2dfc42e220 upstream.
c44696fff04f ("EDAC: Remove arbitrary limit on number of channels") lifted the arbitrary limit on memory controller channels in EDAC. However, the dynamic channel attributes dynamic_csrow_dimm_attr and dynamic_csrow_ce_count_attr remained 6.
This wasn't a problem except channels 6 and 7 weren't visible in sysfs on machines with more than 6 channels after the conversion to static attr groups with
2c1946b6d629 ("EDAC: Use static attribute groups for managing sysfs entries")
[ without that, we're exploding in edac_create_sysfs_mci_device()
because we're dereferencing out of the bounds of the dynamic_csrow_dimm_attr array. ]
Add attributes for channels 6 and 7 along with a guard for the future, should more channels be required and/or to sanity check for misconfigured machines.
We still need to check against the number of channels present on the MC first, as Thor reported.
--- drivers/edac/edac_mc_sysfs.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)
drivers/edac/edac_mc_sysfs.c +19 -1
@@ -313,7 +313,6 @@ static struct device_type csrow_attr_typ* possible dynamic channel DIMM Label attribute files * */ -DEVICE_CHANNEL (ch0_dimm_label,S_IRUGO |S_IWUSR , channel_dimm_label_show, channel_dimm_label_store,0 ); DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
@@ -326,6 +325,10 @@ DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | channel_dimm_label_show, channel_dimm_label_store, 4);DEVICE_CHANNEL (ch5_dimm_label,S_IRUGO |S_IWUSR , channel_dimm_label_show, channel_dimm_label_store,5 ); +DEVICE_CHANNEL (ch6_dimm_label,S_IRUGO |S_IWUSR , + channel_dimm_label_show, channel_dimm_label_store,6 ); +DEVICE_CHANNEL (ch7_dimm_label,S_IRUGO |S_IWUSR , + channel_dimm_label_show, channel_dimm_label_store,7 );/* Total possible dynamic DIMM Label attribute file table */ static struct attribute *dynamic_csrow_dimm_attr[] = {
@@ -335,6 +338,8 @@ static struct attribute *dynamic_csrow_d &dev_attr_legacy_ch3_dimm_label.attr.attr, &dev_attr_legacy_ch4_dimm_label.attr.attr, &dev_attr_legacy_ch5_dimm_label.attr.attr, + &dev_attr_legacy_ch6_dimm_label.attr.attr, + &dev_attr_legacy_ch7_dimm_label.attr.attr, NULL };
@@ -351,6 +356,10 @@ DEVICE_CHANNEL(ch4_ce_count, S_IRUGO, channel_ce_count_show, NULL, 4);DEVICE_CHANNEL (ch5_ce_count,S_IRUGO , channel_ce_count_show,NULL ,5 ); +DEVICE_CHANNEL (ch6_ce_count,S_IRUGO , + channel_ce_count_show,NULL ,6 ); +DEVICE_CHANNEL (ch7_ce_count,S_IRUGO , + channel_ce_count_show,NULL ,7 );/* Total possible dynamic ce_count attribute file table */ static struct attribute *dynamic_csrow_ce_count_attr[] = {
@@ -360,6 +369,8 @@ static struct attribute *dynamic_csrow_c &dev_attr_legacy_ch3_ce_count.attr.attr, &dev_attr_legacy_ch4_ce_count.attr.attr, &dev_attr_legacy_ch5_ce_count.attr.attr, + &dev_attr_legacy_ch6_ce_count.attr.attr, + &dev_attr_legacy_ch7_ce_count.attr.attr, NULL };
@@ -371,9 +382,16 @@ static umode_t csrow_dev_is_visible(struif (idx >= csrow->nr_channels)return 0 ; + +if (idx >=ARRAY_SIZE (dynamic_csrow_ce_count_attr) -1 ) { +WARN_ONCE (1 ,"idx: %d\n" , idx); +return 0 ; + } +/* Only expose populated DIMMs */ if (!csrow->channels[idx]->dimm->nr_pages)return 0 ; +return attr->mode; }
Patches currently in stable-queue which might be from [email protected] are
queue-4.4/edac-correct-channel-count-limit.patch