Patch "MIPS: mm: Fix definition of R6 cache instruction" has been added to the 4.4-stable tree

This is a note to let you know that I've just added the patch titled

MIPS: mm: Fix definition of R6 cache instruction

to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
mips-mm-fix-definition-of-r6-cache-instruction.patch
and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Matt Redfearn <[email protected]>
Date: Tue, 14 Jun 2016 14:59:38 +0100
Subject: MIPS: mm: Fix definition of R6 cache instruction

From: Matt Redfearn <[email protected]>

commit 4f53989b0652ffe2605221c81ca8ffcfc90aed2a upstream.

Commit a168b8f1cde6 ("MIPS: mm: Add MIPS R6 instruction encodings") added an incorrect definition of the redefined MIPSr6 cache instruction.

Executing any kernel code including this instuction results in a reserved instruction exception and kernel panic.

Fix the instruction definition.

Patchwork: https://patchwork.linux-mips.org/patch/13663/

---
 arch/mips/mm/uasm-mips.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -65,7 +65,7 @@ static struct insn insn_table[] = {
 #ifndef CONFIG_CPU_MIPSR6
 	{ insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 #else
-	{ insn_cache,  M6(cache_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9 },
+	{ insn_cache,  M6(spec3_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9 },
 #endif
 	{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
 	{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },

Patches currently in stable-queue which might be from [email protected] are

queue-4.4/mips-mm-fix-definition-of-r6-cache-instruction.patch