mx6: ddr: Allow changing REFSEL and REFR fields

PATCH New Fabio Estevam 3 participants 8 messages Aug 29, 2016 – Sep 6, 2016 Arm (32-bit)

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Fabio Estevam

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2016-08-29 23:37 UTC #0 lore raw

PATCH v4 1/4 mx6: ddr: Allow changing REFSEL and REFR fields

From: Fabio Estevam <[email protected]>

Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v3:
- Fix the logic for setting refsel/refr registers (Eric)

 arch/arm/cpu/armv7/mx6/ddr.c                      | 6 ++----
 arch/arm/include/asm/arch-mx6/mx6-ddr.h           | 2 ++
 board/bachmann/ot1200/ot1200_spl.c                | 2 ++
 board/barco/platinum/spl_picon.c                  | 2 ++
 board/barco/platinum/spl_titanium.c               | 2 ++
 board/ccv/xpress/spl.c                            | 2 ++
 board/compulab/cm_fx6/spl.c                       | 4 ++++
 board/congatec/cgtqmx6eval/cgtqmx6eval.c          | 2 ++
 board/el/el6x/el6x.c                              | 2 ++
 board/freescale/mx6sabresd/mx6sabresd.c           | 2 ++
 board/freescale/mx6slevk/mx6slevk.c               | 2 ++
 board/freescale/mx6sxsabresd/mx6sxsabresd.c       | 2 ++
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++++
 board/gateworks/gw_ventana/gw_ventana_spl.c       | 2 ++
 board/kosagi/novena/novena_spl.c                  | 2 ++
 board/phytec/pcm058/pcm058.c                      | 2 ++
 board/solidrun/mx6cuboxi/mx6cuboxi.c              | 2 ++
 board/udoo/udoo_spl.c                             | 2 ++
 board/wandboard/spl.c                             | 6 ++++++
 19 files changed, 46 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/mx6/ddr.c +2 -4

index f151eec..7beb7ea 100644
@@ -1166,8 +1166,7 @@ void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc0->mpzqhwctrl = val;
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
-		       (3 << 11);  /* REFR: Refresh Rate - 4 refreshes */
+	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
 
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;

@@ -1472,8 +1471,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mpzqhwctrl, val);
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
-		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
+	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
 
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;

arch/arm/include/asm/arch-mx6/mx6-ddr.h +2 -0

index 12c30d2..9922409 100644
@@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo {
 	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
 	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 	u8 ddr_type;	/* DDR type: DDR3(0) or LPDDR2(1) */
+	u8 refsel;	/* REF_SEL field of register MDREF */
+	u8 refr;	/* REFR field of register MDREF */
 };
 
 /*

board/bachmann/ot1200/ot1200_spl.c +2 -0

index f651a40..9d28da4 100644
@@ -85,6 +85,8 @@ static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
 	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 /* MT41K128M16JT-125 */

board/barco/platinum/spl_picon.c +2 -0

index 098542f..97a861f 100644
@@ -138,6 +138,8 @@ static void spl_dram_init(int width)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7, 	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);

board/barco/platinum/spl_titanium.c +2 -0

index a3a4255..d1ba85a 100644
@@ -141,6 +141,8 @@ static void spl_dram_init(int width)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,		/* Refresh cycles at 32KHz */
+		.refr = 7,		/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);

board/ccv/xpress/spl.c +2 -0

index d15b842..bea837d 100644
@@ -60,6 +60,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {

board/compulab/cm_fx6/spl.c +4 -0

index d8328fd..9442d09 100644
@@ -107,6 +107,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {

@@ -174,6 +176,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {

board/congatec/cgtqmx6eval/cgtqmx6eval.c +2 -0

index 3fbd3d2..a4a6029 100644
@@ -1037,6 +1037,8 @@ static void spl_dram_init(int width)
 		.bi_on = 1,
 		.sde_to_rst = 0x0d,
 		.rst_to_cke = 0x20,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {

board/el/el6x/el6x.c +2 -0

index 3b0fb32..7856b84 100644
@@ -604,6 +604,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);

board/freescale/mx6sabresd/mx6sabresd.c +2 -0

index 0cf6809..f836ecb 100644
@@ -854,6 +854,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	if (is_mx6dqp()) {

board/freescale/mx6slevk/mx6slevk.c +2 -0

index f978e50..96c0e8c 100644
@@ -494,6 +494,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
 		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 		.ddr_type = DDR_TYPE_LPDDR2,
+		.refsel = 0,	/* Refresh cycles at 64KHz */
+		.refr = 3,	/* 4 refresh commands per refresh cycle */
 	};
 	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);

board/freescale/mx6sxsabresd/mx6sxsabresd.c +2 -0

index 8d95c51..965e511 100644
@@ -637,6 +637,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +4 -0

index c213861..5e39108 100644
@@ -766,6 +766,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0,    /* LPDDR2 does not need this field */
 	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 	.ddr_type = DDR_TYPE_LPDDR2,
+	.refsel = 0,	/* Refresh cycles at 64KHz */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 #else

@@ -804,6 +806,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {

board/gateworks/gw_ventana/gw_ventana_spl.c +2 -0

index e7f699a..b610e06 100644
@@ -394,6 +394,8 @@ static void spl_dram_init(int width, int size_mb, int board_model)
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	/*

board/kosagi/novena/novena_spl.c +2 -0

index f779bb4..92c61ae 100644
@@ -520,6 +520,8 @@ static struct mx6_ddr_sysinfo novena_ddr_info = {
 	.bi_on		= 1,	/* Bank interleaving enabled */
 	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg elpida_4gib_1600 = {

board/phytec/pcm058/pcm058.c +2 -0

index 0ba4a2e..4e2122f 100644
@@ -521,6 +521,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);

board/solidrun/mx6cuboxi/mx6cuboxi.c +2 -0

index cafa348..3a1ce24 100644
@@ -605,6 +605,8 @@ static void spl_dram_init(int width)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	if (is_mx6dq())

board/udoo/udoo_spl.c +2 -0

index a1154ed..592e69b 100644
@@ -193,6 +193,8 @@ static struct mx6_ddr_sysinfo mem_qdl = {
 	.mif3_mode = 3,
 	.rst_to_cke = 0x23,
 	.sde_to_rst = 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static void ccgr_init(void)

board/wandboard/spl.c +6 -0

index 77afae7..085095c 100644
@@ -187,6 +187,8 @@ static struct mx6_ddr_sysinfo mem_q = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {

@@ -228,6 +230,8 @@ static struct mx6_ddr_sysinfo mem_dl = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 /* DDR 32bit 512MB */

@@ -245,6 +249,8 @@ static struct mx6_ddr_sysinfo mem_s = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static void ccgr_init(void)

Signature · 1 line

1.9.1

Fabio Estevam

author

2016-08-29 23:37 UTC #1 lore raw

PATCH v4 2/4 mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang

From: Fabio Estevam <[email protected]>

When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk, we observe a hang when going into the lowest operational point of cpufreq.

This hang issue does not happen on the NXP U-Boot version.

After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting:

DATA 4 0x021B0020 0x00000800

,which means:

REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes

So adjust the MDREF initialization for mx6ul_evk accordingly to fix the kernel hang issue at low bus frequency.

Reported-by Eric Nelson <[email protected]>

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v3:
- Just adapt due to previous patch

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +2 -2

index 5e39108..2ca0921 100644
@@ -806,8 +806,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	.ddr_type = DDR_TYPE_DDR3,
-	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refsel = 0,	/* Refresh cycles at 64KHz */
+	.refr = 1,	/* 2 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {

Signature · 1 line

1.9.1

Eric Nelson

2016-08-30 00:35 UTC #2 lore raw

PATCH v4 2/4 mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang

Hi Fabio,

Quoted 36 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk, we observe a hang when going into the lowest operational point of cpufreq.
This hang issue does not happen on the NXP U-Boot version.
After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting:
DATA 4 0x021B0020 0x00000800
,which means:
REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes
So adjust the MDREF initialization for mx6ul_evk accordingly to fix the kernel hang issue at low bus frequency.
Reported-by Eric Nelson <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
Changes since v3:
- Just adapt due to previous patch
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +0 -0
index 5e39108..2ca0921 100644

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c struct mx6_ddr_sysinfo ddr_sysinfo = { · line 813

Quoted 10 lines

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +2 -2

@@ -806,8 +806,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	.ddr_type = DDR_TYPE_DDR3,
-	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refsel = 0,	/* Refresh cycles at 64KHz */
+	.refr = 1,	/* 2 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {

Reviewed-by Eric Nelson <[email protected]>

Stefano Babic

2016-09-06 08:36 UTC #3 lore raw

PATCH v4 2/4 mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang

In reply to Fabio Estevam

Quoted 18 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk, we observe a hang when going into the lowest operational point of cpufreq.
This hang issue does not happen on the NXP U-Boot version.
After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting:
DATA 4 0x021B0020 0x00000800
,which means:
REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes

Quoted 6 lines

So adjust the MDREF initialization for mx6ul_evk accordingly to fix the kernel hang issue at low bus frequency.
Reported-by Eric Nelson <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---

Applied (all series as fix !) to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Fabio Estevam

author

2016-08-29 23:37 UTC #4 lore raw

PATCH v4 3/4 mx6ul_14x14_evk: Adjust SPL DDR3 settings

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v3:
- None

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +7 -7

index 2ca0921..9243ec5 100644
@@ -779,17 +779,17 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_odt0 = 0x00000030,
 	.dram_odt1 = 0x00000030,
 	.dram_sdba2 = 0x00000000,
-	.dram_sdclk_0 = 0x00000008,
-	.dram_sdqs0 = 0x00000038,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
 	.dram_sdqs1 = 0x00000030,
 	.dram_reset = 0x00000030,
 };
 
 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 = 0x00070007,
-	.p0_mpdgctrl0 = 0x41490145,
-	.p0_mprddlctl = 0x40404546,
-	.p0_mpwrdlctl = 0x4040524D,
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41570155,
+	.p0_mprddlctl = 0x4040474A,
+	.p0_mpwrdlctl = 0x40405550,
 };
 
 struct mx6_ddr_sysinfo ddr_sysinfo = {

@@ -799,7 +799,7 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.cs1_mirror = 0,
 	.rtt_wr = 2,
 	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
-	.walat = 1,		/* Write additional latency */
+	.walat = 0,		/* Write additional latency */
 	.ralat = 5,		/* Read additional latency */
 	.mif3_mode = 3,		/* Command prediction working mode */
 	.bi_on = 1,		/* Bank interleaving enabled */

Signature · 1 line

1.9.1

Eric Nelson

2016-08-30 00:30 UTC #5 lore raw

PATCH v4 3/4 mx6ul_14x14_evk: Adjust SPL DDR3 settings

Hi Fabio,

Quoted 24 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table.
Signed-off-by Fabio Estevam <[email protected]>
---
Changes since v3:
- None
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +1 -2
index 2ca0921..9243ec5 100644
@@ -779,17 +779,17 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_odt0 = 0x00000030,
 	.dram_odt1 = 0x00000030,
 	.dram_sdba2 = 0x00000000,
-	.dram_sdclk_0 = 0x00000008,
-	.dram_sdqs0 = 0x00000038,
+	.dram_sdclk_0 = 0x00000030,

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { · line 792

Quoted 10 lines

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +1 -4

+	.dram_sdqs0 = 0x00000030,
 	.dram_sdqs1 = 0x00000030,
 	.dram_reset = 0x00000030,
 };
 
 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 = 0x00070007,
-	.p0_mpdgctrl0 = 0x41490145,
-	.p0_mprddlctl = 0x40404546,
-	.p0_mpwrdlctl = 0x4040524D,

Hmmm. I don't think I've ever seen a value of zero for dectrl0, but it does match the DCD.

When time permits, I'll try running the DDR stress tool on my EVK and also see what it takes to get the mx6memcal rig to run on the 6UL.

Quoted 9 lines

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +4 -0

+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41570155,
+	.p0_mprddlctl = 0x4040474A,
+	.p0_mpwrdlctl = 0x40405550,
 };
 
 struct mx6_ddr_sysinfo ddr_sysinfo = {

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c struct mx6_ddr_sysinfo ddr_sysinfo = { · line 805

Quoted 8 lines

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +1 -1

@@ -799,7 +799,7 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.cs1_mirror = 0,
 	.rtt_wr = 2,
 	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
-	.walat = 1,		/* Write additional latency */
+	.walat = 0,		/* Write additional latency */
 	.ralat = 5,		/* Read additional latency */
 	.mif3_mode = 3,		/* Command prediction working mode */
 	.bi_on = 1,		/* Bank interleaving enabled */

Reviewed-by Eric Nelson <[email protected]>

Fabio Estevam

author

2016-08-29 23:37 UTC #6 lore raw

PATCH v4 4/4 mx6ul_14x14_ev: Enable the CCGR clocks earlier

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init().

Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD").

Signed-off-by Fabio Estevam <[email protected]>

Reviewed-by Eric Nelson <[email protected]>

Tested-by Eric Nelson <[email protected]>

---
Changes since v3:
- None

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +2 -2

index 9243ec5..51876dc 100644
@@ -846,11 +846,11 @@ static void spl_dram_init(void)
 
 void board_init_f(ulong dummy)
 {
+	ccgr_init();
+
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
-	ccgr_init();
-
 	/* iomux and setup of i2c */
 	board_early_init_f();

Signature · 1 line

1.9.1

Eric Nelson

2016-08-30 00:34 UTC #7 lore raw

PATCH v4 1/4 mx6: ddr: Allow changing REFSEL and REFR fields

In reply to Fabio Estevam

Hi Fabio,

Quoted 345 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v3:
- Fix the logic for setting refsel/refr registers (Eric)

 arch/arm/cpu/armv7/mx6/ddr.c                      | 6 ++----
 arch/arm/include/asm/arch-mx6/mx6-ddr.h           | 2 ++
 board/bachmann/ot1200/ot1200_spl.c                | 2 ++
 board/barco/platinum/spl_picon.c                  | 2 ++
 board/barco/platinum/spl_titanium.c               | 2 ++
 board/ccv/xpress/spl.c                            | 2 ++
 board/compulab/cm_fx6/spl.c                       | 4 ++++
 board/congatec/cgtqmx6eval/cgtqmx6eval.c          | 2 ++
 board/el/el6x/el6x.c                              | 2 ++
 board/freescale/mx6sabresd/mx6sabresd.c           | 2 ++
 board/freescale/mx6slevk/mx6slevk.c               | 2 ++
 board/freescale/mx6sxsabresd/mx6sxsabresd.c       | 2 ++
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++++
 board/gateworks/gw_ventana/gw_ventana_spl.c       | 2 ++
 board/kosagi/novena/novena_spl.c                  | 2 ++
 board/phytec/pcm058/pcm058.c                      | 2 ++
 board/solidrun/mx6cuboxi/mx6cuboxi.c              | 2 ++
 board/udoo/udoo_spl.c                             | 2 ++
 board/wandboard/spl.c                             | 6 ++++++
 19 files changed, 46 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/mx6/ddr.c +2 -4

index f151eec..7beb7ea 100644
@@ -1166,8 +1166,7 @@ void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc0->mpzqhwctrl = val;
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
-		       (3 << 11);  /* REFR: Refresh Rate - 4 refreshes */
+	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
 
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;

@@ -1472,8 +1471,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mpzqhwctrl, val);
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
-		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
+	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
 
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;

arch/arm/include/asm/arch-mx6/mx6-ddr.h +2 -0

index 12c30d2..9922409 100644
@@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo {
 	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
 	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 	u8 ddr_type;	/* DDR type: DDR3(0) or LPDDR2(1) */
+	u8 refsel;	/* REF_SEL field of register MDREF */
+	u8 refr;	/* REFR field of register MDREF */
 };
 
 /*

board/bachmann/ot1200/ot1200_spl.c +2 -0

index f651a40..9d28da4 100644
@@ -85,6 +85,8 @@ static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
 	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 /* MT41K128M16JT-125 */

board/barco/platinum/spl_picon.c +2 -0

index 098542f..97a861f 100644
@@ -138,6 +138,8 @@ static void spl_dram_init(int width)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7, 	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);

board/barco/platinum/spl_titanium.c +2 -0

index a3a4255..d1ba85a 100644
@@ -141,6 +141,8 @@ static void spl_dram_init(int width)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,		/* Refresh cycles at 32KHz */
+		.refr = 7,		/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);

board/ccv/xpress/spl.c +2 -0

index d15b842..bea837d 100644
@@ -60,6 +60,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {

board/compulab/cm_fx6/spl.c +4 -0

index d8328fd..9442d09 100644
@@ -107,6 +107,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {

@@ -174,6 +176,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {

board/congatec/cgtqmx6eval/cgtqmx6eval.c +2 -0

index 3fbd3d2..a4a6029 100644
@@ -1037,6 +1037,8 @@ static void spl_dram_init(int width)
 		.bi_on = 1,
 		.sde_to_rst = 0x0d,
 		.rst_to_cke = 0x20,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {

board/el/el6x/el6x.c +2 -0

index 3b0fb32..7856b84 100644
@@ -604,6 +604,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);

board/freescale/mx6sabresd/mx6sabresd.c +2 -0

index 0cf6809..f836ecb 100644
@@ -854,6 +854,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	if (is_mx6dqp()) {

board/freescale/mx6slevk/mx6slevk.c +2 -0

index f978e50..96c0e8c 100644
@@ -494,6 +494,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
 		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 		.ddr_type = DDR_TYPE_LPDDR2,
+		.refsel = 0,	/* Refresh cycles at 64KHz */
+		.refr = 3,	/* 4 refresh commands per refresh cycle */
 	};
 	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);

board/freescale/mx6sxsabresd/mx6sxsabresd.c +2 -0

index 8d95c51..965e511 100644
@@ -637,6 +637,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +4 -0

index c213861..5e39108 100644
@@ -766,6 +766,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0,    /* LPDDR2 does not need this field */
 	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 	.ddr_type = DDR_TYPE_LPDDR2,
+	.refsel = 0,	/* Refresh cycles at 64KHz */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 #else

@@ -804,6 +806,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {

board/gateworks/gw_ventana/gw_ventana_spl.c +2 -0

index e7f699a..b610e06 100644
@@ -394,6 +394,8 @@ static void spl_dram_init(int width, int size_mb, int board_model)
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	/*

board/kosagi/novena/novena_spl.c +2 -0

index f779bb4..92c61ae 100644
@@ -520,6 +520,8 @@ static struct mx6_ddr_sysinfo novena_ddr_info = {
 	.bi_on		= 1,	/* Bank interleaving enabled */
 	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg elpida_4gib_1600 = {

board/phytec/pcm058/pcm058.c +2 -0

index 0ba4a2e..4e2122f 100644
@@ -521,6 +521,8 @@ static void spl_dram_init(void)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);

board/solidrun/mx6cuboxi/mx6cuboxi.c +2 -0

index cafa348..3a1ce24 100644
@@ -605,6 +605,8 @@ static void spl_dram_init(int width)
 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
 	};
 
 	if (is_mx6dq())

board/udoo/udoo_spl.c +2 -0

index a1154ed..592e69b 100644
@@ -193,6 +193,8 @@ static struct mx6_ddr_sysinfo mem_qdl = {
 	.mif3_mode = 3,
 	.rst_to_cke = 0x23,
 	.sde_to_rst = 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static void ccgr_init(void)

board/wandboard/spl.c +4 -0

index 77afae7..085095c 100644
@@ -187,6 +187,8 @@ static struct mx6_ddr_sysinfo mem_q = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {

@@ -228,6 +230,8 @@ static struct mx6_ddr_sysinfo mem_dl = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 /* DDR 32bit 512MB */

board/wandboard/spl.c static struct mx6_ddr_sysinfo mem_s = { · line 256

Quoted 8 lines

board/wandboard/spl.c +2 -0

@@ -245,6 +249,8 @@ static struct mx6_ddr_sysinfo mem_s = {
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
 };
 
 static void ccgr_init(void)

Reviewed-by Eric Nelson <[email protected]>