aspeed/ast-g5: Added ast_uart.{c, h} files, moved most of the diagnostic message printing to ast-g5.c

PATCH In review [email protected] 2 participants 5 messages Sep 2, 2016 – Sep 9, 2016

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Arm (32-bit) Arm sub-architectures Arm/Aspeed machine support

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2016-09-02 17:58 UTC #0 lore raw

PATCH 1/1 aspeed/ast-g5: Added ast_uart.{c, h} files, moved most of the diagnostic message printing to ast-g5.c

From: Maxim Sloyko <[email protected]>

Set up a stack in SRAM at the beginning of lowlevel_init, which makes it possible to call non-trivial C functions, as well as put diagnostic strings themselves onto the stack.

Several one-char writes to debug uart still remain in platform.S, I figured it's not worth it to make a separate call to c function for each of those.

---
 arch/arm/include/asm/arch-aspeed/ast_uart.h | 142 +++++++++++
 arch/arm/include/asm/arch-aspeed/regs-scu.h |   4 +-
 arch/arm/mach-aspeed/Makefile               |   2 +-
 arch/arm/mach-aspeed/ast_uart.c             |  38 +++
 board/aspeed/ast-g5/ast-g5.c                | 110 ++++++++-
 board/aspeed/ast-g5/platform.S              | 351 +++-------------------------
 6 files changed, 318 insertions(+), 329 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-aspeed/ast_uart.h
 create mode 100644 arch/arm/mach-aspeed/ast_uart.c

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +142 -0

new file mode 100644
index 0000000..ddf1a14
@@ -0,0 +1,142 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ ******************************************************************************/
+
+#ifndef __AST_UART_H
+#define __AST_UART_H
+
+#include <asm/io.h>
+
+#define AST_UART_RBR(uart)      (uart)
+#define AST_UART_THR(uart)      (uart)
+#define AST_UART_IER(uart)      ((uart) + 0x4)
+#define AST_UART_IIR(uart)      ((uart) + 0x8)
+#define AST_UART_FCR(uart)      ((uart) + 0x8)
+#define AST_UART_LCR(uart)      ((uart) + 0xc)
+#define AST_UART_MCR(uart)      ((uart) + 0x10)
+#define AST_UART_LSR(uart)      ((uart) + 0x14)
+#define AST_UART_MSR(uart)      ((uart) + 0x18)
+#define AST_UART_SCR(uart)      ((uart) + 0x1c)
+
+/* These registers can only be written when DLAB = 1*/
+#define AST_UART_DLL(uart)      ((uart))
+#define AST_UART_DLH(uart)      ((uart) + 0x4)
+
+/* Registers' contents */
+
+#define AST_UART_IER_THRE       (1 << 7)
+#define AST_UART_IER_EDSSI      (1 << 3)
+#define AST_UART_IER_ELSI       (1 << 2)
+#define AST_UART_IER_ETBEI      (1 << 1)
+#define AST_UART_IER_ERBFI      (1 << 0)
+
+/* AND this mask with AST_UART_IIR to find out if FIFOs are enabled. */
+#define AST_UART_IIR_FEN_MASK   (3 << 6)
+
+/* Bit0 == 0 means that the interrupt is pending, bits 3:1 identify
+ * interrupt.  These values are defined so that IIR | 0xf would give you the
+ * value for the interrupt. */
+#define AST_UART_IIR_MSC        (0)
+#define AST_UART_IIR_THRE       (1 << 1)
+#define AST_UART_IIR_RDA        (2 << 1)
+#define AST_UART_IIR_RS         (3 << 1)
+#define AST_UART_IIR_CTO        (6 << 1)
+
+/* RX FIFO Interrupt trigger level */
+#define AST_UART_FCR_RXFITL_MASK    (3 << 6)
+/* One byte received */
+#define AST_UART_FCR_RXFITL1    (0)
+/* 4 bytes received */
+#define AST_UART_FCR_RXFITL4    (1 << 6)
+/* 8 bytes received */
+#define AST_UART_FCR_RXFITL8    (2 << 6)
+/* 14 bytes received */
+#define AST_UART_FCR_RXFITL14   (3 << 6)
+
+/* TX FIFO Interrupt trigger level */
+#define AST_UART_FCR_TXFITL_MASK    (3 << 4)
+/* FIFO Empty (0 bytes in FIFO) */
+#define AST_UART_FCR_TXFITL0    (0)
+/* 2 bytes in FIFO */
+#define AST_UART_FCR_TXFITL2    (1 << 4)
+/* FIFO 1/4 full (4 bytes) */
+#define AST_UART_FCR_TXFITLQ    (2 << 4)
+/* FIFO 1/2 full (8 bytes) */
+#define AST_UART_FCR_TXFITLH    (3 << 4)
+
+#define AST_UART_FCR_TXFRST     (1 << 2)
+#define AST_UART_FCR_RXFRST     (1 << 1)
+#define AST_UART_FCR_FEN        (1 << 0)
+
+#define AST_UART_LCR_DLAB       (1 << 7)
+#define AST_UART_LCR_BC         (1 << 6)
+#define AST_UART_LCR_EPS        (1 << 4)
+#define AST_UART_LCR_PEN        (1 << 3)
+#define AST_UART_LCR_STOP       (1 << 2)
+
+/* Number of bits per character */
+#define AST_UART_LCR_BPC_MASK   (3)
+#define AST_UART_LCR_BPC5       (0)
+#define AST_UART_LCR_BPC6       (1)
+#define AST_UART_LCR_BPC7       (2)
+#define AST_UART_LCR_BPC8       (3)
+
+#define AST_UART_MCR_LB         (1 << 4)
+#define AST_UART_MCR_OUT2       (1 << 3)
+#define AST_UART_MCR_OUT1       (1 << 2)
+#define AST_UART_MCR_RTS        (1 << 1)
+#define AST_UART_MCR_DTR        (1 << 0)
+
+#define AST_UART_LSR_ERXF       (1 << 7)
+#define AST_UART_LSR_TEMPTY     (1 << 6)
+#define AST_UART_LSR_THRE       (1 << 5)
+#define AST_UART_LSR_BI         (1 << 4)
+#define AST_UART_LSR_FE         (1 << 3)
+#define AST_UART_LSR_PE         (1 << 2)
+#define AST_UART_LSR_OE         (1 << 1)
+#define AST_UART_LSR_DR         (1 << 0)
+
+#define AST_UART_MSR_NDCD_OUT2  (1 << 7)
+#define AST_UART_MSR_NRI_OUT1   (1 << 6)
+#define AST_UART_MSR_NDSR_NDTR  (1 << 5)
+#define AST_UART_MSR_NCTS_NRTS  (1 << 4)
+#define AST_UART_MSR_DDCD       (1 << 3)
+#define AST_UART_MSR_TERI       (1 << 2)
+#define AST_UART_MSR_DDSR       (1 << 1)
+#define AST_UART_MSR_DCTS       (1 << 0)
+
+#define AST_UART_FIFO_SIZE      (16)
+
+#define ast_uart_wait_txempty(uart) while(!(readl(AST_UART_LSR((uart))) & AST_UART_LSR_TEMPTY))
+#define ast_uart_write(uart, c)     writel((c), AST_UART_THR((uart)))
+#define ast_uart_enable_fifo(uart)  setbits_le32(AST_UART_FCR((uart)), AST_UART_FCR_FEN)
+#define ast_uart_enable_thre_mode(uart) setbits_le32(AST_UART_IER(uart), AST_UART_IER_THRE)
+
+/* In THRE and FIFO mode, wait until there is some space in FIFO */
+#define ast_uart_wait_fifo_ready(uart) while((readl(AST_UART_LSR(uart)) & AST_UART_LSR_THRE))
+
+#define ast_uart_set_bpc(uart, bpc) clrsetbits_le32(AST_UART_LCR((uart)), AST_UART_LCR_BPC_MASK, (bpc))
+
+#define ast_uart_unlock_dlab(uart) setbits_le32(AST_UART_LCR((uart)), AST_UART_LCR_DLAB)
+#define ast_uart_lock_dlab(uart) clrbits_le32(AST_UART_LCR(uart), AST_UART_LCR_DLAB)
+
+/* NOTE: These write functions only work when THRE mode and FIFOs are enabled. */
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t* buffer, uint16_t len);
+void ast_uart_write_string_sync(uint32_t uart, const char* s);
+
+#endif

arch/arm/include/asm/arch-aspeed/regs-scu.h +2 -2

index b89df82..b714fa9 100644
@@ -10,8 +10,8 @@
  *    1. 2012/12/29 Ryan Chen Create
  *
 ********************************************************************************/
-#ifndef __AST_SCU_H
-#define __AST_SCU_H                     1
+#ifndef __AST_REGS_SCU_H
+#define __AST_REGS_SCU_H                     1
 
 #include <asm/arch/aspeed.h>

arch/arm/mach-aspeed/Makefile +1 -1

index d72f62a..3e0b4f7 100644
@@ -11,5 +11,5 @@
 #
 
 
-obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o
+obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o ast_uart.o
 obj-$(CONFIG_AST_SPI_NOR) += flash.o

arch/arm/mach-aspeed/ast_uart.c new file +38 -0

new file mode 100644
index 0000000..1226827
@@ -0,0 +1,38 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ ******************************************************************************/
+
+#include <asm/io.h>
+#include <asm/arch/ast_uart.h>
+
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t *buffer,
+				uint16_t len)
+{
+	for (; len; --len, ++buffer) {
+		ast_uart_wait_fifo_ready(uart);
+		ast_uart_write(uart, *buffer);
+	}
+}
+
+void ast_uart_write_string_sync(uint32_t uart, const char *s)
+{
+	for (; *s; ++s) {
+		ast_uart_wait_fifo_ready(uart);
+		ast_uart_write(uart, *s);
+	}
+}

board/aspeed/ast-g5/ast-g5.c +107 -3

132 lines not on this page · raw message

board/aspeed/ast-g5/platform.S +28 ~~-323~~

423 lines not on this page · raw message

Signature · 1 line

2.8.0.rc3.226.g39d4020

Maxim Sloyko

author

2016-09-07 16:43 UTC #1 lore raw

Ping!

Quoted 849 lines · On Fri, Sep 2, 2016 at 10:58 AM, <[email protected]> wrote:

From: Maxim Sloyko <[email protected]>

Set up a stack in SRAM at the beginning of lowlevel_init, which makes it possible to call non-trivial C functions, as well as put diagnostic strings themselves onto the stack.

Several one-char writes to debug uart still remain in platform.S, I figured it's not worth it to make a separate call to c function for each of those.

---
 arch/arm/include/asm/arch-aspeed/ast_uart.h | 142 +++++++++++
 arch/arm/include/asm/arch-aspeed/regs-scu.h |   4 +-
 arch/arm/mach-aspeed/Makefile               |   2 +-
 arch/arm/mach-aspeed/ast_uart.c             |  38 +++
 board/aspeed/ast-g5/ast-g5.c                | 110 ++++++++-
 board/aspeed/ast-g5/platform.S              | 351
+++-------------------------
 6 files changed, 318 insertions(+), 329 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-aspeed/ast_uart.h
 create mode 100644 arch/arm/mach-aspeed/ast_uart.c

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +1 -0

new file mode 100644
index 0000000..ddf1a14
@@ -0,0 +1,142 @@
+/**********************************************************

*********************
+ * Copyright (C) 2016 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ ************************************************************ ******************/

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +34 -0

+
+#ifndef __AST_UART_H
+#define __AST_UART_H
+
+#include <asm/io.h>
+
+#define AST_UART_RBR(uart)      (uart)
+#define AST_UART_THR(uart)      (uart)
+#define AST_UART_IER(uart)      ((uart) + 0x4)
+#define AST_UART_IIR(uart)      ((uart) + 0x8)
+#define AST_UART_FCR(uart)      ((uart) + 0x8)
+#define AST_UART_LCR(uart)      ((uart) + 0xc)
+#define AST_UART_MCR(uart)      ((uart) + 0x10)
+#define AST_UART_LSR(uart)      ((uart) + 0x14)
+#define AST_UART_MSR(uart)      ((uart) + 0x18)
+#define AST_UART_SCR(uart)      ((uart) + 0x1c)
+
+/* These registers can only be written when DLAB = 1*/
+#define AST_UART_DLL(uart)      ((uart))
+#define AST_UART_DLH(uart)      ((uart) + 0x4)
+
+/* Registers' contents */
+
+#define AST_UART_IER_THRE       (1 << 7)
+#define AST_UART_IER_EDSSI      (1 << 3)
+#define AST_UART_IER_ELSI       (1 << 2)
+#define AST_UART_IER_ETBEI      (1 << 1)
+#define AST_UART_IER_ERBFI      (1 << 0)
+
+/* AND this mask with AST_UART_IIR to find out if FIFOs are enabled. */
+#define AST_UART_IIR_FEN_MASK   (3 << 6)
+
+/* Bit0 == 0 means that the interrupt is pending, bits 3:1 identify
+ * interrupt.  These values are defined so that IIR | 0xf would give you

the
+ * value for the interrupt. */

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +72 -0

+#define AST_UART_IIR_MSC        (0)
+#define AST_UART_IIR_THRE       (1 << 1)
+#define AST_UART_IIR_RDA        (2 << 1)
+#define AST_UART_IIR_RS         (3 << 1)
+#define AST_UART_IIR_CTO        (6 << 1)
+
+/* RX FIFO Interrupt trigger level */
+#define AST_UART_FCR_RXFITL_MASK    (3 << 6)
+/* One byte received */
+#define AST_UART_FCR_RXFITL1    (0)
+/* 4 bytes received */
+#define AST_UART_FCR_RXFITL4    (1 << 6)
+/* 8 bytes received */
+#define AST_UART_FCR_RXFITL8    (2 << 6)
+/* 14 bytes received */
+#define AST_UART_FCR_RXFITL14   (3 << 6)
+
+/* TX FIFO Interrupt trigger level */
+#define AST_UART_FCR_TXFITL_MASK    (3 << 4)
+/* FIFO Empty (0 bytes in FIFO) */
+#define AST_UART_FCR_TXFITL0    (0)
+/* 2 bytes in FIFO */
+#define AST_UART_FCR_TXFITL2    (1 << 4)
+/* FIFO 1/4 full (4 bytes) */
+#define AST_UART_FCR_TXFITLQ    (2 << 4)
+/* FIFO 1/2 full (8 bytes) */
+#define AST_UART_FCR_TXFITLH    (3 << 4)
+
+#define AST_UART_FCR_TXFRST     (1 << 2)
+#define AST_UART_FCR_RXFRST     (1 << 1)
+#define AST_UART_FCR_FEN        (1 << 0)
+
+#define AST_UART_LCR_DLAB       (1 << 7)
+#define AST_UART_LCR_BC         (1 << 6)
+#define AST_UART_LCR_EPS        (1 << 4)
+#define AST_UART_LCR_PEN        (1 << 3)
+#define AST_UART_LCR_STOP       (1 << 2)
+
+/* Number of bits per character */
+#define AST_UART_LCR_BPC_MASK   (3)
+#define AST_UART_LCR_BPC5       (0)
+#define AST_UART_LCR_BPC6       (1)
+#define AST_UART_LCR_BPC7       (2)
+#define AST_UART_LCR_BPC8       (3)
+
+#define AST_UART_MCR_LB         (1 << 4)
+#define AST_UART_MCR_OUT2       (1 << 3)
+#define AST_UART_MCR_OUT1       (1 << 2)
+#define AST_UART_MCR_RTS        (1 << 1)
+#define AST_UART_MCR_DTR        (1 << 0)
+
+#define AST_UART_LSR_ERXF       (1 << 7)
+#define AST_UART_LSR_TEMPTY     (1 << 6)
+#define AST_UART_LSR_THRE       (1 << 5)
+#define AST_UART_LSR_BI         (1 << 4)
+#define AST_UART_LSR_FE         (1 << 3)
+#define AST_UART_LSR_PE         (1 << 2)
+#define AST_UART_LSR_OE         (1 << 1)
+#define AST_UART_LSR_DR         (1 << 0)
+
+#define AST_UART_MSR_NDCD_OUT2  (1 << 7)
+#define AST_UART_MSR_NRI_OUT1   (1 << 6)
+#define AST_UART_MSR_NDSR_NDTR  (1 << 5)
+#define AST_UART_MSR_NCTS_NRTS  (1 << 4)
+#define AST_UART_MSR_DDCD       (1 << 3)
+#define AST_UART_MSR_TERI       (1 << 2)
+#define AST_UART_MSR_DDSR       (1 << 1)
+#define AST_UART_MSR_DCTS       (1 << 0)
+
+#define AST_UART_FIFO_SIZE      (16)
+
+#define ast_uart_wait_txempty(uart) while(!(readl(AST_UART_LSR((uart)))

& AST_UART_LSR_TEMPTY))

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0

+#define ast_uart_write(uart, c)     writel((c), AST_UART_THR((uart)))
+#define ast_uart_enable_fifo(uart)  setbits_le32(AST_UART_FCR((uart)),

AST_UART_FCR_FEN)
+#define ast_uart_enable_thre_mode(uart) setbits_le32(AST_UART_IER(uart), AST_UART_IER_THRE)

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +3 -0

+
+/* In THRE and FIFO mode, wait until there is some space in FIFO */
+#define ast_uart_wait_fifo_ready(uart) while((readl(AST_UART_LSR(uart))

& AST_UART_LSR_THRE))

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0

+
+#define ast_uart_set_bpc(uart, bpc) clrsetbits_le32(AST_UART_LCR((uart)),

AST_UART_LCR_BPC_MASK, (bpc))

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0

+
+#define ast_uart_unlock_dlab(uart) setbits_le32(AST_UART_LCR((uart)),

AST_UART_LCR_DLAB)
+#define ast_uart_lock_dlab(uart) clrbits_le32(AST_UART_LCR(uart), AST_UART_LCR_DLAB)

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0

+
+/* NOTE: These write functions only work when THRE mode and FIFOs are

enabled. */
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t* buffer, uint16_t len);

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +3 -0

+void ast_uart_write_string_sync(uint32_t uart, const char* s);
+
+#endif

arch/arm/include/asm/arch-aspeed/regs-scu.h +2 -2

index b89df82..b714fa9 100644
@@ -10,8 +10,8 @@
  *    1. 2012/12/29 Ryan Chen Create
  *
 ************************************************************
 ********************/
-#ifndef __AST_SCU_H
-#define __AST_SCU_H                     1
+#ifndef __AST_REGS_SCU_H
+#define __AST_REGS_SCU_H                     1
 
 #include <asm/arch/aspeed.h>

arch/arm/mach-aspeed/Makefile +1 -1

index d72f62a..3e0b4f7 100644
@@ -11,5 +11,5 @@
 #
 
 
-obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o
+obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o

ast_uart.o
obj-$(CONFIG_AST_SPI_NOR) += flash.o

arch/arm/mach-aspeed/ast_ renamed from arch/arm/mach-aspeed/ast_uart.c +0 -0

uart.c
new file mode 100644
index 0000000..1226827

arch/arm/mach-aspeed/ast_uart.c new file +1 -0

@@ -0,0 +1,38 @@
+/**********************************************************

arch/arm/mach-aspeed/ast_uart.c new file +20 -0

+
+#include <asm/io.h>
+#include <asm/arch/ast_uart.h>
+
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t *buffer,
+                               uint16_t len)
+{
+       for (; len; --len, ++buffer) {
+               ast_uart_wait_fifo_ready(uart);
+               ast_uart_write(uart, *buffer);
+       }
+}
+
+void ast_uart_write_string_sync(uint32_t uart, const char *s)
+{
+       for (; *s; ++s) {
+               ast_uart_wait_fifo_ready(uart);
+               ast_uart_write(uart, *s);
+       }
+}

board/aspeed/ast-g5/ast-g5.c +64 -2

index 81ea88a..b0b8535 100644
@@ -35,16 +35,21 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/arch/ast_scu.h>
+#include <asm/arch/ast_g5_platform.h>
 #include <asm/arch/ast-sdmc.h>
+#include <asm/arch/ast_scu.h>
+#include <asm/arch/ast_uart.h>
+#include <asm/arch/regs-scu.h>
 #include <asm/io.h>
 
+#define AST_DEBUG_UART      (0x1e784000)
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
 void show_boot_progress(int progress)
 {
-    printf("Boot reached stage %d\n", progress);
+       printf("Boot reached stage %d\n", progress);
 }
 #endif

@@ -66,9 +71,108 @@ int dram_init(void)
        return 0;
 }
 
+/* assumes digit < 16 */
+static inline char hex_digit(uint8_t digit)
+{
+       if (digit < 10) {
+               return '0' + digit;
+       } else {
+               return 'a' + (digit - 10);
+       }
+}
+
+static inline void format_u8_hex(char *dst, uint8_t value)
+{
+       *dst = hex_digit(value >> 4);
+       *(dst + 1) = hex_digit(value & 0xf);
+}
+
+static inline void debug_uart_print(const char *s)
+{
+       ast_uart_write_string_sync(AST_DEBUG_UART, s);
+}
+
+void debug_print_ddr_version(uint8_t version)
+{
+       char message[8] = "-DDR_\r\n";
+       message[4] = '0' + version;
+       debug_uart_print(message);
+}
+
+void debug_print_dram_init_message(uint8_t version)
+{
+       char message[16] = "\r\nDRAM Init-V__";
+       char *version_dst = message + 13;
+       format_u8_hex(version_dst, version);
+       debug_uart_print(message);
+}
+
+void debug_print_dram_size(char size)
+{
+       char message[6] = "-_Gb-";
+       message[1] = size;
+       debug_uart_print(message);
+}
+
+void debug_print_ddr_status(bool done)
+{
+       if (done) {
+               debug_uart_print("Done\r\n");
+       } else {
+               debug_uart_print("Fail\r\n");
+       }
+}
+
+static inline void format_phy_timing(char *dst, uint8_t value)
+{
+       /* This is adopted from platforms.S file by Aspeed.
+        * They read memory address (which is not mentioned in the data
 sheet)
+        * and then divide byte value by 510 and print 4 digits after the

dot.

board/aspeed/ast-g5/ast-g5.c +12 -0

+        */
+       uint32_t timing_value = value * 1000 / 51;
+       for (int index = 3; index >= 0 && timing_value > 0; --index) {
+               uint8_t digit = timing_value % 10;
+               timing_value /= 10;
+               dst[index] = '0' + digit;
+       }
+}
+
+void debug_print_ddr_phy_timing(uint16_t margin)
+{
+       char message[46] = "Read margin DL:0.0000/0.0000 CK (min:

0.35)\r\n";

board/aspeed/ast-g5/ast-g5.c +31 -1

+       format_phy_timing(message + 17, margin & 0xff);
+       format_phy_timing(message + 24, (margin >> 8) & 0xff);
+       debug_uart_print(message);
+}
+
+static void init_uart_for_debug(uint32_t uart_base)
+{
+       ast_uart_set_bpc(uart_base, AST_UART_LCR_BPC8);
+       ast_uart_unlock_dlab(uart_base);
+       const uint32_t uart_clk_mul =
+           readl(AST_SCU_BASE + AST_SCU_MISC1_CTRL) & (1 << 12) ? 1 : 13;
+#ifdef CONFIG_DRAM_UART_38400
+       const uint32_t br_base = 3 * uart_clk_mul;
+#else
+       const uint32_t br_base = 1 * uart_clk_mul;
+#endif
+       writel(br_base, AST_UART_DLL(uart_base));
+       writel(0, AST_UART_DLH(uart_base));
+
+       /* Lock DLAB */
+       ast_uart_lock_dlab(uart_base);
+       ast_uart_enable_fifo(uart_base);
+       ast_uart_enable_thre_mode(uart_base);
+}
+
+void init_debug_uart(void)
+{
+       init_uart_for_debug(AST_DEBUG_UART);
+}
+
 #ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bd)
 {
-        return ftgmac100_initialize(bd);
+       return ftgmac100_initialize(bd);
 }
 #endif

board/aspeed/ast-g5/ renamed from board/aspeed/ast-g5/platform.S +0 -0

platform.S
index c810f44..a33afee 100644

board/aspeed/ast-g5/platform.S +0 -1

@@ -78,7 +78,6 @@
 #include <version.h>
 
 /***********************************************************
 *******************
-  r4 : return program counter
   r5 : DDR speed timing table base address
   Free registers:

   r0, r1, r2, r3, r6, r7, r8, r9, r10, r11

board/aspeed/ast-g5/platform.S +12 -1

@@ -104,6 +103,9 @@
 #define ASTMMC_REGIDX_RFC    0x3C
 #define ASTMMC_REGIDX_PLL    0x40
 
+#define AST_SRAM_END  0x1e728ffc
+
+
 TIME_TABLE_DDR3_1333:
     .word   0x53503C37       @ 0x010
     .word   0xF858D47F       @ 0x014

@@ -242,12 +244,20 @@ TIME_TABLE_DDR4_1600:
  Calibration Macro End
  ************************************************************
 ******************/
 
+.globl debug_print_dram_init_message
+.globl debug_print_ddr_version
+.globl debug_print_dram_size
+.globl debug_print_ddr_status
+.globl debug_print_ddr_phy_timing
+.globl init_debug_uart
 .globl lowlevel_init
 lowlevel_init:
 
 init_dram:
+    /* Setup a stack in SRAM */
+    ldr   sp, =AST_SRAM_END
     /* save lr */
-    mov   r4, lr
+    push  {lr}
 
     /* Clear AHB bus lock condition */

     ldr   r0, =0x1e600000

board/aspeed/ast-g5/platform.S +3 ~~-75~~

@@ -489,82 +499,10 @@ wait_mmc_reset_done:
     ldr   r1, =0x00020000
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e78400c
-    mov   r1, #0x83
-    str   r1, [r0]
-
-    ldr   r0, =0x1e6e202c
-    ldr   r2, [r0]
-    mov   r2, r2, lsr #12
-    tst   r2, #0x01
-    ldr   r0, =0x1e784000
-    moveq r1, #0x0D                              @ Baudrate 115200
-    movne r1, #0x01                              @ Baudrate 115200, div13
-#ifdef CONFIG_DRAM_UART_38400
-    moveq r1, #0x27                              @ Baudrate 38400
-    movne r1, #0x03                              @ Baudrate 38400 , div13
-#endif
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784004
-    mov   r1, #0x00
-    str   r1, [r0]
-
-    ldr   r0, =0x1e78400c
-    mov   r1, #0x03
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784008
-    mov   r1, #0x07
-    str   r1, [r0]
+    bl    init_debug_uart
 
-    ldr   r0, =0x1e784000
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
-    mov   r1, #0x41                              @ 'A'
-    str   r1, [r0]
-    mov   r1, #0x4D                              @ 'M'
-    str   r1, [r0]
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x49                              @ 'I'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x74                              @ 't'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    mov   r1, #0x56                              @ 'V'
-    str   r1, [r0]
-    mov   r1, #ASTMMC_INIT_VER
-    mov   r1, r1, lsr #4
-    print_hex_char
-    mov   r1, #ASTMMC_INIT_VER
-    print_hex_char
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    ldr   r0, =0x1e784014
-wait_print:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print
-    ldr   r0, =0x1e784000
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
+    mov   r0, #ASTMMC_INIT_VER
+    bl    debug_print_dram_init_message
 /* Debug - UART console message */
 
 /***********************************************************

*******************

board/aspeed/ast-g5/platform.S +2 -9

@@ -647,15 +585,8 @@ wait_print:
  DDR3 Init
  ************************************************************
 ******************/
 ddr3_init:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x33                              @ '3'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #3
+    bl    debug_print_ddr_version
 
 #if   defined (CONFIG_DRAM_1333)

adrl r5, TIME_TABLE_DDR3_1333 @ Init DRAM parameter
table

board/aspeed/ast-g5/platform.S +2 -9

@@ -865,15 +796,8 @@ ddr3_check_dllrdy:
  DDR4 Init
  ************************************************************
 ******************/
 ddr4_init:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x34                              @ '4'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #4
+    bl    debug_print_ddr_version
 
 #if   defined (CONFIG_DRAM_1333)

adrl r5, TIME_TABLE_DDR4_1333 @ Init DRAM parameter
table

board/aspeed/ast-g5/platform.S +9 ~~-229~~

@@ -1439,18 +1363,8 @@ check_dram_size_end:
     ldr   r1, =ASTMMC_INIT_DATE
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    str   r3, [r0]
-    mov   r1, #0x47                              @ 'G'
-    str   r1, [r0]
-    mov   r1, #0x62                              @ 'b'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, r3
+    bl    debug_print_dram_size
 
     /* Enable DRAM Cache */
     ldr   r0, =0x1e6e0004

@@ -1520,26 +1434,8 @@ ddr_wait_engine_idle_1:
     b     set_scratch                            @ CBRTest() return(1)
 
 ddr_test_fail:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x46                              @ 'F'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6C                              @ 'l'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-    ldr   r0, =0x1e784014
-wait_print_0:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_0
-/* Debug - UART console message */
+    mov   r0, #0
+    bl    debug_print_ddr_status
     b     reset_mmc
 
 set_scratch:

@@ -1549,21 +1445,8 @@ set_scratch:
     orr   r1, r1, #0x41
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x6F                              @ 'o'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x65                              @ 'e'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #1
+    bl    debug_print_ddr_status
 
     /* Enable VGA display */
     ldr   r0, =0x1e6e202c

@@ -1571,184 +1454,10 @@ set_scratch:
     bic   r1, r1, #0x40
     str   r1, [r0]
 
-/* Debug - UART console message */
-   /* Print PHY timing information */
-    ldr   r0, =0x1e784014
-wait_print_1:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_1
-
-    ldr   r0, =0x1e784000
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
-    mov   r1, #0x65                              @ 'e'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x64                              @ 'd'
-    str   r1, [r0]
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x6D                              @ 'm'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x72                              @ 'r'
-    str   r1, [r0]
-    mov   r1, #0x67                              @ 'g'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x4C                              @ 'L'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_2:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_2
-
-    ldr   r7, =0x000001FE                        @ divide by 510
-    mov   r8, #10                                @ multiply by 10
-print_DQL_eye_margin:
-    ldr   r0, =0x1e6e03d0
-    ldr   r2, [r0]
-    and   r2, r2, #0xFF
-    ldr   r0, =0x1e784000
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r3, #0x4                               @ print 4 digits
-print_DQL_div_loop:
-    mul   r2, r8, r2
-    cmp   r2, r7
-    blt   print_DQL_div_0
-    mov   r6, #0x0
-print_DQL_div_digit:
-    sub   r2, r2, r7
-    add   r6, r6, #0x1
-    cmp   r2, r7
-    bge   print_DQL_div_digit
-    b     print_DQL_div_n
-
-print_DQL_div_0:
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    b     print_DQL_next
-print_DQL_div_n:
-    add   r1, r6, #0x30                          @ print n
-    str   r1, [r0]
-print_DQL_next:
-    subs  r3, r3, #1
-    beq   print_DQH_eye_margin
-    cmp   r2, #0x0
-    beq   print_DQH_eye_margin
-    b     print_DQL_div_loop
-
-print_DQH_eye_margin:
-    mov   r1, #0x2F                              @ '/'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x48                              @ 'H'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_3:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_3
-
     ldr   r0, =0x1e6e03d0
     ldr   r2, [r0]
-    mov   r2, r2, lsr #8
-    and   r2, r2, #0xFF
-    ldr   r0, =0x1e784000
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r3, #0x4                               @ print 4 digits
-print_DQH_div_loop:
-    mul   r2, r8, r2
-    cmp   r2, r7
-    blt   print_DQH_div_0
-    mov   r6, #0x0
-print_DQH_div_digit:
-    sub   r2, r2, r7
-    add   r6, r6, #0x1
-    cmp   r2, r7
-    bge   print_DQH_div_digit
-    b     print_DQH_div_n
-
-print_DQH_div_0:
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    b     print_DQH_next
-print_DQH_div_n:
-    add   r1, r6, #0x30                          @ print n
-    str   r1, [r0]
-print_DQH_next:
-    subs  r3, r3, #1
-    beq   print_DQ_eye_margin_last
-    cmp   r2, #0x0
-    beq   print_DQ_eye_margin_last
-    b     print_DQH_div_loop
-
-print_DQ_eye_margin_last:
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x43                              @ 'C'
-    str   r1, [r0]
-    mov   r1, #0x4B                              @ 'K'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_4:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_4
-
-    ldr   r0, =0x1e784000
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x28                              @ '('
-    str   r1, [r0]
-    mov   r1, #0x6D                              @ 'm'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r1, #0x33                              @ '3'
-    str   r1, [r0]
-    mov   r1, #0x35                              @ '5'
-    str   r1, [r0]
-    mov   r1, #0x29                              @ ')'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, r2
+    bl    debug_print_ddr_phy_timing
 
 platform_exit:
 #ifdef CONFIG_DRAM_ECC

@@ -1991,9 +1700,5 @@ set_D2PLL:
     ldr   r1, =0xEA
     str   r1, [r0]
 
-    /* restore lr */
-    mov   lr, r4
-
     /* back to arch calling code */
-    mov   pc, lr
-
+    pop   {pc}
--

2.8.0.rc3.226.g39d4020

Signature · 1 line

*M*axim *S*loyko

Joel Stanley

maintainer

2016-09-08 00:31 UTC #2 lore raw

In reply to [email protected]

Hello Maxim,

Quoted 5 lines · On Sat, Sep 3, 2016 at 3:28 AM, <[email protected]> wrote:

From: Maxim Sloyko <[email protected]>
Set up a stack in SRAM at the beginning of lowlevel_init, which makes it possible to call non-trivial C functions, as well as put diagnostic strings themselves onto the stack.

Thanks for the patch. I am happy to see efforts to tame platform.S into something we can maintain and upstream. Do you plan on continuing this cleanup?

A bigger picture question: is there a good reason to retain these messages at boot? I don't think they provide any use for developers. They might be useful at bring up though. What are your thoughts?

Quoted 29 lines

Several one-char writes to debug uart still remain in platform.S, I figured it's not worth it to make a separate call to c function for each of those.

---
 arch/arm/include/asm/arch-aspeed/ast_uart.h | 142 +++++++++++
 arch/arm/include/asm/arch-aspeed/regs-scu.h |   4 +-
 arch/arm/mach-aspeed/Makefile               |   2 +-
 arch/arm/mach-aspeed/ast_uart.c             |  38 +++
 board/aspeed/ast-g5/ast-g5.c                | 110 ++++++++-
 board/aspeed/ast-g5/platform.S              | 351 +++-------------------------
 6 files changed, 318 insertions(+), 329 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-aspeed/ast_uart.h
 create mode 100644 arch/arm/mach-aspeed/ast_uart.c

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +8 -0

new file mode 100644
index 0000000..ddf1a14
@@ -0,0 +1,142 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *

arch/arm/include/asm/arch-aspeed/ast_uart.h line 18

Quoted 10 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +10 -0

+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ ******************************************************************************/

Drop the ascii art.

u-boot uses the SPDX-License-Identifier tags. See
http://www.denx.de/wiki/U-Boot/Licensing

Quoted 100 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +100 -0

+
+#ifndef __AST_UART_H
+#define __AST_UART_H
+
+#include <asm/io.h>
+
+#define AST_UART_RBR(uart)      (uart)
+#define AST_UART_THR(uart)      (uart)
+#define AST_UART_IER(uart)      ((uart) + 0x4)
+#define AST_UART_IIR(uart)      ((uart) + 0x8)
+#define AST_UART_FCR(uart)      ((uart) + 0x8)
+#define AST_UART_LCR(uart)      ((uart) + 0xc)
+#define AST_UART_MCR(uart)      ((uart) + 0x10)
+#define AST_UART_LSR(uart)      ((uart) + 0x14)
+#define AST_UART_MSR(uart)      ((uart) + 0x18)
+#define AST_UART_SCR(uart)      ((uart) + 0x1c)
+
+/* These registers can only be written when DLAB = 1*/
+#define AST_UART_DLL(uart)      ((uart))
+#define AST_UART_DLH(uart)      ((uart) + 0x4)
+
+/* Registers' contents */
+
+#define AST_UART_IER_THRE       (1 << 7)
+#define AST_UART_IER_EDSSI      (1 << 3)
+#define AST_UART_IER_ELSI       (1 << 2)
+#define AST_UART_IER_ETBEI      (1 << 1)
+#define AST_UART_IER_ERBFI      (1 << 0)
+
+/* AND this mask with AST_UART_IIR to find out if FIFOs are enabled. */
+#define AST_UART_IIR_FEN_MASK   (3 << 6)
+
+/* Bit0 == 0 means that the interrupt is pending, bits 3:1 identify
+ * interrupt.  These values are defined so that IIR | 0xf would give you the
+ * value for the interrupt. */
+#define AST_UART_IIR_MSC        (0)
+#define AST_UART_IIR_THRE       (1 << 1)
+#define AST_UART_IIR_RDA        (2 << 1)
+#define AST_UART_IIR_RS         (3 << 1)
+#define AST_UART_IIR_CTO        (6 << 1)
+
+/* RX FIFO Interrupt trigger level */
+#define AST_UART_FCR_RXFITL_MASK    (3 << 6)
+/* One byte received */
+#define AST_UART_FCR_RXFITL1    (0)
+/* 4 bytes received */
+#define AST_UART_FCR_RXFITL4    (1 << 6)
+/* 8 bytes received */
+#define AST_UART_FCR_RXFITL8    (2 << 6)
+/* 14 bytes received */
+#define AST_UART_FCR_RXFITL14   (3 << 6)
+
+/* TX FIFO Interrupt trigger level */
+#define AST_UART_FCR_TXFITL_MASK    (3 << 4)
+/* FIFO Empty (0 bytes in FIFO) */
+#define AST_UART_FCR_TXFITL0    (0)
+/* 2 bytes in FIFO */
+#define AST_UART_FCR_TXFITL2    (1 << 4)
+/* FIFO 1/4 full (4 bytes) */
+#define AST_UART_FCR_TXFITLQ    (2 << 4)
+/* FIFO 1/2 full (8 bytes) */
+#define AST_UART_FCR_TXFITLH    (3 << 4)
+
+#define AST_UART_FCR_TXFRST     (1 << 2)
+#define AST_UART_FCR_RXFRST     (1 << 1)
+#define AST_UART_FCR_FEN        (1 << 0)
+
+#define AST_UART_LCR_DLAB       (1 << 7)
+#define AST_UART_LCR_BC         (1 << 6)
+#define AST_UART_LCR_EPS        (1 << 4)
+#define AST_UART_LCR_PEN        (1 << 3)
+#define AST_UART_LCR_STOP       (1 << 2)
+
+/* Number of bits per character */
+#define AST_UART_LCR_BPC_MASK   (3)
+#define AST_UART_LCR_BPC5       (0)
+#define AST_UART_LCR_BPC6       (1)
+#define AST_UART_LCR_BPC7       (2)
+#define AST_UART_LCR_BPC8       (3)
+
+#define AST_UART_MCR_LB         (1 << 4)
+#define AST_UART_MCR_OUT2       (1 << 3)
+#define AST_UART_MCR_OUT1       (1 << 2)
+#define AST_UART_MCR_RTS        (1 << 1)
+#define AST_UART_MCR_DTR        (1 << 0)
+
+#define AST_UART_LSR_ERXF       (1 << 7)
+#define AST_UART_LSR_TEMPTY     (1 << 6)
+#define AST_UART_LSR_THRE       (1 << 5)
+#define AST_UART_LSR_BI         (1 << 4)
+#define AST_UART_LSR_FE         (1 << 3)
+#define AST_UART_LSR_PE         (1 << 2)
+#define AST_UART_LSR_OE         (1 << 1)
+#define AST_UART_LSR_DR         (1 << 0)
+
+#define AST_UART_MSR_NDCD_OUT2  (1 << 7)
+#define AST_UART_MSR_NRI_OUT1   (1 << 6)
+#define AST_UART_MSR_NDSR_NDTR  (1 << 5)
+#define AST_UART_MSR_NCTS_NRTS  (1 << 4)
+#define AST_UART_MSR_DDCD       (1 << 3)

arch/arm/include/asm/arch-aspeed/ast_uart.h line 128

Quoted 10 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +10 -0

+#define AST_UART_MSR_TERI       (1 << 2)
+#define AST_UART_MSR_DDSR       (1 << 1)
+#define AST_UART_MSR_DCTS       (1 << 0)
+
+#define AST_UART_FIFO_SIZE      (16)
+
+#define ast_uart_wait_txempty(uart) while(!(readl(AST_UART_LSR((uart))) & AST_UART_LSR_TEMPTY))
+#define ast_uart_write(uart, c)     writel((c), AST_UART_THR((uart)))
+#define ast_uart_enable_fifo(uart)  setbits_le32(AST_UART_FCR((uart)), AST_UART_FCR_FEN)
+#define ast_uart_enable_thre_mode(uart) setbits_le32(AST_UART_IER(uart), AST_UART_IER_THRE)

Why not functions for these?

Quoted 54 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +14 -0

+
+/* In THRE and FIFO mode, wait until there is some space in FIFO */
+#define ast_uart_wait_fifo_ready(uart) while((readl(AST_UART_LSR(uart)) & AST_UART_LSR_THRE))
+
+#define ast_uart_set_bpc(uart, bpc) clrsetbits_le32(AST_UART_LCR((uart)), AST_UART_LCR_BPC_MASK, (bpc))
+
+#define ast_uart_unlock_dlab(uart) setbits_le32(AST_UART_LCR((uart)), AST_UART_LCR_DLAB)
+#define ast_uart_lock_dlab(uart) clrbits_le32(AST_UART_LCR(uart), AST_UART_LCR_DLAB)
+
+/* NOTE: These write functions only work when THRE mode and FIFOs are enabled. */
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t* buffer, uint16_t len);
+void ast_uart_write_string_sync(uint32_t uart, const char* s);
+
+#endif

arch/arm/include/asm/arch-aspeed/regs-scu.h +2 -2

index b89df82..b714fa9 100644
@@ -10,8 +10,8 @@
  *    1. 2012/12/29 Ryan Chen Create
  *
 ********************************************************************************/
-#ifndef __AST_SCU_H
-#define __AST_SCU_H                     1
+#ifndef __AST_REGS_SCU_H
+#define __AST_REGS_SCU_H                     1
 
 #include <asm/arch/aspeed.h>

arch/arm/mach-aspeed/Makefile +1 -1

index d72f62a..3e0b4f7 100644
@@ -11,5 +11,5 @@
 #
 
 
-obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o
+obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o ast_uart.o
 obj-$(CONFIG_AST_SPI_NOR) += flash.o

arch/arm/mach-aspeed/ast_uart.c new file +8 -0

new file mode 100644
index 0000000..1226827
@@ -0,0 +1,38 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *

arch/arm/mach-aspeed/ast_uart.c line 18

Quoted 10 lines

arch/arm/mach-aspeed/ast_uart.c new file +10 -0

+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ ******************************************************************************/

Fix the header.

Quoted 10 lines

arch/arm/mach-aspeed/ast_uart.c new file +10 -0

+
+#include <asm/io.h>
+#include <asm/arch/ast_uart.h>
+
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t *buffer,
+                               uint16_t len)
+{
+       for (; len; --len, ++buffer) {
+               ast_uart_wait_fifo_ready(uart);
+               ast_uart_write(uart, *buffer);

arch/arm/mach-aspeed/ast_uart.c line 38

Quoted 10 lines

arch/arm/mach-aspeed/ast_uart.c new file +10 -0

+       }
+}
+
+void ast_uart_write_string_sync(uint32_t uart, const char *s)
+{
+       for (; *s; ++s) {
+               ast_uart_wait_fifo_ready(uart);
+               ast_uart_write(uart, *s);
+       }
+}

Is there any way we could reuse common string/serial code from u-boot?

Quoted 15 lines

board/aspeed/ast-g5/ast-g5.c +4 -1

index 81ea88a..b0b8535 100644
@@ -35,16 +35,21 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/arch/ast_scu.h>
+#include <asm/arch/ast_g5_platform.h>
 #include <asm/arch/ast-sdmc.h>
+#include <asm/arch/ast_scu.h>
+#include <asm/arch/ast_uart.h>
+#include <asm/arch/regs-scu.h>
 #include <asm/io.h>

board/aspeed/ast-g5/ast-g5.c line 52

Quoted 10 lines

board/aspeed/ast-g5/ast-g5.c +3 -1

 
+#define AST_DEBUG_UART      (0x1e784000)
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
 void show_boot_progress(int progress)
 {
-    printf("Boot reached stage %d\n", progress);
+       printf("Boot reached stage %d\n", progress);

This appears unrelated to your changes.

Quoted 12 lines

board/aspeed/ast-g5/ast-g5.c +5 -0

 }
 #endif

@@ -66,9 +71,108 @@ int dram_init(void)
        return 0;
 }
 
+/* assumes digit < 16 */
+static inline char hex_digit(uint8_t digit)
+{
+       if (digit < 10) {
+               return '0' + digit;

board/aspeed/ast-g5/ast-g5.c int dram_init(void) · line 88

Quoted 10 lines

board/aspeed/ast-g5/ast-g5.c +10 -0

+       } else {
+               return 'a' + (digit - 10);
+       }
+}
+
+static inline void format_u8_hex(char *dst, uint8_t value)
+{
+       *dst = hex_digit(value >> 4);
+       *(dst + 1) = hex_digit(value & 0xf);
+}

These are common printf formatting. Can we use them from another part of u-boot?

Quoted 79 lines

board/aspeed/ast-g5/ast-g5.c +79 -0

+
+static inline void debug_uart_print(const char *s)
+{
+       ast_uart_write_string_sync(AST_DEBUG_UART, s);
+}
+
+void debug_print_ddr_version(uint8_t version)
+{
+       char message[8] = "-DDR_\r\n";
+       message[4] = '0' + version;
+       debug_uart_print(message);
+}
+
+void debug_print_dram_init_message(uint8_t version)
+{
+       char message[16] = "\r\nDRAM Init-V__";
+       char *version_dst = message + 13;
+       format_u8_hex(version_dst, version);
+       debug_uart_print(message);
+}
+
+void debug_print_dram_size(char size)
+{
+       char message[6] = "-_Gb-";
+       message[1] = size;
+       debug_uart_print(message);
+}
+
+void debug_print_ddr_status(bool done)
+{
+       if (done) {
+               debug_uart_print("Done\r\n");
+       } else {
+               debug_uart_print("Fail\r\n");
+       }
+}
+
+static inline void format_phy_timing(char *dst, uint8_t value)
+{
+       /* This is adopted from platforms.S file by Aspeed.
+        * They read memory address (which is not mentioned in the data sheet)
+        * and then divide byte value by 510 and print 4 digits after the dot.
+        */
+       uint32_t timing_value = value * 1000 / 51;
+       for (int index = 3; index >= 0 && timing_value > 0; --index) {
+               uint8_t digit = timing_value % 10;
+               timing_value /= 10;
+               dst[index] = '0' + digit;
+       }
+}
+
+void debug_print_ddr_phy_timing(uint16_t margin)
+{
+       char message[46] = "Read margin DL:0.0000/0.0000 CK (min: 0.35)\r\n";
+       format_phy_timing(message + 17, margin & 0xff);
+       format_phy_timing(message + 24, (margin >> 8) & 0xff);
+       debug_uart_print(message);
+}
+
+static void init_uart_for_debug(uint32_t uart_base)
+{
+       ast_uart_set_bpc(uart_base, AST_UART_LCR_BPC8);
+       ast_uart_unlock_dlab(uart_base);
+       const uint32_t uart_clk_mul =
+           readl(AST_SCU_BASE + AST_SCU_MISC1_CTRL) & (1 << 12) ? 1 : 13;
+#ifdef CONFIG_DRAM_UART_38400
+       const uint32_t br_base = 3 * uart_clk_mul;
+#else
+       const uint32_t br_base = 1 * uart_clk_mul;
+#endif
+       writel(br_base, AST_UART_DLL(uart_base));
+       writel(0, AST_UART_DLH(uart_base));
+
+       /* Lock DLAB */
+       ast_uart_lock_dlab(uart_base);
+       ast_uart_enable_fifo(uart_base);
+       ast_uart_enable_thre_mode(uart_base);
+}
+

board/aspeed/ast-g5/ast-g5.c int dram_init(void) · line 176

Quoted 10 lines

board/aspeed/ast-g5/ast-g5.c +6 -1

+void init_debug_uart(void)
+{
+       init_uart_for_debug(AST_DEBUG_UART);
+}
+
 #ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bd)
 {
-        return ftgmac100_initialize(bd);
+       return ftgmac100_initialize(bd);

Unrelated change.

board/aspeed/ast-g5/platform.S line 81

Quoted 11 lines

board/aspeed/ast-g5/ast-g5.c +0 -0

 }
 #endif

board/aspeed/ast-g5/platform.S +0 -1

index c810f44..a33afee 100644
@@ -78,7 +78,6 @@
 #include <version.h>
 
 /******************************************************************************
-  r4 : return program counter

Quoted 436 lines

board/aspeed/ast-g5/platform.S +28 ~~-323~~

   r5 : DDR speed timing table base address
   Free registers:
   r0, r1, r2, r3, r6, r7, r8, r9, r10, r11

@@ -104,6 +103,9 @@
 #define ASTMMC_REGIDX_RFC    0x3C
 #define ASTMMC_REGIDX_PLL    0x40
 
+#define AST_SRAM_END  0x1e728ffc
+
+
 TIME_TABLE_DDR3_1333:
     .word   0x53503C37       @ 0x010
     .word   0xF858D47F       @ 0x014

@@ -242,12 +244,20 @@ TIME_TABLE_DDR4_1600:
  Calibration Macro End
  ******************************************************************************/
 
+.globl debug_print_dram_init_message
+.globl debug_print_ddr_version
+.globl debug_print_dram_size
+.globl debug_print_ddr_status
+.globl debug_print_ddr_phy_timing
+.globl init_debug_uart
 .globl lowlevel_init
 lowlevel_init:
 
 init_dram:
+    /* Setup a stack in SRAM */
+    ldr   sp, =AST_SRAM_END
     /* save lr */
-    mov   r4, lr
+    push  {lr}
 
     /* Clear AHB bus lock condition */
     ldr   r0, =0x1e600000

@@ -489,82 +499,10 @@ wait_mmc_reset_done:
     ldr   r1, =0x00020000
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e78400c
-    mov   r1, #0x83
-    str   r1, [r0]
-
-    ldr   r0, =0x1e6e202c
-    ldr   r2, [r0]
-    mov   r2, r2, lsr #12
-    tst   r2, #0x01
-    ldr   r0, =0x1e784000
-    moveq r1, #0x0D                              @ Baudrate 115200
-    movne r1, #0x01                              @ Baudrate 115200, div13
-#ifdef CONFIG_DRAM_UART_38400
-    moveq r1, #0x27                              @ Baudrate 38400
-    movne r1, #0x03                              @ Baudrate 38400 , div13
-#endif
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784004
-    mov   r1, #0x00
-    str   r1, [r0]
-
-    ldr   r0, =0x1e78400c
-    mov   r1, #0x03
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784008
-    mov   r1, #0x07
-    str   r1, [r0]
+    bl    init_debug_uart
 
-    ldr   r0, =0x1e784000
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
-    mov   r1, #0x41                              @ 'A'
-    str   r1, [r0]
-    mov   r1, #0x4D                              @ 'M'
-    str   r1, [r0]
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x49                              @ 'I'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x74                              @ 't'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    mov   r1, #0x56                              @ 'V'
-    str   r1, [r0]
-    mov   r1, #ASTMMC_INIT_VER
-    mov   r1, r1, lsr #4
-    print_hex_char
-    mov   r1, #ASTMMC_INIT_VER
-    print_hex_char
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    ldr   r0, =0x1e784014
-wait_print:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print
-    ldr   r0, =0x1e784000
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
+    mov   r0, #ASTMMC_INIT_VER
+    bl    debug_print_dram_init_message
 /* Debug - UART console message */
 
 /******************************************************************************

@@ -647,15 +585,8 @@ wait_print:
  DDR3 Init
  ******************************************************************************/
 ddr3_init:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x33                              @ '3'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #3
+    bl    debug_print_ddr_version
 
 #if   defined (CONFIG_DRAM_1333)
     adrl  r5, TIME_TABLE_DDR3_1333               @ Init DRAM parameter table

@@ -865,15 +796,8 @@ ddr3_check_dllrdy:
  DDR4 Init
  ******************************************************************************/
 ddr4_init:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x34                              @ '4'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #4
+    bl    debug_print_ddr_version
 
 #if   defined (CONFIG_DRAM_1333)
     adrl  r5, TIME_TABLE_DDR4_1333               @ Init DRAM parameter table

@@ -1439,18 +1363,8 @@ check_dram_size_end:
     ldr   r1, =ASTMMC_INIT_DATE
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    str   r3, [r0]
-    mov   r1, #0x47                              @ 'G'
-    str   r1, [r0]
-    mov   r1, #0x62                              @ 'b'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, r3
+    bl    debug_print_dram_size
 
     /* Enable DRAM Cache */
     ldr   r0, =0x1e6e0004

@@ -1520,26 +1434,8 @@ ddr_wait_engine_idle_1:
     b     set_scratch                            @ CBRTest() return(1)
 
 ddr_test_fail:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x46                              @ 'F'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6C                              @ 'l'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-    ldr   r0, =0x1e784014
-wait_print_0:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_0
-/* Debug - UART console message */
+    mov   r0, #0
+    bl    debug_print_ddr_status
     b     reset_mmc
 
 set_scratch:

@@ -1549,21 +1445,8 @@ set_scratch:
     orr   r1, r1, #0x41
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x6F                              @ 'o'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x65                              @ 'e'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #1
+    bl    debug_print_ddr_status
 
     /* Enable VGA display */
     ldr   r0, =0x1e6e202c

@@ -1571,184 +1454,10 @@ set_scratch:
     bic   r1, r1, #0x40
     str   r1, [r0]
 
-/* Debug - UART console message */
-   /* Print PHY timing information */
-    ldr   r0, =0x1e784014
-wait_print_1:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_1
-
-    ldr   r0, =0x1e784000
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
-    mov   r1, #0x65                              @ 'e'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x64                              @ 'd'
-    str   r1, [r0]
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x6D                              @ 'm'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x72                              @ 'r'
-    str   r1, [r0]
-    mov   r1, #0x67                              @ 'g'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x4C                              @ 'L'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_2:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_2
-
-    ldr   r7, =0x000001FE                        @ divide by 510
-    mov   r8, #10                                @ multiply by 10
-print_DQL_eye_margin:
-    ldr   r0, =0x1e6e03d0
-    ldr   r2, [r0]
-    and   r2, r2, #0xFF
-    ldr   r0, =0x1e784000
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r3, #0x4                               @ print 4 digits
-print_DQL_div_loop:
-    mul   r2, r8, r2
-    cmp   r2, r7
-    blt   print_DQL_div_0
-    mov   r6, #0x0
-print_DQL_div_digit:
-    sub   r2, r2, r7
-    add   r6, r6, #0x1
-    cmp   r2, r7
-    bge   print_DQL_div_digit
-    b     print_DQL_div_n
-
-print_DQL_div_0:
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    b     print_DQL_next
-print_DQL_div_n:
-    add   r1, r6, #0x30                          @ print n
-    str   r1, [r0]
-print_DQL_next:
-    subs  r3, r3, #1
-    beq   print_DQH_eye_margin
-    cmp   r2, #0x0
-    beq   print_DQH_eye_margin
-    b     print_DQL_div_loop
-
-print_DQH_eye_margin:
-    mov   r1, #0x2F                              @ '/'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x48                              @ 'H'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_3:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_3
-
     ldr   r0, =0x1e6e03d0
     ldr   r2, [r0]
-    mov   r2, r2, lsr #8
-    and   r2, r2, #0xFF
-    ldr   r0, =0x1e784000
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r3, #0x4                               @ print 4 digits
-print_DQH_div_loop:
-    mul   r2, r8, r2
-    cmp   r2, r7
-    blt   print_DQH_div_0
-    mov   r6, #0x0
-print_DQH_div_digit:
-    sub   r2, r2, r7
-    add   r6, r6, #0x1
-    cmp   r2, r7
-    bge   print_DQH_div_digit
-    b     print_DQH_div_n
-
-print_DQH_div_0:
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    b     print_DQH_next
-print_DQH_div_n:
-    add   r1, r6, #0x30                          @ print n
-    str   r1, [r0]
-print_DQH_next:
-    subs  r3, r3, #1
-    beq   print_DQ_eye_margin_last
-    cmp   r2, #0x0
-    beq   print_DQ_eye_margin_last
-    b     print_DQH_div_loop
-
-print_DQ_eye_margin_last:
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x43                              @ 'C'
-    str   r1, [r0]
-    mov   r1, #0x4B                              @ 'K'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_4:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_4
-
-    ldr   r0, =0x1e784000
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x28                              @ '('
-    str   r1, [r0]
-    mov   r1, #0x6D                              @ 'm'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r1, #0x33                              @ '3'
-    str   r1, [r0]
-    mov   r1, #0x35                              @ '5'
-    str   r1, [r0]
-    mov   r1, #0x29                              @ ')'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, r2
+    bl    debug_print_ddr_phy_timing
 
 platform_exit:
 #ifdef CONFIG_DRAM_ECC

@@ -1991,9 +1700,5 @@ set_D2PLL:
     ldr   r1, =0xEA
     str   r1, [r0]
 
-    /* restore lr */
-    mov   lr, r4
-
     /* back to arch calling code */
-    mov   pc, lr
-
+    pop   {pc}
--

2.8.0.rc3.226.g39d4020

_______________________________________________
openbmc mailing list
[email protected]
https://lists.ozlabs.org/listinfo/openbmc

[email protected]

author

2016-09-09 17:35 UTC #3 lore raw

PATCH 1/1 aspeed/ast-g5: Added ast_uart.{c, h} files, moved most of the diagnostic message printing to ast-g5.c

From: Maxim Sloyko <[email protected]>

Set up a stack in SRAM at the beginning of lowlevel_init, which makes it possible to call non-trivial C functions, as well as put diagnostic strings themselves onto the stack.

Several one-char writes to debug uart still remain in platform.S, I figured it's not worth it to make a separate call to c function for each of those.

---
 arch/arm/include/asm/arch-aspeed/ast_uart.h | 129 ++++++++++
 arch/arm/include/asm/arch-aspeed/regs-scu.h |   4 +-
 arch/arm/mach-aspeed/Makefile               |   2 +-
 arch/arm/mach-aspeed/ast_uart.c             |  25 ++
 board/aspeed/ast-g5/ast-g5.c                | 106 ++++++++-
 board/aspeed/ast-g5/platform.S              | 353 +++-------------------------
 6 files changed, 291 insertions(+), 328 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-aspeed/ast_uart.h
 create mode 100644 arch/arm/mach-aspeed/ast_uart.c

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +129 -0

new file mode 100644
index 0000000..9aceedb
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AST_UART_H
+#define __AST_UART_H
+
+#include <asm/io.h>
+
+#define AST_UART_RBR(uart)      (uart)
+#define AST_UART_THR(uart)      (uart)
+#define AST_UART_IER(uart)      ((uart) + 0x4)
+#define AST_UART_IIR(uart)      ((uart) + 0x8)
+#define AST_UART_FCR(uart)      ((uart) + 0x8)
+#define AST_UART_LCR(uart)      ((uart) + 0xc)
+#define AST_UART_MCR(uart)      ((uart) + 0x10)
+#define AST_UART_LSR(uart)      ((uart) + 0x14)
+#define AST_UART_MSR(uart)      ((uart) + 0x18)
+#define AST_UART_SCR(uart)      ((uart) + 0x1c)
+
+/* These registers can only be written when DLAB = 1*/
+#define AST_UART_DLL(uart)      ((uart))
+#define AST_UART_DLH(uart)      ((uart) + 0x4)
+
+/* Registers' contents */
+
+#define AST_UART_IER_THRE       (1 << 7)
+#define AST_UART_IER_EDSSI      (1 << 3)
+#define AST_UART_IER_ELSI       (1 << 2)
+#define AST_UART_IER_ETBEI      (1 << 1)
+#define AST_UART_IER_ERBFI      (1 << 0)
+
+/* AND this mask with AST_UART_IIR to find out if FIFOs are enabled. */
+#define AST_UART_IIR_FEN_MASK   (3 << 6)
+
+/* Bit0 == 0 means that the interrupt is pending, bits 3:1 identify
+ * interrupt.  These values are defined so that IIR | 0xf would give you the
+ * value for the interrupt. */
+#define AST_UART_IIR_MSC        (0)
+#define AST_UART_IIR_THRE       (1 << 1)
+#define AST_UART_IIR_RDA        (2 << 1)
+#define AST_UART_IIR_RS         (3 << 1)
+#define AST_UART_IIR_CTO        (6 << 1)
+
+/* RX FIFO Interrupt trigger level */
+#define AST_UART_FCR_RXFITL_MASK    (3 << 6)
+/* One byte received */
+#define AST_UART_FCR_RXFITL1    (0)
+/* 4 bytes received */
+#define AST_UART_FCR_RXFITL4    (1 << 6)
+/* 8 bytes received */
+#define AST_UART_FCR_RXFITL8    (2 << 6)
+/* 14 bytes received */
+#define AST_UART_FCR_RXFITL14   (3 << 6)
+
+/* TX FIFO Interrupt trigger level */
+#define AST_UART_FCR_TXFITL_MASK    (3 << 4)
+/* FIFO Empty (0 bytes in FIFO) */
+#define AST_UART_FCR_TXFITL0    (0)
+/* 2 bytes in FIFO */
+#define AST_UART_FCR_TXFITL2    (1 << 4)
+/* FIFO 1/4 full (4 bytes) */
+#define AST_UART_FCR_TXFITLQ    (2 << 4)
+/* FIFO 1/2 full (8 bytes) */
+#define AST_UART_FCR_TXFITLH    (3 << 4)
+
+#define AST_UART_FCR_TXFRST     (1 << 2)
+#define AST_UART_FCR_RXFRST     (1 << 1)
+#define AST_UART_FCR_FEN        (1 << 0)
+
+#define AST_UART_LCR_DLAB       (1 << 7)
+#define AST_UART_LCR_BC         (1 << 6)
+#define AST_UART_LCR_EPS        (1 << 4)
+#define AST_UART_LCR_PEN        (1 << 3)
+#define AST_UART_LCR_STOP       (1 << 2)
+
+/* Number of bits per character */
+#define AST_UART_LCR_BPC_MASK   (3)
+#define AST_UART_LCR_BPC5       (0)
+#define AST_UART_LCR_BPC6       (1)
+#define AST_UART_LCR_BPC7       (2)
+#define AST_UART_LCR_BPC8       (3)
+
+#define AST_UART_MCR_LB         (1 << 4)
+#define AST_UART_MCR_OUT2       (1 << 3)
+#define AST_UART_MCR_OUT1       (1 << 2)
+#define AST_UART_MCR_RTS        (1 << 1)
+#define AST_UART_MCR_DTR        (1 << 0)
+
+#define AST_UART_LSR_ERXF       (1 << 7)
+#define AST_UART_LSR_TEMPTY     (1 << 6)
+#define AST_UART_LSR_THRE       (1 << 5)
+#define AST_UART_LSR_BI         (1 << 4)
+#define AST_UART_LSR_FE         (1 << 3)
+#define AST_UART_LSR_PE         (1 << 2)
+#define AST_UART_LSR_OE         (1 << 1)
+#define AST_UART_LSR_DR         (1 << 0)
+
+#define AST_UART_MSR_NDCD_OUT2  (1 << 7)
+#define AST_UART_MSR_NRI_OUT1   (1 << 6)
+#define AST_UART_MSR_NDSR_NDTR  (1 << 5)
+#define AST_UART_MSR_NCTS_NRTS  (1 << 4)
+#define AST_UART_MSR_DDCD       (1 << 3)
+#define AST_UART_MSR_TERI       (1 << 2)
+#define AST_UART_MSR_DDSR       (1 << 1)
+#define AST_UART_MSR_DCTS       (1 << 0)
+
+#define AST_UART_FIFO_SIZE      (16)
+
+#define ast_uart_wait_txempty(uart) while(!(readl(AST_UART_LSR((uart))) & AST_UART_LSR_TEMPTY))
+#define ast_uart_write(uart, c)     writel((c), AST_UART_THR((uart)))
+#define ast_uart_enable_fifo(uart)  setbits_le32(AST_UART_FCR((uart)), AST_UART_FCR_FEN)
+#define ast_uart_enable_thre_mode(uart) setbits_le32(AST_UART_IER(uart), AST_UART_IER_THRE)
+
+/* In THRE and FIFO mode, wait until there is some space in FIFO */
+#define ast_uart_wait_fifo_ready(uart) while((readl(AST_UART_LSR(uart)) & AST_UART_LSR_THRE))
+
+#define ast_uart_set_bpc(uart, bpc) clrsetbits_le32(AST_UART_LCR((uart)), AST_UART_LCR_BPC_MASK, (bpc))
+
+#define ast_uart_unlock_dlab(uart) setbits_le32(AST_UART_LCR((uart)), AST_UART_LCR_DLAB)
+#define ast_uart_lock_dlab(uart) clrbits_le32(AST_UART_LCR(uart), AST_UART_LCR_DLAB)
+
+/* NOTE: These write functions only work when THRE mode and FIFOs are enabled. */
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t* buffer, uint16_t len);
+void ast_uart_write_string_sync(uint32_t uart, const char* s);
+
+#endif

arch/arm/include/asm/arch-aspeed/regs-scu.h +2 -2

index b89df82..b714fa9 100644
@@ -10,8 +10,8 @@
  *    1. 2012/12/29 Ryan Chen Create
  *
 ********************************************************************************/
-#ifndef __AST_SCU_H
-#define __AST_SCU_H                     1
+#ifndef __AST_REGS_SCU_H
+#define __AST_REGS_SCU_H                     1
 
 #include <asm/arch/aspeed.h>

arch/arm/mach-aspeed/Makefile +1 -1

index d72f62a..3e0b4f7 100644
@@ -11,5 +11,5 @@
 #
 
 
-obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o
+obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o ast_uart.o
 obj-$(CONFIG_AST_SPI_NOR) += flash.o

arch/arm/mach-aspeed/ast_uart.c new file +25 -0

new file mode 100644
index 0000000..b0d4dfa
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/ast_uart.h>
+
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t *buffer,
+				uint16_t len)
+{
+	for (; len; --len, ++buffer) {
+		ast_uart_wait_fifo_ready(uart);
+		ast_uart_write(uart, *buffer);
+	}
+}
+
+void ast_uart_write_string_sync(uint32_t uart, const char *s)
+{
+	for (; *s; ++s) {
+		ast_uart_wait_fifo_ready(uart);
+		ast_uart_write(uart, *s);
+	}
+}

board/aspeed/ast-g5/ast-g5.c +105 -1

121 lines not on this page · raw message

board/aspeed/ast-g5/platform.S +29 ~~-324~~

427 lines not on this page · raw message

Signature · 1 line

2.8.0.rc3.226.g39d4020

Maxim Sloyko

author

2016-09-09 17:43 UTC #4 lore raw

In reply to Joel Stanley

Sorry, the new patch is in separate message, I'm still trying to figure out how this process works.

Quoted 5 lines · Joel Stanley

Hello Maxim,
Quoted 2 lines · On Sat, Sep 3, 2016 at 3:28 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>

Quoted 8 lines

Quoted 3 lines
Set up a stack in SRAM at the beginning of lowlevel_init, which makes it possible to call non-trivial C functions, as well as put diagnostic strings themselves onto the stack.
Thanks for the patch. I am happy to see efforts to tame platform.S into something we can maintain and upstream. Do you plan on continuing this cleanup?

Time-permitting, yes. I'm trying to move all of this to Driver Model with device tree, which I think will make most of platform.S obsolete. No promises yet though.

Quoted 5 lines

A bigger picture question: is there a good reason to retain these messages at boot? I don't think they provide any use for developers. They might be useful at bring up though. What are your thoughts?

They are somewhat useful to me at the moment, yes.

Quoted 43 lines

Quoted 5 lines
Several one-char writes to debug uart still remain in platform.S, I figured it's not worth it to make a separate call to c function for each of those.
Quoted 7 lines
---
 arch/arm/include/asm/arch-aspeed/ast_uart.h | 142 +++++++++++
 arch/arm/include/asm/arch-aspeed/regs-scu.h |   4 +-
 arch/arm/mach-aspeed/Makefile               |   2 +-
 arch/arm/mach-aspeed/ast_uart.c             |  38 +++
 board/aspeed/ast-g5/ast-g5.c                | 110 ++++++++-
 board/aspeed/ast-g5/platform.S              | 351
+++-------------------------
Review
Quoted 5 lines
 6 files changed, 318 insertions(+), 329 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-aspeed/ast_uart.h
 create mode 100644 arch/arm/mach-aspeed/ast_uart.c
(quoted diff) +0 -0
b/arch/arm/include/asm/arch-aspeed/ast_uart.h
arch/arm/include/asm/arch-aspeed/ast_uart.h line 1
Quoted 6 lines
new file mode 100644
index 0000000..ddf1a14
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +1 -0
@@ -0,0 +1,142 @@
+/**********************************************************
*********************
Quoted 7 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +7 -0
+ * Copyright (C) 2016 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
arch/arm/include/asm/arch-aspeed/ast_uart.h
Quoted 10 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +10 -0
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ ************************************************************

Quoted 8 lines

******************/
Drop the ascii art.
u-boot uses the SPDX-License-Identifier tags. See
http://www.denx.de/wiki/U-Boot/Licensing

Fixed.

Quoted 109 lines

Quoted 24 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +24 -0

+
+#ifndef __AST_UART_H
+#define __AST_UART_H
+
+#include <asm/io.h>
+
+#define AST_UART_RBR(uart)      (uart)
+#define AST_UART_THR(uart)      (uart)
+#define AST_UART_IER(uart)      ((uart) + 0x4)
+#define AST_UART_IIR(uart)      ((uart) + 0x8)
+#define AST_UART_FCR(uart)      ((uart) + 0x8)
+#define AST_UART_LCR(uart)      ((uart) + 0xc)
+#define AST_UART_MCR(uart)      ((uart) + 0x10)
+#define AST_UART_LSR(uart)      ((uart) + 0x14)
+#define AST_UART_MSR(uart)      ((uart) + 0x18)
+#define AST_UART_SCR(uart)      ((uart) + 0x1c)
+
+/* These registers can only be written when DLAB = 1*/
+#define AST_UART_DLL(uart)      ((uart))
+#define AST_UART_DLH(uart)      ((uart) + 0x4)
+
+/* Registers' contents */
+
+#define AST_UART_IER_THRE       (1 << 7)

arch/arm/include/asm/arch-aspeed/ast_uart.h

Quoted 10 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +10 -0

+#define AST_UART_IER_EDSSI      (1 << 3)
+#define AST_UART_IER_ELSI       (1 << 2)
+#define AST_UART_IER_ETBEI      (1 << 1)
+#define AST_UART_IER_ERBFI      (1 << 0)
+
+/* AND this mask with AST_UART_IIR to find out if FIFOs are enabled. */
+#define AST_UART_IIR_FEN_MASK   (3 << 6)
+
+/* Bit0 == 0 means that the interrupt is pending, bits 3:1 identify
+ * interrupt.  These values are defined so that IIR | 0xf would give

you the

Quoted 63 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +63 -0

+ * value for the interrupt. */
+#define AST_UART_IIR_MSC        (0)
+#define AST_UART_IIR_THRE       (1 << 1)
+#define AST_UART_IIR_RDA        (2 << 1)
+#define AST_UART_IIR_RS         (3 << 1)
+#define AST_UART_IIR_CTO        (6 << 1)
+
+/* RX FIFO Interrupt trigger level */
+#define AST_UART_FCR_RXFITL_MASK    (3 << 6)
+/* One byte received */
+#define AST_UART_FCR_RXFITL1    (0)
+/* 4 bytes received */
+#define AST_UART_FCR_RXFITL4    (1 << 6)
+/* 8 bytes received */
+#define AST_UART_FCR_RXFITL8    (2 << 6)
+/* 14 bytes received */
+#define AST_UART_FCR_RXFITL14   (3 << 6)
+
+/* TX FIFO Interrupt trigger level */
+#define AST_UART_FCR_TXFITL_MASK    (3 << 4)
+/* FIFO Empty (0 bytes in FIFO) */
+#define AST_UART_FCR_TXFITL0    (0)
+/* 2 bytes in FIFO */
+#define AST_UART_FCR_TXFITL2    (1 << 4)
+/* FIFO 1/4 full (4 bytes) */
+#define AST_UART_FCR_TXFITLQ    (2 << 4)
+/* FIFO 1/2 full (8 bytes) */
+#define AST_UART_FCR_TXFITLH    (3 << 4)
+
+#define AST_UART_FCR_TXFRST     (1 << 2)
+#define AST_UART_FCR_RXFRST     (1 << 1)
+#define AST_UART_FCR_FEN        (1 << 0)
+
+#define AST_UART_LCR_DLAB       (1 << 7)
+#define AST_UART_LCR_BC         (1 << 6)
+#define AST_UART_LCR_EPS        (1 << 4)
+#define AST_UART_LCR_PEN        (1 << 3)
+#define AST_UART_LCR_STOP       (1 << 2)
+
+/* Number of bits per character */
+#define AST_UART_LCR_BPC_MASK   (3)
+#define AST_UART_LCR_BPC5       (0)
+#define AST_UART_LCR_BPC6       (1)
+#define AST_UART_LCR_BPC7       (2)
+#define AST_UART_LCR_BPC8       (3)
+
+#define AST_UART_MCR_LB         (1 << 4)
+#define AST_UART_MCR_OUT2       (1 << 3)
+#define AST_UART_MCR_OUT1       (1 << 2)
+#define AST_UART_MCR_RTS        (1 << 1)
+#define AST_UART_MCR_DTR        (1 << 0)
+
+#define AST_UART_LSR_ERXF       (1 << 7)
+#define AST_UART_LSR_TEMPTY     (1 << 6)
+#define AST_UART_LSR_THRE       (1 << 5)
+#define AST_UART_LSR_BI         (1 << 4)
+#define AST_UART_LSR_FE         (1 << 3)
+#define AST_UART_LSR_PE         (1 << 2)
+#define AST_UART_LSR_OE         (1 << 1)
+#define AST_UART_LSR_DR         (1 << 0)
+
+#define AST_UART_MSR_NDCD_OUT2  (1 << 7)
+#define AST_UART_MSR_NRI_OUT1   (1 << 6)

arch/arm/include/asm/arch-aspeed/ast_uart.h

Quoted 10 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h new file +10 -0

+#define AST_UART_MSR_NDSR_NDTR  (1 << 5)
+#define AST_UART_MSR_NCTS_NRTS  (1 << 4)
+#define AST_UART_MSR_DDCD       (1 << 3)
+#define AST_UART_MSR_TERI       (1 << 2)
+#define AST_UART_MSR_DDSR       (1 << 1)
+#define AST_UART_MSR_DCTS       (1 << 0)
+
+#define AST_UART_FIFO_SIZE      (16)
+
+#define ast_uart_wait_txempty(uart) while(!(readl(AST_UART_LSR((uart)))

& AST_UART_LSR_TEMPTY))

Quoted 8 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h line 127
Quoted 2 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0
+#define ast_uart_write(uart, c)     writel((c), AST_UART_THR((uart)))
+#define ast_uart_enable_fifo(uart)  setbits_le32(AST_UART_FCR((uart)),
AST_UART_FCR_FEN)
arch/arm/include/asm/arch-aspeed/ast_uart.h line 128
Quoted 1 line
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +1 -0
+#define ast_uart_enable_thre_mode(uart) setbits_le32(AST_UART_IER(uart),
AST_UART_IER_THRE)
Why not functions for these?

Just to avoid function call overhead. They look simple enough.

Quoted 95 lines

arch/arm/include/asm/arch-aspeed/ast_uart.h
Quoted 4 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +3 -0
+
+/* In THRE and FIFO mode, wait until there is some space in FIFO */
+#define ast_uart_wait_fifo_ready(uart) while((readl(AST_UART_LSR(uart))
& AST_UART_LSR_THRE))
arch/arm/include/asm/arch-aspeed/ast_uart.h line 133
Quoted 2 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0
+
+#define ast_uart_set_bpc(uart, bpc) clrsetbits_le32(AST_UART_LCR((uart)),
AST_UART_LCR_BPC_MASK, (bpc))
arch/arm/include/asm/arch-aspeed/ast_uart.h line 135
Quoted 2 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0
+
+#define ast_uart_unlock_dlab(uart) setbits_le32(AST_UART_LCR((uart)),
AST_UART_LCR_DLAB)
arch/arm/include/asm/arch-aspeed/ast_uart.h line 136
Quoted 1 line
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +1 -0
+#define ast_uart_lock_dlab(uart) clrbits_le32(AST_UART_LCR(uart),
AST_UART_LCR_DLAB)
arch/arm/include/asm/arch-aspeed/ast_uart.h line 138
Quoted 2 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +2 -0
+
+/* NOTE: These write functions only work when THRE mode and FIFOs are
enabled. */
arch/arm/include/asm/arch-aspeed/ast_uart.h line 139
Quoted 1 line
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +1 -0
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t* buffer,
uint16_t len);
Review
Quoted 4 lines
arch/arm/include/asm/arch-aspeed/ast_uart.h new file +3 -0
+void ast_uart_write_string_sync(uint32_t uart, const char* s);
+
+#endif
(quoted diff) +0 -0
b/arch/arm/include/asm/arch-aspeed/regs-scu.h
arch/arm/include/asm/arch-aspeed/regs-scu.h line 12
Quoted 7 lines
index b89df82..b714fa9 100644
arch/arm/include/asm/arch-aspeed/regs-scu.h +0 -0
@@ -10,8 +10,8 @@
  *    1. 2012/12/29 Ryan Chen Create
  *
 ************************************************************
********************/
arch/arm/mach-aspeed/
Quoted 8 lines
arch/arm/include/asm/arch-aspeed/regs-scu.h +2 -2
-#ifndef __AST_SCU_H
-#define __AST_SCU_H                     1
+#ifndef __AST_REGS_SCU_H
+#define __AST_REGS_SCU_H                     1
 
 #include <asm/arch/aspeed.h>
 
arch/arm/mach-aspeed/ renamed from arch/arm/mach-aspeed/Makefile +0 -0
Makefile
arch/arm/mach-aspeed/Makefile line 14
Quoted 9 lines
index d72f62a..3e0b4f7 100644
arch/arm/mach-aspeed/Makefile +1 -1
@@ -11,5 +11,5 @@
 #
 
 
-obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o
+obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o
ast_uart.o
arch/arm/mach-aspeed/ast_
Quoted 2 lines
arch/arm/mach-aspeed/Makefile +0 -0
 obj-$(CONFIG_AST_SPI_NOR) += flash.o
arch/arm/mach-aspeed/ast_ renamed from arch/arm/mach-aspeed/ast_uart.c +0 -0
uart.c
arch/arm/mach-aspeed/ast_uart.c line 1
Quoted 6 lines
new file mode 100644
index 0000000..1226827
arch/arm/mach-aspeed/ast_uart.c new file +1 -0
@@ -0,0 +1,38 @@
+/**********************************************************
*********************
Quoted 7 lines
arch/arm/mach-aspeed/ast_uart.c new file +7 -0
+ * Copyright (C) 2016 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
arch/arm/mach-aspeed/ast_uart.c line 18
Quoted 10 lines
arch/arm/mach-aspeed/ast_uart.c new file +10 -0
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ ************************************************************
******************/
Fix the header.
Quoted 14 lines
arch/arm/mach-aspeed/ast_uart.c new file +14 -0
+
+#include <asm/io.h>
+#include <asm/arch/ast_uart.h>
+
+void ast_uart_write_buffer_sync(uint32_t uart, const uint8_t *buffer,
+                               uint16_t len)
+{
+       for (; len; --len, ++buffer) {
+               ast_uart_wait_fifo_ready(uart);
+               ast_uart_write(uart, *buffer);
+       }
+}
+
+void ast_uart_write_string_sync(uint32_t uart, const char *s)

Quoted 9 lines

arch/arm/mach-aspeed/ast_uart.c line 38
Quoted 6 lines
arch/arm/mach-aspeed/ast_uart.c new file +6 -0
+{
+       for (; *s; ++s) {
+               ast_uart_wait_fifo_ready(uart);
+               ast_uart_write(uart, *s);
+       }
+}
Is there any way we could reuse common string/serial code from u-boot?

Maybe, I have no experience with that. Making this fully compatible with console or serial is somewhat out of scope of what I'm trying to do here.

Quoted 21 lines

board/aspeed/ast-g5/ast-g5.c +6 -1

index 81ea88a..b0b8535 100644
@@ -35,16 +35,21 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/arch/ast_scu.h>
+#include <asm/arch/ast_g5_platform.h>
 #include <asm/arch/ast-sdmc.h>
+#include <asm/arch/ast_scu.h>
+#include <asm/arch/ast_uart.h>
+#include <asm/arch/regs-scu.h>
 #include <asm/io.h>
 
+#define AST_DEBUG_UART      (0x1e784000)
+
 DECLARE_GLOBAL_DATA_PTR;

Quoted 8 lines

board/aspeed/ast-g5/ast-g5.c line 52
Quoted 5 lines
board/aspeed/ast-g5/ast-g5.c +1 -1
 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
 void show_boot_progress(int progress)
 {
-    printf("Boot reached stage %d\n", progress);
+       printf("Boot reached stage %d\n", progress);
This appears unrelated to your changes.

I'll send automatic style fixes in a separate patch.

Quoted 133 lines

Quoted 13 lines

board/aspeed/ast-g5/ast-g5.c +5 -0

 }
 #endif

@@ -66,9 +71,108 @@ int dram_init(void)
        return 0;
 }
 
+/* assumes digit < 16 */
+static inline char hex_digit(uint8_t digit)
+{
+       if (digit < 10) {
+               return '0' + digit;

board/aspeed/ast-g5/ast-g5.c int dram_init(void) · line 88

Quoted 10 lines

board/aspeed/ast-g5/ast-g5.c +10 -0

+       } else {
+               return 'a' + (digit - 10);
+       }
+}
+
+static inline void format_u8_hex(char *dst, uint8_t value)
+{
+       *dst = hex_digit(value >> 4);
+       *(dst + 1) = hex_digit(value & 0xf);
+}

These are common printf formatting. Can we use them from another part of u-boot?

Quoted 31 lines

board/aspeed/ast-g5/ast-g5.c +31 -0

+
+static inline void debug_uart_print(const char *s)
+{
+       ast_uart_write_string_sync(AST_DEBUG_UART, s);
+}
+
+void debug_print_ddr_version(uint8_t version)
+{
+       char message[8] = "-DDR_\r\n";
+       message[4] = '0' + version;
+       debug_uart_print(message);
+}
+
+void debug_print_dram_init_message(uint8_t version)
+{
+       char message[16] = "\r\nDRAM Init-V__";
+       char *version_dst = message + 13;
+       format_u8_hex(version_dst, version);
+       debug_uart_print(message);
+}
+
+void debug_print_dram_size(char size)
+{
+       char message[6] = "-_Gb-";
+       message[1] = size;
+       debug_uart_print(message);
+}
+
+void debug_print_ddr_status(bool done)
+{
+       if (done) {

board/aspeed/ast-g5/ast-g5.c int dram_init(void)

Quoted 10 lines

board/aspeed/ast-g5/ast-g5.c +10 -0

+               debug_uart_print("Done\r\n");
+       } else {
+               debug_uart_print("Fail\r\n");
+       }
+}
+
+static inline void format_phy_timing(char *dst, uint8_t value)
+{
+       /* This is adopted from platforms.S file by Aspeed.
+        * They read memory address (which is not mentioned in the data

sheet)

board/aspeed/ast-g5/ast-g5.c int dram_init(void) · line 130

Quoted 1 line

board/aspeed/ast-g5/ast-g5.c +1 -0

+        * and then divide byte value by 510 and print 4 digits after

the dot.

board/aspeed/ast-g5/ast-g5.c int dram_init(void)

Quoted 12 lines

board/aspeed/ast-g5/ast-g5.c +12 -0

+        */
+       uint32_t timing_value = value * 1000 / 51;
+       for (int index = 3; index >= 0 && timing_value > 0; --index) {
+               uint8_t digit = timing_value % 10;
+               timing_value /= 10;
+               dst[index] = '0' + digit;
+       }
+}
+
+void debug_print_ddr_phy_timing(uint16_t margin)
+{
+       char message[46] = "Read margin DL:0.0000/0.0000 CK (min:

0.35)\r\n";

board/aspeed/ast-g5/ast-g5.c int dram_init(void)

Quoted 11 lines

board/aspeed/ast-g5/ast-g5.c +11 -0

+       format_phy_timing(message + 17, margin & 0xff);
+       format_phy_timing(message + 24, (margin >> 8) & 0xff);
+       debug_uart_print(message);
+}
+
+static void init_uart_for_debug(uint32_t uart_base)
+{
+       ast_uart_set_bpc(uart_base, AST_UART_LCR_BPC8);
+       ast_uart_unlock_dlab(uart_base);
+       const uint32_t uart_clk_mul =
+           readl(AST_SCU_BASE + AST_SCU_MISC1_CTRL) & (1 << 12) ? 1 :

13;

Quoted 14 lines

board/aspeed/ast-g5/ast-g5.c +14 -0

+#ifdef CONFIG_DRAM_UART_38400
+       const uint32_t br_base = 3 * uart_clk_mul;
+#else
+       const uint32_t br_base = 1 * uart_clk_mul;
+#endif
+       writel(br_base, AST_UART_DLL(uart_base));
+       writel(0, AST_UART_DLH(uart_base));
+
+       /* Lock DLAB */
+       ast_uart_lock_dlab(uart_base);
+       ast_uart_enable_fifo(uart_base);
+       ast_uart_enable_thre_mode(uart_base);
+}
+

board/aspeed/ast-g5/ast-g5.c int dram_init(void) · line 176

Quoted 10 lines

board/aspeed/ast-g5/ast-g5.c +6 -1

+void init_debug_uart(void)
+{
+       init_uart_for_debug(AST_DEBUG_UART);
+}
+
 #ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bd)
 {
-        return ftgmac100_initialize(bd);
+       return ftgmac100_initialize(bd);

Unrelated change.

board/aspeed/ast-g5/

Quoted 3 lines

board/aspeed/ast-g5/ast-g5.c +0 -0
 }
 #endif
board/aspeed/ast-g5/ renamed from board/aspeed/ast-g5/platform.S +0 -0

platform.S

Quoted 6 lines

index c810f44..a33afee 100644
board/aspeed/ast-g5/platform.S +0 -0
@@ -78,7 +78,6 @@
 #include <version.h>
 

Quoted 6 lines

board/aspeed/ast-g5/platform.S line 80
Quoted 1 line
board/aspeed/ast-g5/platform.S +0 -0
 /***********************************************************
*******************
board/aspeed/ast-g5/platform.S line 81
Quoted 1 line
board/aspeed/ast-g5/platform.S +0 -1
-  r4 : return program counter
??

r4 is no longer used in this code.

Quoted 446 lines

Quoted 15 lines

board/aspeed/ast-g5/platform.S +3 -0

   r5 : DDR speed timing table base address
   Free registers:
   r0, r1, r2, r3, r6, r7, r8, r9, r10, r11

@@ -104,6 +103,9 @@
 #define ASTMMC_REGIDX_RFC    0x3C
 #define ASTMMC_REGIDX_PLL    0x40
 
+#define AST_SRAM_END  0x1e728ffc
+
+
 TIME_TABLE_DDR3_1333:
     .word   0x53503C37       @ 0x010
     .word   0xF858D47F       @ 0x014

board/aspeed/ast-g5/platform.S TIME_TABLE_DDR4_1600: · line 245

Quoted 2 lines

board/aspeed/ast-g5/platform.S +0 -0

@@ -242,12 +244,20 @@ TIME_TABLE_DDR4_1600:
  Calibration Macro End
  ************************************************************

******************/

Quoted 25 lines

board/aspeed/ast-g5/platform.S +9 -3

+.globl debug_print_dram_init_message
+.globl debug_print_ddr_version
+.globl debug_print_dram_size
+.globl debug_print_ddr_status
+.globl debug_print_ddr_phy_timing
+.globl init_debug_uart
 .globl lowlevel_init
 lowlevel_init:
 
 init_dram:
+    /* Setup a stack in SRAM */
+    ldr   sp, =AST_SRAM_END
     /* save lr */
-    mov   r4, lr
+    push  {lr}
 
     /* Clear AHB bus lock condition */
     ldr   r0, =0x1e600000

@@ -489,82 +499,10 @@ wait_mmc_reset_done:
     ldr   r1, =0x00020000
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e78400c

board/aspeed/ast-g5/platform.S wait_mmc_reset_done: · line 503

Quoted 10 lines

board/aspeed/ast-g5/platform.S +0 ~~-10~~

-    mov   r1, #0x83
-    str   r1, [r0]
-
-    ldr   r0, =0x1e6e202c
-    ldr   r2, [r0]
-    mov   r2, r2, lsr #12
-    tst   r2, #0x01
-    ldr   r0, =0x1e784000
-    moveq r1, #0x0D                              @ Baudrate 115200
-    movne r1, #0x01                              @ Baudrate 115200,

div13

board/aspeed/ast-g5/platform.S wait_mmc_reset_done:

Quoted 3 lines

board/aspeed/ast-g5/platform.S +0 -3

-#ifdef CONFIG_DRAM_UART_38400
-    moveq r1, #0x27                              @ Baudrate 38400
-    movne r1, #0x03                              @ Baudrate 38400 ,

div13

Quoted 57 lines

board/aspeed/ast-g5/platform.S +1 ~~-55~~

-#endif
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784004
-    mov   r1, #0x00
-    str   r1, [r0]
-
-    ldr   r0, =0x1e78400c
-    mov   r1, #0x03
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784008
-    mov   r1, #0x07
-    str   r1, [r0]
+    bl    init_debug_uart
 
-    ldr   r0, =0x1e784000
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
-    mov   r1, #0x41                              @ 'A'
-    str   r1, [r0]
-    mov   r1, #0x4D                              @ 'M'
-    str   r1, [r0]
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x49                              @ 'I'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x74                              @ 't'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    mov   r1, #0x56                              @ 'V'
-    str   r1, [r0]
-    mov   r1, #ASTMMC_INIT_VER
-    mov   r1, r1, lsr #4
-    print_hex_char
-    mov   r1, #ASTMMC_INIT_VER
-    print_hex_char
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    ldr   r0, =0x1e784014
-wait_print:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print
-    ldr   r0, =0x1e784000
-    mov   r1, #0x44                              @ 'D'

board/aspeed/ast-g5/platform.S wait_mmc_reset_done:

Quoted 10 lines

board/aspeed/ast-g5/platform.S +2 -5

-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
+    mov   r0, #ASTMMC_INIT_VER
+    bl    debug_print_dram_init_message
 /* Debug - UART console message */
 
 /***********************************************************

*******************

board/aspeed/ast-g5/platform.S wait_print: · line 586

Quoted 3 lines

board/aspeed/ast-g5/platform.S +0 -0

@@ -647,15 +585,8 @@ wait_print:
  DDR3 Init
  ************************************************************

******************/

Quoted 5 lines

board/aspeed/ast-g5/platform.S +0 -4

 ddr3_init:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x33                              @ '3'
-    str   r1, [r0]

board/aspeed/ast-g5/platform.S wait_print:

Quoted 10 lines

board/aspeed/ast-g5/platform.S +2 -5

-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #3
+    bl    debug_print_ddr_version
 
 #if   defined (CONFIG_DRAM_1333)
     adrl  r5, TIME_TABLE_DDR3_1333               @ Init DRAM parameter

table

board/aspeed/ast-g5/platform.S ddr3_check_dllrdy: · line 797

Quoted 3 lines

board/aspeed/ast-g5/platform.S +0 -0

@@ -865,15 +796,8 @@ ddr3_check_dllrdy:
  DDR4 Init
  ************************************************************

******************/

Quoted 5 lines

board/aspeed/ast-g5/platform.S +0 -4

 ddr4_init:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x34                              @ '4'
-    str   r1, [r0]

board/aspeed/ast-g5/platform.S ddr3_check_dllrdy:

Quoted 10 lines

board/aspeed/ast-g5/platform.S +2 -5

-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #4
+    bl    debug_print_ddr_version
 
 #if   defined (CONFIG_DRAM_1333)
     adrl  r5, TIME_TABLE_DDR4_1333               @ Init DRAM parameter

table

Quoted 279 lines

board/aspeed/ast-g5/platform.S +9 ~~-229~~

@@ -1439,18 +1363,8 @@ check_dram_size_end:
     ldr   r1, =ASTMMC_INIT_DATE
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    str   r3, [r0]
-    mov   r1, #0x47                              @ 'G'
-    str   r1, [r0]
-    mov   r1, #0x62                              @ 'b'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, r3
+    bl    debug_print_dram_size
 
     /* Enable DRAM Cache */
     ldr   r0, =0x1e6e0004

@@ -1520,26 +1434,8 @@ ddr_wait_engine_idle_1:
     b     set_scratch                            @ CBRTest() return(1)
 
 ddr_test_fail:
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x46                              @ 'F'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6C                              @ 'l'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-    ldr   r0, =0x1e784014
-wait_print_0:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_0
-/* Debug - UART console message */
+    mov   r0, #0
+    bl    debug_print_ddr_status
     b     reset_mmc
 
 set_scratch:

@@ -1549,21 +1445,8 @@ set_scratch:
     orr   r1, r1, #0x41
     str   r1, [r0]
 
-/* Debug - UART console message */
-    ldr   r0, =0x1e784000
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x6F                              @ 'o'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x65                              @ 'e'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, #1
+    bl    debug_print_ddr_status
 
     /* Enable VGA display */
     ldr   r0, =0x1e6e202c

@@ -1571,184 +1454,10 @@ set_scratch:
     bic   r1, r1, #0x40
     str   r1, [r0]
 
-/* Debug - UART console message */
-   /* Print PHY timing information */
-    ldr   r0, =0x1e784014
-wait_print_1:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_1
-
-    ldr   r0, =0x1e784000
-    mov   r1, #0x52                              @ 'R'
-    str   r1, [r0]
-    mov   r1, #0x65                              @ 'e'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x64                              @ 'd'
-    str   r1, [r0]
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x6D                              @ 'm'
-    str   r1, [r0]
-    mov   r1, #0x61                              @ 'a'
-    str   r1, [r0]
-    mov   r1, #0x72                              @ 'r'
-    str   r1, [r0]
-    mov   r1, #0x67                              @ 'g'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x2D                              @ '-'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x4C                              @ 'L'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_2:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_2
-
-    ldr   r7, =0x000001FE                        @ divide by 510
-    mov   r8, #10                                @ multiply by 10
-print_DQL_eye_margin:
-    ldr   r0, =0x1e6e03d0
-    ldr   r2, [r0]
-    and   r2, r2, #0xFF
-    ldr   r0, =0x1e784000
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r3, #0x4                               @ print 4 digits
-print_DQL_div_loop:
-    mul   r2, r8, r2
-    cmp   r2, r7
-    blt   print_DQL_div_0
-    mov   r6, #0x0
-print_DQL_div_digit:
-    sub   r2, r2, r7
-    add   r6, r6, #0x1
-    cmp   r2, r7
-    bge   print_DQL_div_digit
-    b     print_DQL_div_n
-
-print_DQL_div_0:
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    b     print_DQL_next
-print_DQL_div_n:
-    add   r1, r6, #0x30                          @ print n
-    str   r1, [r0]
-print_DQL_next:
-    subs  r3, r3, #1
-    beq   print_DQH_eye_margin
-    cmp   r2, #0x0
-    beq   print_DQH_eye_margin
-    b     print_DQL_div_loop
-
-print_DQH_eye_margin:
-    mov   r1, #0x2F                              @ '/'
-    str   r1, [r0]
-    mov   r1, #0x44                              @ 'D'
-    str   r1, [r0]
-    mov   r1, #0x48                              @ 'H'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_3:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_3
-
     ldr   r0, =0x1e6e03d0
     ldr   r2, [r0]
-    mov   r2, r2, lsr #8
-    and   r2, r2, #0xFF
-    ldr   r0, =0x1e784000
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r3, #0x4                               @ print 4 digits
-print_DQH_div_loop:
-    mul   r2, r8, r2
-    cmp   r2, r7
-    blt   print_DQH_div_0
-    mov   r6, #0x0
-print_DQH_div_digit:
-    sub   r2, r2, r7
-    add   r6, r6, #0x1
-    cmp   r2, r7
-    bge   print_DQH_div_digit
-    b     print_DQH_div_n
-
-print_DQH_div_0:
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    b     print_DQH_next
-print_DQH_div_n:
-    add   r1, r6, #0x30                          @ print n
-    str   r1, [r0]
-print_DQH_next:
-    subs  r3, r3, #1
-    beq   print_DQ_eye_margin_last
-    cmp   r2, #0x0
-    beq   print_DQ_eye_margin_last
-    b     print_DQH_div_loop
-
-print_DQ_eye_margin_last:
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x43                              @ 'C'
-    str   r1, [r0]
-    mov   r1, #0x4B                              @ 'K'
-    str   r1, [r0]
-
-    ldr   r0, =0x1e784014
-wait_print_4:
-    ldr   r1, [r0]
-    tst   r1, #0x40
-    beq   wait_print_4
-
-    ldr   r0, =0x1e784000
-    mov   r1, #0x20                              @ ' '
-    str   r1, [r0]
-    mov   r1, #0x28                              @ '('
-    str   r1, [r0]
-    mov   r1, #0x6D                              @ 'm'
-    str   r1, [r0]
-    mov   r1, #0x69                              @ 'i'
-    str   r1, [r0]
-    mov   r1, #0x6E                              @ 'n'
-    str   r1, [r0]
-    mov   r1, #0x3A                              @ ':'
-    str   r1, [r0]
-    mov   r1, #0x30                              @ '0'
-    str   r1, [r0]
-    mov   r1, #0x2E                              @ '.'
-    str   r1, [r0]
-    mov   r1, #0x33                              @ '3'
-    str   r1, [r0]
-    mov   r1, #0x35                              @ '5'
-    str   r1, [r0]
-    mov   r1, #0x29                              @ ')'
-    str   r1, [r0]
-    mov   r1, #0x0D                              @ '\r'
-    str   r1, [r0]
-    mov   r1, #0x0A                              @ '\n'
-    str   r1, [r0]
-/* Debug - UART console message */
+    mov   r0, r2
+    bl    debug_print_ddr_phy_timing
 
 platform_exit:
 #ifdef CONFIG_DRAM_ECC

@@ -1991,9 +1700,5 @@ set_D2PLL:
     ldr   r1, =0xEA
     str   r1, [r0]
 
-    /* restore lr */
-    mov   lr, r4
-
     /* back to arch calling code */
-    mov   pc, lr
-
+    pop   {pc}
--

2.8.0.rc3.226.g39d4020

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*M*axim *S*loyko