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drm/i915: Add ddb size field to device info structure

PATCH In review Deepak M 3 participants 9 messages Sep 14, 2016 – Sep 15, 2016

Subsystems (2)
DRM drivers Intel i915
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Deepak M

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#0 lore raw

PATCH 1/1 drm/i915: Add ddb size field to device info structure

Adding the ddb size into the devide info will avoid platform checks while computing wm.

Suggested-by Ander Conselvan de Oliveira <[email protected]>
Signed-off-by Deepak M <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 13 +------------
 3 files changed, 7 insertions(+), 12 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 1e2dda8..4518ef3 100644
@@ -710,6 +710,7 @@ struct intel_device_info {
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+	u16 ddb_size;
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
drivers/gpu/drm/i915/i915_pci.c +5 -0
index d771870d..687c768 100644
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {

@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 

@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,

@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {

@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
drivers/gpu/drm/i915/intel_pm.c +1 -12
index 6af438f..7eeb73b 100644
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE		896	/* in blocks */
-#define BXT_DDB_SIZE		512
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*

@@ -3057,11 +3050,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	else
 		*num_active = hweight32(dev_priv->active_crtcs);
 
-	if (IS_BROXTON(dev))
-		ddb_size = BXT_DDB_SIZE;
-	else
-		ddb_size = SKL_DDB_SIZE;
-
+	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
 	/*
Signature · 6 lines
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CI
#1 lore raw

✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure

== Series Details ==

== Series Details ==

Series: drm/i915: Add ddb size field to device info structure
URL : https://patchwork.freedesktop.org/series/12427/
State : success

== Summary ==

Series 12427v1 drm/i915: Add ddb size field to device info structure
https://patchwork.freedesktop.org/api/1.0/series/12427/revisions/1/mbox/

Test kms_pipe_crc_basic:

        Subgroup hang-read-crc-pipe-c:
                skip       -> PASS       (fi-hsw-4770r)
fi-bsw-n3050     total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-hsw-4770k     total:244  pass:226  dwarn:0   dfail:0   fail:0   skip:18 
fi-hsw-4770r     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650       total:244  pass:183  dwarn:0   dfail:0   fail:1   skip:60 
fi-ivb-3520m     total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:221  dwarn:0   dfail:0   fail:1   skip:22 
fi-skl-6700k     total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-snb-2520m     total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37

Results at /archive/results/CI_IGT_test/Patchwork_2527/

208290026552464713d3897ab5d649f4445d5513 drm-intel-nightly: 2016y-09m-13d-14h-45m-32s UTC integration manifest 838a0e3 drm/i915: Add ddb size field to device info structure

_______________________________________________
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[email protected]
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maintainer Reviewed-by on v1 1/1
#2 lore raw
In reply to Deepak M
Quoted 16 lines · Deepak M

Adding the ddb size into the devide info will avoid platform checks while computing wm.

Suggested-by Ander Conselvan de Oliveira <[email protected]>
Signed-off-by Deepak M <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 13 +------------
 3 files changed, 7 insertions(+), 12 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +0 -0
index 1e2dda8..4518ef3 100644

drivers/gpu/drm/i915/i915_drv.h struct intel_device_info { · line 713

Quoted 4 lines
drivers/gpu/drm/i915/i915_drv.h +1 -0
@@ -710,6 +710,7 @@ struct intel_device_info {
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+	u16 ddb_size;

This could use the /* in blocks */ comment.

Quoted 66 lines
drivers/gpu/drm/i915/i915_drv.h +0 -0
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
drivers/gpu/drm/i915/i915_pci.c +5 -0
index d771870d..687c768 100644
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {

@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 

@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,

@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {

@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
drivers/gpu/drm/i915/intel_pm.c +0 -7
index 6af438f..7eeb73b 100644
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE		896	/* in blocks */
-#define BXT_DDB_SIZE		512
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*

drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, · line 3053

Quoted 9 lines
drivers/gpu/drm/i915/intel_pm.c +1 -5
@@ -3057,11 +3050,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	else
 		*num_active = hweight32(dev_priv->active_crtcs);
 
-	if (IS_BROXTON(dev))
-		ddb_size = BXT_DDB_SIZE;
-	else
-		ddb_size = SKL_DDB_SIZE;
-
+	ddb_size = INTEL_INFO(dev_priv)->ddb_size;

I'd perhaps stick a WARN_ON(ddb_size == 0) here.

With those fixed,

Reviewed-by Jani Nikula <[email protected]>
Quoted 3 lines
drivers/gpu/drm/i915/intel_pm.c +0 -0
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
 	/*
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#3 lore raw

PATCH 1/1 drm/i915: Add ddb size field to device info structure

Adding the ddb size into the devide info will avoid platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)

Suggested-by Ander Conselvan de Oliveira <[email protected]>
Signed-off-by Deepak M <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 15 +++------------
 3 files changed, 9 insertions(+), 12 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 1e2dda8..6014c3a 100644
@@ -710,6 +710,7 @@ struct intel_device_info {
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+	u16 ddb_size; /* in blocks */
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
drivers/gpu/drm/i915/i915_pci.c +5 -0
index d771870d..687c768 100644
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {

@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 

@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,

@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {

@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
drivers/gpu/drm/i915/intel_pm.c +3 -12
index 6af438f..9c5861e 100644
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE		896	/* in blocks */
-#define BXT_DDB_SIZE		512
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*

@@ -3057,13 +3050,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	else
 		*num_active = hweight32(dev_priv->active_crtcs);
 
-	if (IS_BROXTON(dev))
-		ddb_size = BXT_DDB_SIZE;
-	else
-		ddb_size = SKL_DDB_SIZE;
-
+	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
+	WARN_ON(ddb_size == 0);
+
 	/*
 	 * If the state doesn't change the active CRTC's, then there's
 	 * no need to recalculate; the existing pipe allocation limits
Signature · 6 lines
1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
maintainer
#4 lore raw
Quoted 90 lines · Deepak M

Adding the ddb size into the devide info will avoid platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)

Suggested-by Ander Conselvan de Oliveira <[email protected]>
Signed-off-by Deepak M <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 15 +++------------
 3 files changed, 9 insertions(+), 12 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 1e2dda8..6014c3a 100644
@@ -710,6 +710,7 @@ struct intel_device_info {
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+	u16 ddb_size; /* in blocks */
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
drivers/gpu/drm/i915/i915_pci.c +5 -0
index d771870d..687c768 100644
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {

@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 

@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,

@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {

@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
drivers/gpu/drm/i915/intel_pm.c +0 -7
index 6af438f..9c5861e 100644
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE		896	/* in blocks */
-#define BXT_DDB_SIZE		512
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*

@@ -3057,13 +3050,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	else
 		*num_active = hweight32(dev_priv->active_crtcs);

drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, · line 3056

Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +2 -5
 
-	if (IS_BROXTON(dev))
-		ddb_size = BXT_DDB_SIZE;
-	else
-		ddb_size = SKL_DDB_SIZE;
-
+	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
+	WARN_ON(ddb_size == 0);

Please be careful. You have to stick the WARN_ON *before* you decrement by 4.

BR,
Jani.

Quoted 4 lines
drivers/gpu/drm/i915/intel_pm.c +1 -0
+
 	/*
 	 * If the state doesn't change the active CRTC's, then there's
 	 * no need to recalculate; the existing pipe allocation limits
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#5 lore raw

PATCH 1/1 drm/i915: Add ddb size field to device info structure

Adding the ddb size into the devide info will avoid platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)
v3: Added WARN_ON at the right place.(Jani)

Suggested-by Ander Conselvan de Oliveira <[email protected]>
Signed-off-by Deepak M <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 13 ++-----------
 3 files changed, 8 insertions(+), 11 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 1e2dda8..6014c3a 100644
@@ -710,6 +710,7 @@ struct intel_device_info {
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+	u16 ddb_size; /* in blocks */
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
drivers/gpu/drm/i915/i915_pci.c +5 -0
index d771870d..687c768 100644
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {

@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 

@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,

@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {

@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
drivers/gpu/drm/i915/intel_pm.c +2 -11
index 6af438f..2df06b7 100644
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE		896	/* in blocks */
-#define BXT_DDB_SIZE		512
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*

@@ -3057,10 +3050,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	else
 		*num_active = hweight32(dev_priv->active_crtcs);
 
-	if (IS_BROXTON(dev))
-		ddb_size = BXT_DDB_SIZE;
-	else
-		ddb_size = SKL_DDB_SIZE;
+	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+	WARN_ON(ddb_size == 0);
 
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
Signature · 6 lines
1.9.1

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#6 lore raw
Quoted 8 lines · Deepak M

Adding the ddb size into the devide info will avoid platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)
v3: Added WARN_ON at the right place.(Jani)

Suggested-by Ander Conselvan de Oliveira <[email protected]>
Signed-off-by Deepak M <[email protected]>

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.

Quoted 92 lines
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 13 ++-----------
 3 files changed, 8 insertions(+), 11 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 1e2dda8..6014c3a 100644
@@ -710,6 +710,7 @@ struct intel_device_info {
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+	u16 ddb_size; /* in blocks */
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
drivers/gpu/drm/i915/i915_pci.c +5 -0
index d771870d..687c768 100644
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {

@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 

@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,

@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {

@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
drivers/gpu/drm/i915/intel_pm.c +2 -11
index 6af438f..2df06b7 100644
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE		896	/* in blocks */
-#define BXT_DDB_SIZE		512
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*

@@ -3057,10 +3050,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	else
 		*num_active = hweight32(dev_priv->active_crtcs);
 
-	if (IS_BROXTON(dev))
-		ddb_size = BXT_DDB_SIZE;
-	else
-		ddb_size = SKL_DDB_SIZE;
+	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+	WARN_ON(ddb_size == 0);
 
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center
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CI
#7 lore raw

✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev2)

In reply to Deepak M
== Series Details ==

== Series Details ==

Series: drm/i915: Add ddb size field to device info structure (rev2)
URL : https://patchwork.freedesktop.org/series/12427/
State : success

== Summary ==

Series 12427v2 drm/i915: Add ddb size field to device info structure
https://patchwork.freedesktop.org/api/1.0/series/12427/revisions/2/mbox/

fi-bsw-n3050     total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-hsw-4770k     total:244  pass:226  dwarn:0   dfail:0   fail:0   skip:18 
fi-hsw-4770r     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650       total:244  pass:183  dwarn:0   dfail:0   fail:1   skip:60 
fi-ivb-3520m     total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:221  dwarn:0   dfail:0   fail:1   skip:22 
fi-skl-6700k     total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-snb-2520m     total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37

Results at /archive/results/CI_IGT_test/Patchwork_2529/

0c7c6ebb924db723ecabc2521e2afa71beeec471 drm-intel-nightly: 2016y-09m-14d-07h-41m-42s UTC integration manifest 67b040a drm/i915: Add ddb size field to device info structure

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CI
#8 lore raw

✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev3)

In reply to Deepak M
== Series Details ==

== Series Details ==

Series: drm/i915: Add ddb size field to device info structure (rev3)
URL : https://patchwork.freedesktop.org/series/12427/
State : success

== Summary ==

Series 12427v3 drm/i915: Add ddb size field to device info structure
https://patchwork.freedesktop.org/api/1.0/series/12427/revisions/3/mbox/

Test gem_exec_suspend:

        Subgroup basic-s3:
                incomplete -> PASS       (fi-hsw-4770k)
fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-byt-j1900     total:244  pass:210  dwarn:2   dfail:0   fail:1   skip:31 
fi-byt-n2820     total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770k     total:244  pass:226  dwarn:0   dfail:0   fail:0   skip:18 
fi-hsw-4770r     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650       total:244  pass:183  dwarn:0   dfail:0   fail:1   skip:60 
fi-ivb-3520m     total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:221  dwarn:0   dfail:0   fail:1   skip:22 
fi-skl-6700k     total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hq    total:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m     total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37

Results at /archive/results/CI_IGT_test/Patchwork_2539/

9aa8c0cdbc076bcc0486d7a31922a0f77c032fe7 drm-intel-nightly: 2016y-09m-14d-09h-19m-25s UTC integration manifest a0f1e3e drm/i915: Add ddb size field to device info structure

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