ddr: altera: Configuring SDRAM extra cycles timing parameters

PATCH Superseded Chin Liang See 2 participants 4 messages Sep 20, 2016 – Sep 21, 2016

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/socfpga architecture

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Chin Liang See

author

2016-09-20 06:05 UTC #0 lore raw

PATCH v2 1/1 ddr: altera: Configuring SDRAM extra cycles timing parameters

To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface

Signed-off-by Chin Liang See <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

---
Changes for v2
- Removed v1 patches #2 to #9 as no boards are using LPDDR2

---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
 arch/arm/mach-socfpga/qts-filter.sh        | 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +++++++++
 drivers/ddr/altera/sdram.c                 | 3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)

arch/arm/mach-socfpga/include/mach/sdram.h +7 -1

index f12bb84..b11228f 100644
@@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
 	u32	dram_timing4;	/* 0x10 */
 	u32	lowpwr_timing;
 	u32	dram_odt;
-	u32	__padding0[4];
+	u32	extratime1;
+	u32	__padding0[3];
 	u32	dram_addrw;	/* 0x2c */
 	u32	dram_if_width;	/* 0x30 */
 	u32	dram_dev_width;

@@ -88,6 +89,7 @@ struct socfpga_sdram_config {
 	u32	dram_timing4;
 	u32	lowpwr_timing;
 	u32	dram_odt;
+	u32	extratime1;
 	u32	dram_addrw;
 	u32	dram_if_width;
 	u32	dram_dev_width;

@@ -427,6 +429,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
 /* Field instance: sdr::ctrlgrp::dramsts                                   */
 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1                             */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
 
 /* SDRAM width macro for configuration with ECC */
 #define SDRAM_WIDTH_32BIT_WITH_ECC	40

arch/arm/mach-socfpga/qts-filter.sh +0 -1

index 050d6ba..1148a71 100755
@@ -119,7 +119,7 @@ EOF
 # Filter out only the macros which are actually used by the code
 #
 grep_sdram_config() {
-	egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CO!
 NFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP!
 |CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR

 |CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR
TCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_A!
 CTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_RE!
 FRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_D
ATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_T!
 O_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"

}

arch/arm/mach-socfpga/wrap_sdram_config.c +9 -0

index 31cc7de..d72f5e1 100644
@@ -81,6 +81,15 @@ static const struct socfpga_sdram_config sdram_config = {
 			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
 		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+#ifdef CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
+	.extratime1 =
+	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
+	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
+(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
+#endif
 	.dram_addrw =
 		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|

drivers/ddr/altera/sdram.c +3 -0

index 7e4606d..e74c5b0 100644
@@ -418,6 +418,9 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 
 	debug("Configuring DRAMODT\n");
 	writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+
+	debug("Configuring EXTRATIME1\n");
+	writel(cfg->extratime1, &sdr_ctrl->extratime1);
 }
 
 /**

Signature · 1 line

2.2.2

Marek Vasut

2016-09-21 01:20 UTC #1 lore raw

PATCH v2 1/1 ddr: altera: Configuring SDRAM extra cycles timing parameters

Quoted 10 lines · Chin Liang See

To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
Changes for v2
- Removed v1 patches #2 to #9 as no boards are using LPDDR2

Quoted 7 lines

---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
 arch/arm/mach-socfpga/qts-filter.sh        | 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +++++++++
 drivers/ddr/altera/sdram.c                 | 3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)

[...]

I'd really like to avoid the ifdef, can we do that (fix all boards to set the register to zero) ? Otherwise I'm fine with the patch.

Signature · 2 lines

Best regards,
Marek Vasut

Chin Liang See

author

2016-09-21 01:53 UTC #2 lore raw

PATCH v2 1/1 ddr: altera: Configuring SDRAM extra cycles timing parameters

Quoted 20 lines · Marek Vasut

Quoted 11 lines · Chin Liang See
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
Changes for v2
- Removed v1 patches #2 to #9 as no boards are using LPDDR2
Quoted 7 lines
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
 arch/arm/mach-socfpga/qts-filter.sh        | 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +++++++++
 drivers/ddr/altera/sdram.c                 | 3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)
[...]

Quoted 3 lines

I'd really like to avoid the ifdef, can we do that (fix all boards to set the register to zero) ? Otherwise I'm fine with the patch.

Ok I know where you come from. ifdef will cause some test challenge in term of coverage. In this case, let me fix all boards to zeroes.

Thanks
Chin Liang

Quoted 1 line

Marek Vasut

2016-09-21 09:55 UTC #3 lore raw

PATCH v2 1/1 ddr: altera: Configuring SDRAM extra cycles timing parameters

Quoted 21 lines · Chin Liang See

Quoted 20 lines · Marek Vasut
Quoted 18 lines · Chin Liang See
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface
Signed-off-by Chin Liang See <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
Changes for v2
- Removed v1 patches #2 to #9 as no boards are using LPDDR2
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
 arch/arm/mach-socfpga/qts-filter.sh        | 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +++++++++
 drivers/ddr/altera/sdram.c                 | 3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)
[...]

Quoted 6 lines

Quoted 3 lines
I'd really like to avoid the ifdef, can we do that (fix all boards to set the register to zero) ? Otherwise I'm fine with the patch.
Ok I know where you come from. ifdef will cause some test challenge in term of coverage. In this case, let me fix all boards to zeroes.

Thanks

Signature · 2 lines

Best regards,
Marek Vasut