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Patch "pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33" has been added to the 4.7-stable tree

PATCH [email protected] 1 participant 1 message Sep 22, 2016

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Stable branch Arm/Allwinner sunXi SoC support Pin control
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This is a note to let you know that I've just added the patch titled

pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33

to the 4.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     pinctrl-sunxi-fix-uart1-cts-rts-pins-at-pg-on-a23-a33.patch

and it can be found in the queue-4.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From 486095fae3a8a6b1ae07c51844699d9bd5cfbebc Mon Sep 17 00:00:00 2001

From: Icenowy Zheng <[email protected]>
Date: Tue, 23 Aug 2016 13:58:25 +0800
Subject: pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33

From: Icenowy Zheng <[email protected]>

commit 486095fae3a8a6b1ae07c51844699d9bd5cfbebc upstream.

PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33 datasheets. However, the function is wrongly named "uart2" in the pinctrl driver. This patch fixes this by modifying them to be named "uart1".

Signed-off-by Icenowy Zheng <[email protected]>
Acked-by Maxime Ripard <[email protected]>
Signed-off-by Linus Walleij <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
---
 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c |    4 ++--
 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c +2 -2
@@ -485,12 +485,12 @@ static const struct sunxi_desc_pin sun8i
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
 		  SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)),	/* PG_EINT8 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
 		  SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)),	/* PG_EINT9 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +2 -2
@@ -407,12 +407,12 @@ static const struct sunxi_desc_pin sun8i
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
 		  SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)),	/* PG_EINT8 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
 		  SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)),	/* PG_EINT9 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),

Patches currently in stable-queue which might be from [email protected] are

queue-4.7/pinctrl-sunxi-fix-uart1-cts-rts-pins-at-pg-on-a23-a33.patch