aspeed/g5: Device Tree for ast2500 and eval board, I2C driver
Subsystems (4)
PATCH 1/1 aspeed/g5: Device Tree for ast2500 and eval board, I2C driver
From: Maxim Sloyko <[email protected]>
The driver is limited: only single master mode is supported and only byte-by-byte reads and writes are supported, no DMA or Pool Buffers.
Also, pin function configuration is performed by the I2C driver, because there is no pinctrl driver at the moment.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 ++ arch/arm/dts/aspeed-g5.dtsi | 392 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 + arch/arm/include/asm/arch-aspeed/regs-scu.h | 74 +++--- arch/arm/mach-aspeed/ast-scu.c | 31 ++- board/aspeed/ast-g5/ast-g5.c | 2 +- configs/ast_g5_defconfig | 4 +- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 155 +++++++++++ 12 files changed, 970 insertions(+), 37 deletions(-) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsi create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h
arch/arm/dts/Makefile +2 -0
@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-y += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here
arch/arm/dts/aspeed-g5-evb.dts new file +28 -0
@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};
arch/arm/dts/aspeed-g5.dtsi new file +392 -0
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arch/arm/include/asm/arch-aspeed/ast_scu.h +6 -0
@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );
@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif
arch/arm/include/asm/arch-aspeed/regs-scu.h +40 -34
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arch/arm/mach-aspeed/ast-scu.c +30 -1
@@ -250,6 +250,7 @@ u32 ast_get_ahbclk(void) return ((hpll / axi_div) / ahb_div); } +#else /* ! AST_SOC_G5 */ u32 ast_get_h_pll_clk (void )
@@ -318,6 +319,14 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +u32 apb_div =SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {
@@ -394,7 +403,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ;
@@ -496,3 +505,23 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 num) +{ +/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (num <3 ) { +#ifdef AST_SOC_G5 +if (num ==1 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA1 |SCU_FUN_PIN_SCL1 ); + }else { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA2 |SCU_FUN_PIN_SCL2 ); + } +#endif + }else { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 ,SCU_FUN_PIN_I2C (num)); + } +}
board/aspeed/ast-g5/ast-g5.c +1 -1
@@ -36,6 +36,7 @@#include <common.h> #include <netdev.h> #include <asm/arch/ast_scu.h> +#include <asm/arch/regs-scu.h> #include <asm/arch/ast-sdmc.h> #include <asm/io.h>
@@ -52,7 +53,6 @@ int board_init(void) {/* adress of boot parameters */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ; - gd->flags =0 ;return 0 ; }
configs/ast_g5_defconfig +3 -1
@@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_DEFAULT_DEVICE_TREE="aspeed-g5" CONFIG_TARGET_AST_G5=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y
@@ -6,4 +7,5 @@ CONFIG_SYS_PROMPT="ast# " CONFIG_CMD_SAVEENV=y CONFIG_CMD_FLASH=y CONFIG_CMD_PING=y -CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP=y +CONFIG_SYS_I2C_ASPEED=y
drivers/i2c/Kconfig +6 -0
@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. +config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2C
drivers/i2c/Makefile +1 -0
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
drivers/i2c/ast_i2c.c new file +306 -0
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drivers/i2c/ast_i2c.h new file +155 -0
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Signature · 1 line
2.8.0.rc3.226.g39d4020
Ping!
Quoted 1,265 lines · On Mon, Sep 19, 2016 at 10:26 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
The driver is limited: only single master mode is supported and only byte-by-byte reads and writes are supported, no DMA or Pool Buffers.
Also, pin function configuration is performed by the I2C driver, because there is no pinctrl driver at the moment.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 ++ arch/arm/dts/aspeed-g5.dtsi | 392 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 + arch/arm/include/asm/arch-aspeed/regs-scu.h | 74 +++--- arch/arm/mach-aspeed/ast-scu.c | 31 ++- board/aspeed/ast-g5/ast-g5.c | 2 +- configs/ast_g5_defconfig | 4 +- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 155 +++++++++++ 12 files changed, 970 insertions(+), 37 deletions(-) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsi create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.harch/arm/dts/Makefile +2
-0@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-y += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags herearch/arm/dts/aspeed-g5-evb. renamed from arch/arm/dts/aspeed-g5-evb.dts +0
-0dts
new file mode 100644
index 0000000..95dc77aarch/arm/dts/aspeed-g5-evb.dts new file +28
-0@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};arch/arm/dts/aspeed-g5.dtsi new file +107
-0@@ -0,0 +1,392 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176", "arm,armv6"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinmux: pinmux@1e6e2000 { + reg= <0x1e6e2000 0x1000>; + compatible = "aspeed,ast2500-pinctrl"; + }; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2500-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + aspeed-g5-interface; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + aspeed-g5-interface; + no-hw-checksum; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2500-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers onlyone
arch/arm/dts/aspeed-g5.dtsi new file +104
-0+ // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + ibt: ibt@1e789140 { + compatible = "aspeed,bt-host"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x1c>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@1e787000 { + compatible = "ns16550a"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + i2c: i2c@1e78a000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + compatible = "aspeed,ast2500-i2c-controller";
arch/arm/dts/aspeed-g5.dtsi new file +13
-0+ reg = <0x1e78a000 0x40>; + ranges = <0 0x1e78a000 0x1000>; + interrupts = <12>; + clocks = <&clk_apb>; + buffer = <0x1e78a200 0x10>; + clock-ranges; + interrupt-controller; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +13
-0+ bus = <0>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <0>; + interrupt-parent = <&i2c>; + buffer; + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <1>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <1>; + buffer = <0x10 0x10>; + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xC0 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <2>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <2>; + buffer = <0x20 0x10>; + }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <3>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <3>; + buffer = <0x30 0x10>; + }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x140 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <4>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <4>; + buffer = <0x40 0x10>; + }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <5>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <5>; + buffer = <0x50 0x10>; + }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1C0 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <6>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <6>; + buffer = <0x60 0x10>; + }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <7>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <7>; + buffer = <0x70 0x10>; + }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x340 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <8>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <8>; + buffer = <0x80 0x10>; + }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <9>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <9>; + buffer = <0x90 0x10>; + }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3c0 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <10>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <10>; + buffer = <0xa0 0x10>; + }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <11>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <11>; + buffer = <0xb0 0x10>; + }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x440 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <12>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <12>; + buffer = <0xc0 0x10>; + }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x40>; + compatible ="aspeed,ast2500-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +11
-0+ bus = <13>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <13>; + buffer = <0xd0 0x10>; + }; + + }; + }; + }; +};arch/arm/include/asm/arch-aspeed/ast_scu.h +6
-0@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif arch/arm/include/asm/arch-aspeed/regs-scu.h +2
-2@@ -10,8 +10,8 @@* 1. 2012/12/29 Ryan Chen Create * ************************************************************ ********************/ -#ifndef __AST_SCU_H -#define __AST_SCU_H 1 +#ifndef __AST_REGS_SCU_H +#define __AST_REGS_SCU_H 1#include <asm/arch/aspeed.h> @@ -830,49 +830,50 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */
#defineSCU_FUN_PIN_SPICS1(0x1<< 31)
#defineSCU_FUN_PIN_LPC_PLUS(0x1<< 30)arch/arm/include/asm/arch-aspeed/regs-scu.h +33
-32-#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21) +#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3)) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUN_PIN_MII2_TX_DRIV (x) (x << 10) +#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUN_PIN_MII1_TX_DRIV (x) (x << 8) +#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)#define MII_NORMAL_DRIV 0x0#define MII_HIGH_DRIV 0x2 -#define SCU_FUC_PIN_UART6 (0x1 << 7) -#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) -#define SCU_FUC_PIN_DIGI_V_OUT (x) (x) -#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3) +#define SCU_FUN_PIN_UART6 (0x1 << 7) +#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUN_PIN_DIGI_V_OUT (x) (x) +#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)#define VIDEO_DISABLE 0x0#define VIDEO_12BITS 0x1#define VIDEO_24BITS 0x2//#define VIDEO_DISABLE 0x3 -#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) -#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3) +#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3) -#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) -#define SCU_FUC_PIN_SD2 (0x1 << 1) -#define SCU_FUC_PIN_SD1 (0x1 << 0) +#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUN_PIN_SD2 (0x1 << 1) +#define SCU_FUN_PIN_SD1 (0x1 << 0)/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/
arch/arm/include/asm/arch-aspeed/regs-scu.h +5
-0@@ -914,6 +915,11 @@#define SCU_FUN_PIN_ROMA4 (0x1 << 18)#define SCU_FUN_PIN_ROMA3 (0x1 << 17)#define SCU_FUN_PIN_ROMA2 (0x1 << 16) +/* AST2500 only */ +#define SCU_FUN_PIN_SDA2 (0x1 << 15) +#define SCU_FUN_PIN_SCL2 (0x1 << 14) +#define SCU_FUN_PIN_SDA1 (0x1 << 13) +#define SCU_FUN_PIN_SCL1 (0x1 << 12)/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */
#defineSCU_FUN_PIN_ROMA21(0x1<< 3)arch/arm/mach-aspeed/ast- renamed from arch/arm/mach-aspeed/ast-scu.c +0
-0
scu.c
index 0cc0d67..31cea60 100644arch/arm/mach-aspeed/ast-scu.c +21
-1@@ -250,6 +250,7 @@ u32 ast_get_ahbclk(void) return ((hpll / axi_div) / ahb_div); } +#else /* ! AST_SOC_G5 */ u32 ast_get_h_pll_clk (void )@@ -318,6 +319,14 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +u32 apb_div =SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {@@ -394,7 +403,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ;@@ -496,3 +505,23 @@ void ast_scu_get_who_init_dram(void) break; } } + +void ast_scu_enable_i2c(u8 num) +{ + /* Enable I2C Controllers */ + clrbits_le32(AST_SCU_BASE + AST_SCU_RESET, SCU_RESET_I2C); + + if (num < 3) { +#ifdef AST_SOC_G5 + if (num == 1) { + setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8, + SCU_FUN_PIN_SDA1 |
SCU_FUN_PIN_SCL1);arch/arm/mach-aspeed/ast-scu.c +3
-0+ }else { + setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8, + SCU_FUN_PIN_SDA2 |
SCU_FUN_PIN_SCL2);arch/arm/mach-aspeed/ast-scu.c +4
-0+ } +#endif + }else { + setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL5,
SCU_FUN_PIN_I2C(num));arch/arm/mach-aspeed/ast-scu.c +2
-0+ } +}board/aspeed/ast-g5/ast-g5.c +1
-1@@ -36,6 +36,7 @@#include <common.h> #include <netdev.h> #include <asm/arch/ast_scu.h> +#include <asm/arch/regs-scu.h> #include <asm/arch/ast-sdmc.h> #include <asm/io.h> @@ -52,7 +53,6 @@ int board_init(void) {/* adress of boot parameters */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ; - gd->flags =0 ;return 0 ; }configs/ast_g5_defconfig +3
-1@@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_DEFAULT_DEVICE_TREE="aspeed-g5" CONFIG_TARGET_AST_G5=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y@@ -6,4 +7,5 @@ CONFIG_SYS_PROMPT="ast# " CONFIG_CMD_SAVEENV=y CONFIG_CMD_FLASH=y CONFIG_CMD_PING=y -CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP=y +CONFIG_SYS_I2C_ASPEED=ydrivers/i2c/Kconfig +0
-0@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. Thiscontroller is
e.g. used by Xilinx Zynq.drivers/i2c/Kconfig +6
-0+config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2Cdrivers/i2c/Makefile +1
-0@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.odrivers/i2c/ast_i2c.c new file +53
-0@@ -0,0 +1,306 @@ +/* +* Copyright (C) 2016 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> + +#include <asm/arch/ast_scu.h> +#include <asm/arch/regs-scu.h> +#include <asm/io.h> + +#include "ast_i2c.h" + +#define I2C_TIMEOUT_US (100000) +#define I2C_SLEEP_STEP (20) +#define EI2C_TIMEOUT (1001) + +DECLARE_GLOBAL_DATA_PTR ; + +struct ast_i2c { +u32 id; +struct ast_i2c_regs *regs; +int speed; +}; + +#define RETURN_IF_ERROR (expr) do {\ + int err = (expr);\ + if (err < 0) {\ + return err;\ + }\ +} while (0) + +static u32 __get_clk_reg_val (u32 divider_ratio) +{ +unsigned int inc =0 , div; +u32 scl_low, scl_high, data; + +for (div =0 ; divider_ratio >=16 ; div++) { + inc |= (divider_ratio &1 ); + divider_ratio >>=1 ; + } + divider_ratio += inc; + scl_low = (divider_ratio >>1 ) -1 ; + scl_high = divider_ratio - scl_low -2 ; + data =0x77700300 | (scl_high <<16 ) | (scl_low <<12 ) | div; +return data; +} + +static inline void __ast_i2c_clear_interrupts(struct ast_i2c_regs
*i2c_base)drivers/i2c/ast_i2c.c new file +14
-0+{ +writel (~0 , &i2c_base->isr); +} + +static int __ast_i2c_init_bus (struct ast_i2c *i2c_bus) +{ +/* Reset device */ +writel (0 , &i2c_bus->regs->fcr); +/* Enable Master Mode. Assuming single-master. */ +debug ("Enable Master for %p\n" , i2c_bus->regs); + setbits_le32(&i2c_bus->regs->fcr, + AST_I2CD_MASTER_EN + | AST_I2CD_M_SDA_LOCK_EN + | AST_I2CD_MULTI_MASTER_DIS |
AST_I2CD_M_SCL_DRIVE_EN);drivers/i2c/ast_i2c.c new file +27
-0+debug ("FCR: %p\n" , &i2c_bus->regs->fcr); +/* Enable Interrupts */ +writel (AST_I2CD_INTR_TX_ACK + |AST_I2CD_INTR_TX_NAK + |AST_I2CD_INTR_RX_DONE + |AST_I2CD_INTR_BUS_RECOVER_DONE + |AST_I2CD_INTR_NORMAL_STOP + |AST_I2CD_INTR_ABNORMAL , &i2c_bus->regs->icr); +return 0 ; +} + +static int ast_i2c_probe (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); + +debug ("Enabling I2C%u \n" , dev->seq); +ast_scu_enable_i2c (dev->seq); + + i2c_bus->id = dev->seq; +struct ast_i2c_regs *i2c_base = + (struct ast_i2c_regs *)dev_get_addr (dev); + i2c_bus->regs = i2c_base; + +return __ast_i2c_init_bus (i2c_bus); +} + +static inline int __ast_i2c_wait_isr(struct ast_i2c_regs *i2c_base, u32flag)
drivers/i2c/ast_i2c.c new file +46
-0+{ +int timeout =I2C_TIMEOUT_US ; +while (!(readl (&i2c_base->isr) & flag) && timeout >0 ) { +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +__ast_i2c_clear_interrupts (i2c_base); +if (timeout <=0 ) +return -EI2C_TIMEOUT ; +return 0 ; +} + +static inline int __ast_i2c_send_stop (struct ast_i2c_regs *i2c_base) +{ +writel (AST_I2CD_M_STOP_CMD , &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_isr + (i2c_base,AST_I2CD_INTR_NORMAL_STOP )); +return 0 ; +} + +static inline int __ast_i2c_wait_tx (struct ast_i2c_regs *i2c_base) +{ +int timeout =I2C_TIMEOUT_US ; +u32 flag =AST_I2CD_INTR_TX_ACK |AST_I2CD_INTR_TX_NAK ; +u32 status =readl (&i2c_base->isr) & flag; +while (!status && timeout >0 ) { + status =readl (&i2c_base->isr) & flag; +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +int ret =0 ; +if (status ==AST_I2CD_INTR_TX_NAK ) { + ret = -EREMOTEIO ; + } + +if (timeout <=0 ) { + ret = -EI2C_TIMEOUT ; + } + +__ast_i2c_clear_interrupts (i2c_base); +return ret; +} + +static inline int __ast_i2c_start_txn(struct ast_i2c_regs *i2c_base, u8devaddr)
drivers/i2c/ast_i2c.c new file +9
-0+{ +/* Start and Send Device Address */ +writel (devaddr, &i2c_base->trbbr); +writel (AST_I2CD_M_START_CMD |AST_I2CD_M_TX_CMD , &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_tx (i2c_base)); +return 0 ; +} + +static int __ast_i2c_read_data(struct ast_i2c *i2c_bus, u8 chip, u8*buffer,
drivers/i2c/ast_i2c.c new file +17
-0+ int len) +{ +int i2c_error =0 ; +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + + i2c_error =__ast_i2c_start_txn (i2c_base, (chip <<1 ) |I2C_M_RD ); + +if (!i2c_error) { +u32 i2c_cmd =AST_I2CD_M_RX_CMD ; +for (; len >0 ; len--, buffer++) { +if (len ==1 ) { + i2c_cmd |=AST_I2CD_M_S_RX_CMD_LAST ; + } +writel (i2c_cmd, &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_isr + (i2c_base,AST_I2CD_INTR_RX_DONE )); + *buffer = AST_I2CD_RX_DATA_BUF_GET(
readl(&i2c_base->trbbr));drivers/i2c/ast_i2c.c new file +9
-0+ } +__ast_i2c_clear_interrupts (i2c_base); + } +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base)); + +return i2c_error; +} + +static int __ast_i2c_write_data(struct ast_i2c *i2c_bus, u8 chip, u8*buffer,
drivers/i2c/ast_i2c.c new file +36
-0+ int len) +{ +int i2c_error =0 ; +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + + i2c_error =__ast_i2c_start_txn (i2c_base, (chip <<1 )); +for (; len >0 &&0 == i2c_error; len--, buffer++) { +writel (*buffer, &i2c_base->trbbr); +writel (AST_I2CD_M_TX_CMD , &i2c_base->csr); + i2c_error =__ast_i2c_wait_tx (i2c_base); + } +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base)); +return i2c_error; +} + +static int ast_i2c_deblock (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +u32 csr =readl (&i2c_base->csr); +debug ("Bus hung (%x), attempting recovery\n" , csr); + +bool sda_high = csr &AST_I2CD_SDA_LINE_STS ; +bool scl_high = csr &AST_I2CD_SCL_LINE_STS ; +if (sda_high && scl_high) { +/* Bus is idle, no deblocking needed. */ +return 0 ; + }else if (sda_high) { +/* Send stop command */ +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base)); + }else if (scl_high) { +/* Possibly stuck slave */ +writel (AST_I2CD_BUS_RECOVER_CMD , &i2c_base->csr); + RETURN_IF_ERROR(__ast_i2c_wait_isr + (i2c_base, AST_I2CD_INTR_BUS_RECOVER_DONE));
drivers/i2c/ast_i2c.c new file +9
-0+ }else { +/* Just try to reinit the device. */ +RETURN_IF_ERROR (__ast_i2c_init_bus (i2c_bus)); + } + +return 0 ; +} + +static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, intnmsgs)
drivers/i2c/ast_i2c.c new file +11
-0+{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +int ret; + +debug ("i2c_xfer: %d messages\n" , nmsgs); +for (; nmsgs >0 ; nmsgs--, msg++) { +/* TODO: use this for repeated start */ +bool next_is_read = nmsgs >1 && (msg[1 ].flags &I2C_M_RD ); + +if (msg->flags &I2C_M_RD ) { + debug("i2c_read: chip=0x%x, len=0x%x,flags=0x%x\n",
drivers/i2c/ast_i2c.c new file +3
-0+ msg->addr, msg->len, msg->flags); + ret = + __ast_i2c_read_data(i2c_bus, msg->addr,
msg->buf,drivers/i2c/ast_i2c.c new file +3
-0+ msg->len); + }else { + debug("i2c_write: chip=0x%x, len=0x%x,flags=0x%x\n",
drivers/i2c/ast_i2c.c new file +3
-0+ msg->addr, msg->len, msg->flags); + ret = + __ast_i2c_write_data(i2c_bus, msg->addr,
msg->buf,drivers/i2c/ast_i2c.c new file +66
-0+ msg->len); + } +if (ret) { +debug ("%s: error (%d)\n" , __func__, ret); +return -EREMOTEIO ; + } + } + +return 0 ; +} + +static int ast_i2c_set_speed (struct udevice *dev,unsigned int speed) +{ +debug ("Setting speed ofr I2C%d to <%u>\n" , dev->seq, speed); +if (!speed) { +debug ("No valid speed specified.\n" ); +return -EINVAL ; + } +struct ast_i2c *i2c_bus =dev_get_priv (dev); + + i2c_bus->speed = speed; +/* TODO: get this from device tree */ +u32 pclk =ast_get_apbclk (); +u32 divider = pclk / speed; + +struct ast_i2c_regs *i2c_base = i2c_bus->regs; +if (speed >400000 ) { +debug ("Enabling High Speed\n" ); +setbits_le32 (&i2c_base->fcr,AST_I2CD_M_HIGH_SPEED_EN + |AST_I2CD_M_SDA_DRIVE_1T_EN + |AST_I2CD_SDA_DRIVE_1T_EN ); +writel (0x3 , &i2c_base->cactcr2); +writel (__get_clk_reg_val (divider), &i2c_base->cactcr1); + }else { +debug ("Enabling Normal Speed\n" ); +writel (__get_clk_reg_val (divider), &i2c_base->cactcr1); +writel (AST_NO_TIMEOUT_CTRL , &i2c_base->cactcr2); + } + +__ast_i2c_clear_interrupts (i2c_base); +return 0 ; +} + +static const struct dm_i2c_ops ast_i2c_ops = { + .xfer = ast_i2c_xfer, + .set_bus_speed = ast_i2c_set_speed, + .deblock = ast_i2c_deblock, +}; + +static const struct udevice_id ast_i2c_ids[] = { + {.compatible ="aspeed,ast2500-i2c-controller" ,}, + {.compatible ="aspeed,ast2500-i2c-bus" ,}, + {}, +}; + +/* Tell GNU Indent to keep this as is: */ +/* *INDENT-OFF* */ +U_BOOT_DRIVER (i2c_aspeed) = { + .name ="i2c_aspeed" , + .id =UCLASS_I2C , + .of_match = ast_i2c_ids, + .probe = ast_i2c_probe, + .priv_auto_alloc_size =sizeof (struct ast_i2c ), + .ops = &ast_i2c_ops, +}; +/* *INDENT-ON* */ drivers/i2c/ast_i2c.h new file +28
-0@@ -0,0 +1,155 @@ +/* +* Copyright (C) 2016 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __AST_I2C_H_ +#define __AST_I2C_H_ + +struct ast_i2c_regs { +uint32_t fcr; +uint32_t cactcr1; +uint32_t cactcr2; +uint32_t icr; +uint32_t isr; +uint32_t csr; +uint32_t sdar; +uint32_t pbcr; +uint32_t trbbr; +#ifdef CONFIG_TARGET_AST_G5 +uint32_t dma_mbar; +uint32_t dma_tlr; +#endif +}; + +/* Device Register Definition */ +/* 0x00 : I2CD Function Control Register */ +#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) +#define AST_I2CD_BUFF_SEL (x) (x << 20) //page 0 ~ 7
drivers/i2c/ast_i2c.h new file +16
-0+#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) +#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) +#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) +#define AST_I2CD_MSB_STS (0x1 << 9) +#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) +#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) +#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) +#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) +#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) +#define AST_I2CD_DEF_ARP_EN (0x1 << 3) +#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) +#define AST_I2CD_SLAVE_EN (0x1 << 1) +#define AST_I2CD_MASTER_EN (0x1 ) + +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ +#define AST_I2CD_tBUF (0x1 <<28) // 0~7
+#defineAST_I2CD_tHDSTA
(0x1<< 24) // 0~7
+#defineAST_I2CD_tACST(0x1<<
20) // 0~7
+#defineAST_I2CD_tCKHIGH(0x1<<
16) // 0~7
+#defineAST_I2CD_tCKLOW
(0x1<< 12) // 0~7
+#defineAST_I2CD_tHDDAT
(0x1<< 10) // 0~7
+#defineAST_I2CD_CLK_TO_BASE_DIV(0x1<< 8) //
0~3drivers/i2c/ast_i2c.h new file +4
-0+#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf + +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ +#define AST_I2CD_tTIMEOUT (0x1 ) //0~7
drivers/i2c/ast_i2c.h new file +30
-0+#define AST_NO_TIMEOUT_CTRL 0x0 + +/* 0x0c : I2CD Interrupt Control Register & +* 0x10 : I2CD Interrupt Status Register +* +* These share bit definitions, so use the same values for the enable & +* status bits. +*/ +#define AST_I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) +#define AST_I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) +#define AST_I2CD_INTR_SMBUS_ALERT (0x1 << 12) +#define AST_I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) +#define AST_I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) +#define AST_I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) +#define AST_I2CD_INTR_GCALL_ADDR (0x1 << 8) +#define AST_I2CD_INTR_SLAVE_MATCH (0x1 << 7) +#define AST_I2CD_INTR_SCL_TIMEOUT (0x1 << 6) +#define AST_I2CD_INTR_ABNORMAL (0x1 << 5) +#define AST_I2CD_INTR_NORMAL_STOP (0x1 << 4) +#define AST_I2CD_INTR_ARBIT_LOSS (0x1 << 3) +#define AST_I2CD_INTR_RX_DONE (0x1 << 2) +#define AST_I2CD_INTR_TX_NAK (0x1 << 1) +#define AST_I2CD_INTR_TX_ACK (0x1 << 0) + +/* 0x14 : I2CD Command/Status Register */ +#define AST_I2CD_SDA_OE (0x1 << 28) +#define AST_I2CD_SDA_O (0x1 << 27) +#define AST_I2CD_SCL_OE (0x1 << 26) +#define AST_I2CD_SCL_O (0x1 << 25) +#define AST_I2CD_TX_TIMING (0x1 << 24) //0 ~3
drivers/i2c/ast_i2c.h new file +47
-0+#define AST_I2CD_TX_STATUS (0x1 << 23) + +// Tx State Machine +#define AST_I2CD_IDLE 0x0 +#define AST_I2CD_MACTIVE 0x8 +#define AST_I2CD_MSTART 0x9 +#define AST_I2CD_MSTARTR 0xa +#define AST_I2CD_MSTOP 0xb +#define AST_I2CD_MTXD 0xc +#define AST_I2CD_MRXACK 0xd +#define AST_I2CD_MRXD 0xe +#define AST_I2CD_MTXACK 0xf +#define AST_I2CD_SWAIT 0x1 +#define AST_I2CD_SRXD 0x4 +#define AST_I2CD_STXACK 0x5 +#define AST_I2CD_STXD 0x6 +#define AST_I2CD_SRXACK 0x7 +#define AST_I2CD_RECOVER 0x3 + +#define AST_I2CD_SCL_LINE_STS (0x1 << 18) +#define AST_I2CD_SDA_LINE_STS (0x1 << 17) +#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) +#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) +#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) +#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) +#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) +#define AST_I2CD_BUS_RECOVER_CMD (0x1 << 11) +#define AST_I2CD_S_ALT_EN (0x1 << 10) +// 0 : DMA Buffer, 1: Pool Buffer +//AST1070 DMA register +#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) +#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) + +/* Command Bit */ +#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) +#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) +#define AST_I2CD_M_STOP_CMD (0x1 << 5) +#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) +#define AST_I2CD_M_RX_CMD (0x1 << 3) +#define AST_I2CD_S_TX_CMD (0x1 << 2) +#define AST_I2CD_M_TX_CMD (0x1 << 1) +#define AST_I2CD_M_START_CMD (0x1 ) + +/* 0x18 : I2CD Slave Device Address Register */ + +/* 0x1C : I2CD Pool Buffer Control Register */ +#define AST_I2CD_RX_BUF_ADDR_GET (x) (((x) >>24) &
0xff)
+#defineAST_I2CD_RX_BUF_END_ADDR_SET(x)((x) <<
16)
+#defineAST_I2CD_TX_DATA_BUF_END_SET(x)(((x) &0xff) << 8)drivers/i2c/ast_i2c.h new file +5
-0+#define AST_I2CD_RX_DATA_BUF_GET (x) (((x) >> 8) & 0xff) +#define AST_I2CD_BUF_BASE_ADDR_SET (x) ((x) & 0x3f) + +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ +#define AST_I2CD_GET_MODE (x) (((x) >>8) &
0x1)drivers/i2c/ast_i2c.h new file +2
-0+ +#define AST_I2CD_RX_BYTE_BUFFER (
0xff<< 8)
+#defineAST_I2CD_TX_BYTE_BUFFER
(0xff)drivers/i2c/ast_i2c.h new file +14
-1+ +//1. usage flag , 2 size, 3. request address +/* Use platform_data instead of module parameters */ +/* Fast Mode = 400 kHz, Standard = 100 kHz */ +//static int clock = 100; /* Default: 100 kHz */ + +#define AST_I2CD_CMDS (AST_I2CD_BUS_RECOVER_CMD_EN | \ + AST_I2CD_M_STOP_CMD | \ + AST_I2CD_M_S_RX_CMD_LAST | \ + AST_I2CD_M_RX_CMD | \ + AST_I2CD_M_TX_CMD | \ + AST_I2CD_M_START_CMD) + +#endif /* _ASPEED_REGS_I2C_H_ */ --2.8.0.rc3.226.g39d4020
Signature · 1 line
*M*axim *S*loyko
Joel Stanley
maintainerHello Maxim,
Quoted 4 lines · On Tue, Sep 20, 2016 at 2:56 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
The driver is limited: only single master mode is supported and only byte-by-byte reads and writes are supported, no DMA or Pool Buffers.
Has this code been ported from the kernel driver? If so, mention it in your commit message and/or a comment in the code. A comment about what needed to be modified in order to make it integrate in the u-boot tree would be helpful. Also mention where you copied the code from; which tree or commit.
Be sure to incorporate any changes made to the upstream Linux driver as it goes through review.
Quoted 2 lines
Also, pin function configuration is performed by the I2C driver, because there is no pinctrl driver at the moment.
It looks like you've got several patches combined into one. To make it easier to review, try to have a separate patch for each feature you're adding.
Quoted 4 lines
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 ++ arch/arm/dts/aspeed-g5.dtsi | 392 ++++++++++++++++++++++++++++
This would be one patch.
I assume they came from the kernel tree? If so, mention this, including which tree/commit you got them from.
Quoted 2 lines
arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 + arch/arm/include/asm/arch-aspeed/regs-scu.h | 74 +++---
This would be another.
Quoted 2 lines
arch/arm/mach-aspeed/ast-scu.c | 31 ++- board/aspeed/ast-g5/ast-g5.c | 2 +-
I believe these integrate the i2c driver with the arch and the board. They should be separate commits.
Quoted 1 line
configs/ast_g5_defconfig | 4 +-
Updating the defconfig should be it's own patch.
Quoted 4 lines
drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 155 +++++++++++
Adding the i2c driver has nothing to do with the other functions, so that could be it's own patch.
Cheers,
Joel
Hi Joel,
Sorry for the delay with the reply, my work computer stopped working, needed to attend that.
I split the patch into three different self-consistent (hopefully) patches, but somewhat different from what you've suggested.
Quoted 5 lines · Joel Stanley
Hello Maxim,
Quoted 2 lines · On Tue, Sep 20, 2016 at 2:56 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Quoted 9 lines
Quoted 2 lines
The driver is limited: only single master mode is supported and only byte-by-byte reads and writes are supported, no DMA or Pool Buffers.
Has this code been ported from the kernel driver? If so, mention it in your commit message and/or a comment in the code. A comment about what needed to be modified in order to make it integrate in the u-boot tree would be helpful. Also mention where you copied the code from; which tree or commit.
I would not call that "copied". The APIs are very different at the moment, especially since in u-boot device tree is not fully utilized, so yes, I used kernel driver as a reference, but this is essentially a rewrite.
Quoted 30 lines
Be sure to incorporate any changes made to the upstream Linux driver as it goes through review.
Quoted 2 lines
Also, pin function configuration is performed by the I2C driver, because there is no pinctrl driver at the moment.
It looks like you've got several patches combined into one. To make it easier to review, try to have a separate patch for each feature you're adding.
Quoted 4 lines
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 ++ arch/arm/dts/aspeed-g5.dtsi | 392++++++++++++++++++++++++++++
This would be one patch.
I assume they came from the kernel tree? If so, mention this, including which tree/commit you got them from.
Quoted 2 lines
arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 + arch/arm/include/asm/arch-aspeed/regs-scu.h | 74 +++---This would be another.
Quoted 2 lines
arch/arm/mach-aspeed/ast-scu.c | 31 ++- board/aspeed/ast-g5/ast-g5.c | 2 +-
Quoted 7 lines
I believe these integrate the i2c driver with the arch and the board. They should be separate commits.
Quoted 1 line
configs/ast_g5_defconfig | 4 +-Updating the defconfig should be it's own patch.
This change was dropped.
Quoted 13 lines
Quoted 5 lines
drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 155 +++++++++++Adding the i2c driver has nothing to do with the other functions, so that could be it's own patch.
Cheers,
Joel
Signature · 1 line
*M*axim *S*loyko
PATCH 1/3 aspeed/g5: Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
In reply to [email protected]From: Maxim Sloyko <[email protected]>
Fixed the bug in board initialization, which caused failures during boot with device tree.
The flags are used to modify malloc behaviour after relocation, resetting the flag caused it to fail.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 +++++++++++++++++++++++++++++++++++++++++ board/aspeed/ast-g5/ast-g5.c | 1 - 4 files changed, 571 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsi
arch/arm/dts/Makefile +2 -0
@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here
arch/arm/dts/aspeed-g5-evb.dts new file +28 -0
@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};
arch/arm/dts/aspeed-g5.dtsi new file +541 -0
541 lines not on this page · raw message
board/aspeed/ast-g5/ast-g5.c +0 -1
@@ -52,7 +52,6 @@ int board_init(void) {/* adress of boot parameters */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ; - gd->flags =0 ;return 0 ; }
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH 2/3 aspeed/g5: helper SCU functions for configuring aspeed I2C
From: Maxim Sloyko <[email protected]>
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 74 ++++++++++++++++------------- arch/arm/mach-aspeed/ast-scu.c | 30 +++++++++++- 3 files changed, 75 insertions(+), 35 deletions(-)
arch/arm/include/asm/arch-aspeed/ast_scu.h +6 -0
@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );
@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif
arch/arm/include/asm/arch-aspeed/regs-scu.h +40 -34
103 lines not on this page · raw message
arch/arm/mach-aspeed/ast-scu.c +29 -1
@@ -318,6 +318,14 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +u32 apb_div =SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {
@@ -394,7 +402,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ;
@@ -496,3 +504,23 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 num) +{ +/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (num <3 ) { +#ifdef AST_SOC_G5 +if (num ==1 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA1 |SCU_FUN_PIN_SCL1 ); + }else { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA2 |SCU_FUN_PIN_SCL2 ); + } +#endif + }else { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 ,SCU_FUN_PIN_I2C (num)); + } +}
Signature · 1 line
2.8.0.rc3.226.g39d4020
Joel Stanley
maintainerRe: [PATCH 2/3] aspeed/g5: helper SCU functions for configuring aspeed I2C
On Wed, Sep 28, 2016 at 3:13 AM, <[email protected]> wrote:
You need a commit message.
Quoted 5 lines
From: Maxim Sloyko <[email protected]>
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 74 ++++++++++++++++-------------
Please put the reformatting of header files in a seperate patch.
Quoted 76 lines
arch/arm/mach-aspeed/ast-scu.c | 30 +++++++++++- 3 files changed, 75 insertions(+), 35 deletions(-)arch/arm/include/asm/arch-aspeed/ast_scu.h +6
-0@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif arch/arm/include/asm/arch-aspeed/regs-scu.h +11
-25@@ -10,8 +10,8 @@* 1. 2012/12/29 Ryan Chen Create * ********************************************************************************/ -#ifndef __AST_SCU_H -#define __AST_SCU_H 1 +#ifndef __AST_REGS_SCU_H +#define __AST_REGS_SCU_H 1#include <asm/arch/aspeed.h> @@ -830,49 +830,50 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */ #define SCU_FUN_PIN_SPICS1 (0x1 << 31)#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) -#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21)
arch/arm/include/asm/arch-aspeed/regs-scu.h line 851
Quoted 10 lines
arch/arm/include/asm/arch-aspeed/regs-scu.h +10
-0+#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3)) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12)
It looks like you're just changing the SCU_FUC_ to SCU_FUN. Without a commit message I'm not sure why you're doing this, can you explain why?
I don't think it is required.
If you were to make a change like this you should perform the renaming and update the call sites in a separate patch to any other changes. This makes it easier to review.
Quoted 5 lines
arch/arm/mach-aspeed/ast-scu.c +0
-0
arch/arm/mach-aspeed/ast-scu.c u32 ast_get_ahbclk(void) · line 326
Quoted 9 lines
arch/arm/mach-aspeed/ast-scu.c +6
-0@@ -318,6 +318,14 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +u32 apb_div =SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +}
This will do for now. We suspect need to write a clock driver that will live in drivers/clk/ to do it properly.
Can apb_div ever be zero?
Quoted 15 lines
arch/arm/mach-aspeed/ast-scu.c +3
-1+ +void ast_scu_show_system_info (void ) {@@ -394,7 +402,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ;
arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 509
Quoted 6 lines
arch/arm/mach-aspeed/ast-scu.c +3
-0@@ -496,3 +504,23 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 num) +{
Is num the bus? Perhaps a better name would be "bus_enable" or similar.
I think you mentioned that num must be > 0. If so, check for zero, log an error and return.
arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 513
Quoted 4 lines
arch/arm/mach-aspeed/ast-scu.c +4
-0+/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (num <3 ) {
How do we enable buses number 1 and 2 when AST_SOC_G5 is not set?
arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 518
Quoted 5 lines
arch/arm/mach-aspeed/ast-scu.c +5
-0+#ifdef AST_SOC_G5 +if (num ==1 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA1 |SCU_FUN_PIN_SCL1 ); + }else {
Make the else check for num == 2, as that's what you're looking for.
Quoted 17 lines
arch/arm/mach-aspeed/ast-scu.c +8
-1+setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , + SCU_FUN_PIN_SDA2 | SCU_FUN_PIN_SCL2); + } +#endif + }else { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 ,SCU_FUN_PIN_I2C (num)); + } +} --2.8.0.rc3.226.g39d4020
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Re: [PATCH 2/3] aspeed/g5: helper SCU functions for configuring aspeed I2C
Quoted 4 lines · Joel Stanley
On Wed, Sep 28, 2016 at 3:13 AM, <[email protected]> wrote:
You need a commit message.
Quoted 9 lines
Quoted 5 lines
From: Maxim Sloyko <[email protected]>
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 74++++++++++++++++-------------
Please put the reformatting of header files in a seperate patch.
What do you mean by reformatting?
Quoted 96 lines
Review
Quoted 5 lines
arch/arm/mach-aspeed/ast-scu.c | 30 +++++++++++- 3 files changed, 75 insertions(+), 35 deletions(-)(quoted diff) +0
-0
b/arch/arm/include/asm/arch-aspeed/ast_scu.hReview
Quoted 22 lines
index d248416..80ebd6f 100644
arch/arm/include/asm/arch-aspeed/ast_scu.h +6
-0@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif (quoted diff) +0
-0
b/arch/arm/include/asm/arch-aspeed/regs-scu.harch/arm/include/asm/arch-aspeed/regs-scu.h line 12
Quoted 7 lines
index b89df82..92ce84a 100644
arch/arm/include/asm/arch-aspeed/regs-scu.h +0
-0@@ -10,8 +10,8 @@* 1. 2012/12/29 Ryan Chen Create * ************************************************************ ********************/
arch/arm/include/asm/arch-aspeed/regs-scu.h line 830
Quoted 9 lines
arch/arm/include/asm/arch-aspeed/regs-scu.h +2
-2-#ifndef __AST_SCU_H -#define __AST_SCU_H 1 +#ifndef __AST_REGS_SCU_H +#define __AST_REGS_SCU_H 1#include <asm/arch/aspeed.h> @@ -830,49 +830,50 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */
Quoted 34 lines
arch/arm/include/asm/arch-aspeed/regs-scu.h +9
-23#define SCU_FUN_PIN_SPICS1 (0x1 << 31)#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) -#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21)arch/arm/include/asm/arch-aspeed/regs-scu.h line 851
Quoted 10 lines
arch/arm/include/asm/arch-aspeed/regs-scu.h +10
-0+#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3)) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12)It looks like you're just changing the
SCU_FUC_toSCU_FUN. Without a commit message I'm not sure why you're doing this, can you explain why?
Quoted 6 lines
I don't think it is required.
If you were to make a change like this you should perform the renaming and update the call sites in a separate patch to any other changes. This makes it easier to review.
Because that's a typo that got out of hand. FUN supposed to stand for FUNCTION,
FUC ... no guesses.
Quoted 21 lines
arch/arm/mach-aspeed/ast-
Quoted 3 lines
arch/arm/mach-aspeed/ast- renamed from arch/arm/mach-aspeed/ast-scu.c +0
-0
scu.carch/arm/mach-aspeed/ast-scu.c u32 ast_get_ahbclk(void) · line 326
Quoted 13 lines
index 0cc0d67..1452b93 100644
arch/arm/mach-aspeed/ast-scu.c +6
-0@@ -318,6 +318,14 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +u32 apb_div =SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +}This will do for now. We suspect need to write a clock driver that will live in
drivers/clk/to do it properly.
Quoted 3 lines
Can
apb_divever be zero?
Oh, this is actually wrong... Fixed.
Quoted 28 lines
Quoted 15 lines
arch/arm/mach-aspeed/ast-scu.c +3
-1+ +void ast_scu_show_system_info (void ) {@@ -394,7 +402,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ;arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 509
Quoted 6 lines
arch/arm/mach-aspeed/ast-scu.c +3
-0@@ -496,3 +504,23 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 num) +{Is num the bus? Perhaps a better name would be "
bus_enable" or similar.I think you mentioned that num must be > 0. If so, check for zero, log an error and return.
Quoted 7 lines
arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 513
Quoted 4 lines
arch/arm/mach-aspeed/ast-scu.c +4
-0+/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (num <3 ) {How do we enable buses number 1 and 2 when
AST_SOC_G5is not set?
I don't know. My guess is we don't, as in, the pins are always assigned these functions. In datasheet these bits in PIN CTRL8 register are marked as "new in ast2500" and there is no mention of sda{1,2},scl{1,2} in ast2500 datasheet.
Also, this part is basically taken from aspeed's sdk, this is why I assume they are always on.
Quoted 32 lines
arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void)
Quoted 4 lines
arch/arm/mach-aspeed/ast-scu.c +3
-0+#ifdef AST_SOC_G5 +if (num ==1 ) { + setbits_le32(AST_SCU_BASE +
AST_SCU_FUN_PIN_CTRL8,arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 517
Quoted 1 line
arch/arm/mach-aspeed/ast-scu.c +1
-0+ SCU_FUN_PIN_SDA1 |
SCU_FUN_PIN_SCL1);arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 518
Quoted 1 line
arch/arm/mach-aspeed/ast-scu.c +1
-0+ }else {Make the else check for num == 2, as that's what you're looking for.
arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 519
Quoted 1 line
arch/arm/mach-aspeed/ast-scu.c +1
-0+ setbits_le32(AST_SCU_BASE +
AST_SCU_FUN_PIN_CTRL8,arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void) · line 520
Quoted 1 line
arch/arm/mach-aspeed/ast-scu.c +1
-0+ SCU_FUN_PIN_SDA2 |
SCU_FUN_PIN_SCL2);arch/arm/mach-aspeed/ast-scu.c void ast_scu_get_who_init_dram(void)
Quoted 4 lines
arch/arm/mach-aspeed/ast-scu.c +4
-0+ } +#endif + }else { + setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL5,
SCU_FUN_PIN_I2C(num));Quoted 11 lines
arch/arm/mach-aspeed/ast-scu.c +2
-1+ } +} --2.8.0.rc3.226.g39d4020
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Signature · 1 line
*M*axim *S*loyko
Re: [PATCH 2/3] aspeed/g5: helper SCU functions for configuring aspeed I2C
Quoted 5 lines · Maxim Sloyko
Quoted 5 lines
Quoted 4 lines
+ /* Enable I2C Controllers */
+ clrbits_le32(AST_SCU_BASE +AST_SCU_RESET,SCU_RESET_I2C); +
+ if (num < 3) {
Quoted 7 lines
Quoted 1 line
How do we enable buses number 1 and 2 when
AST_SOC_G5is not set?I don't know. My guess is we don't, as in, the pins are always assigned these functions. In datasheet these bits in PIN CTRL8 register are marked as "new in ast2500" and there is no mention of sda{1,2},scl{1,2} in ast2500 datasheet.
Also, this part is basically taken from aspeed's sdk, this is why I assume they are always on.
So to clarify, the AST2400 has (SCL1, SDA1) and (SCL2, SDA2) on fixed function pins: (K21, K22) and (J19, J18) respectively. I don't have the datasheets for earlier releases of the AST SoCs, so can't speak for them. The AST2500 has (SCL1, SDA1) and (SCL2, SDA2) on multi-function
pins: (M18, M19) and (M20, P20) respectively.
As an aside: In AST2500 case I2Cs 1 and 2 are only multiplexed with GPIO and are at a higher priority, so we don't need to flip any other bits to enable I2C.
Maybe there should be some comments along these given the code looks odd at first glance?
Cheers,
Andrew
Separately: This code makes me glad I took a data-driven approach for the Linux pinmux driver (not to say that result is beautiful either, but I don't want even begin to imagine the maze of conditionals protecting corner cases).
Re: [PATCH 2/3] aspeed/g5: helper SCU functions for configuring aspeed I2C
Quoted 20 lines · Andrew Jeffery
Quoted 5 lines · Maxim Sloyko
Quoted 5 lines
Quoted 4 lines
arch/arm/mach-aspeed/ast-scu.c +4
-0+/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (num <3 ) {Quoted 7 lines
Quoted 1 line
How do we enable buses number 1 and 2 when
AST_SOC_G5is not set?I don't know. My guess is we don't, as in, the pins are always assigned these functions. In datasheet these bits in PIN CTRL8 register are marked as "new in ast2500" and there is no mention of sda{1,2},scl{1,2} in ast2500 datasheet.
Also, this part is basically taken from aspeed's sdk, this is why I assume they are always on.So to clarify, the AST2400 has (SCL1, SDA1) and (SCL2, SDA2) on fixed function pins: (K21, K22) and (J19, J18) respectively. I don't have the datasheets for earlier releases of the AST SoCs, so can't speak for them. The AST2500 has (SCL1, SDA1) and (SCL2, SDA2) on multi-function
pins: (M18, M19) and (M20, P20) respectively.
Quoted 7 lines
As an aside: In AST2500 case I2Cs 1 and 2 are only multiplexed with GPIO and are at a higher priority, so we don't need to flip any other bits to enable I2C.
Maybe there should be some comments along these given the code looks odd at first glance?
Added comment.
Quoted 9 lines
Cheers,
Andrew
Separately: This code makes me glad I took a data-driven approach for the Linux pinmux driver (not to say that result is beautiful either, but I don't want even begin to imagine the maze of conditionals protecting corner cases).
Signature · 1 line
*M*axim *S*loyko
PATCH 1/3 aspeed: Fix regs-scu.h and ast_scu.h incompatibility.
In reply to [email protected]From: Maxim Sloyko <[email protected]>
Fix regs-scu.h and ast_scu.h incompatibility. They were using the same include guard.
--- arch/arm/include/asm/arch-aspeed/regs-scu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-aspeed/regs-scu.h +2 -2
@@ -10,8 +10,8 @@* 1. 2012/12/29 Ryan Chen Create * ********************************************************************************/ -#ifndef __AST_SCU_H -#define __AST_SCU_H 1 +#ifndef __AST_REGS_SCU_H +#define __AST_REGS_SCU_H 1#include <asm/arch/aspeed.h>
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH 2/3 aspeed: Fixed FUC -> FUN typo in SCU.
From: Maxim Sloyko <[email protected]>
Fixed FUC -> FUN typo in SCU.
--- arch/arm/include/asm/arch-aspeed/regs-scu.h | 65 +++++++++++++++-------------- arch/arm/mach-aspeed/ast-scu.c | 2 +- 2 files changed, 34 insertions(+), 33 deletions(-)
arch/arm/include/asm/arch-aspeed/regs-scu.h +33 -32
@@ -830,49 +830,50 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */ #define SCU_FUN_PIN_SPICS1 (0x1 << 31)#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) -#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21) +#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3)) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUN_PIN_MII2_TX_DRIV (x) (x << 10) +#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUN_PIN_MII1_TX_DRIV (x) (x << 8) +#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)#define MII_NORMAL_DRIV 0x0#define MII_HIGH_DRIV 0x2 -#define SCU_FUC_PIN_UART6 (0x1 << 7) -#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) -#define SCU_FUC_PIN_DIGI_V_OUT (x) (x) -#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3) +#define SCU_FUN_PIN_UART6 (0x1 << 7) +#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUN_PIN_DIGI_V_OUT (x) (x) +#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)#define VIDEO_DISABLE 0x0#define VIDEO_12BITS 0x1#define VIDEO_24BITS 0x2//#define VIDEO_DISABLE 0x3 -#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) -#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3) +#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3) -#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) -#define SCU_FUC_PIN_SD2 (0x1 << 1) -#define SCU_FUC_PIN_SD1 (0x1 << 0) +#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUN_PIN_SD2 (0x1 << 1) +#define SCU_FUN_PIN_SD1 (0x1 << 0)/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/
arch/arm/mach-aspeed/ast-scu.c +1 -1
@@ -394,7 +394,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ;
Signature · 1 line
2.8.0.rc3.226.g39d4020
Re: [PATCH 2/3] aspeed: Fixed FUC -> FUN typo in SCU.
Ping
Quoted 117 lines · On Thu, Sep 29, 2016 at 2:27 PM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Fixed FUC -> FUN typo in SCU.
--- arch/arm/include/asm/arch-aspeed/regs-scu.h | 65 +++++++++++++++-------------- arch/arm/mach-aspeed/ast-scu.c | 2 +- 2 files changed, 34 insertions(+), 33 deletions(-)arch/arm/include/asm/arch-aspeed/regs-scu.h +0
-0@@ -830,49 +830,50 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */
#defineSCU_FUN_PIN_SPICS1(0x1<< 31)
#defineSCU_FUN_PIN_LPC_PLUS(0x1<< 30)arch/arm/include/asm/arch-aspeed/regs-scu.h +33
-32-#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21) +#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3)) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUN_PIN_MII2_TX_DRIV (x) (x << 10) +#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUN_PIN_MII1_TX_DRIV (x) (x << 8) +#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)#define MII_NORMAL_DRIV 0x0#define MII_HIGH_DRIV 0x2 -#define SCU_FUC_PIN_UART6 (0x1 << 7) -#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) -#define SCU_FUC_PIN_DIGI_V_OUT (x) (x) -#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3) +#define SCU_FUN_PIN_UART6 (0x1 << 7) +#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUN_PIN_DIGI_V_OUT (x) (x) +#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)#define VIDEO_DISABLE 0x0#define VIDEO_12BITS 0x1#define VIDEO_24BITS 0x2//#define VIDEO_DISABLE 0x3 -#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) -#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3) +#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3) -#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) -#define SCU_FUC_PIN_SD2 (0x1 << 1) -#define SCU_FUC_PIN_SD1 (0x1 << 0) +#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUN_PIN_SD2 (0x1 << 1) +#define SCU_FUN_PIN_SD1 (0x1 << 0)/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/
arch/arm/mach-aspeed/ast- renamed from arch/arm/mach-aspeed/ast-scu.c +0
-0
scu.c
index 0cc0d67..280c421 100644arch/arm/mach-aspeed/ast-scu.c +1
-2@@ -394,7 +394,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ; --2.8.0.rc3.226.g39d4020
Signature · 1 line
*M*axim *S*loyko
Joel Stanley
maintainerRe: [PATCH 2/3] aspeed: Fixed FUC -> FUN typo in SCU.
In reply to [email protected]Quoted 3 lines · On Fri, Sep 30, 2016 at 7:27 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Fixed FUC -> FUN typo in SCU.
This lacks a signed off by as previously discussed.
You have not made a convincing argument for this change. I suggest you drop the patch from your series.
Cheers,
Joel
Quoted 112 lines
--- arch/arm/include/asm/arch-aspeed/regs-scu.h | 65 +++++++++++++++-------------- arch/arm/mach-aspeed/ast-scu.c | 2 +- 2 files changed, 34 insertions(+), 33 deletions(-)arch/arm/include/asm/arch-aspeed/regs-scu.h +33
-32@@ -830,49 +830,50 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */ #define SCU_FUN_PIN_SPICS1 (0x1 << 31)#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) -#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21) +#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3)) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUN_PIN_MII2_TX_DRIV (x) (x << 10) +#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUN_PIN_MII1_TX_DRIV (x) (x << 8) +#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)#define MII_NORMAL_DRIV 0x0#define MII_HIGH_DRIV 0x2 -#define SCU_FUC_PIN_UART6 (0x1 << 7) -#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) -#define SCU_FUC_PIN_DIGI_V_OUT (x) (x) -#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3) +#define SCU_FUN_PIN_UART6 (0x1 << 7) +#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUN_PIN_DIGI_V_OUT (x) (x) +#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)#define VIDEO_DISABLE 0x0#define VIDEO_12BITS 0x1#define VIDEO_24BITS 0x2//#define VIDEO_DISABLE 0x3 -#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) -#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3) +#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3) -#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) -#define SCU_FUC_PIN_SD2 (0x1 << 1) -#define SCU_FUC_PIN_SD1 (0x1 << 0) +#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUN_PIN_SD2 (0x1 << 1) +#define SCU_FUN_PIN_SD1 (0x1 << 0)/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/ arch/arm/mach-aspeed/ast-scu.c +1
-2@@ -394,7 +394,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ; --2.8.0.rc3.226.g39d4020
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Re: [PATCH 2/3] aspeed: Fixed FUC -> FUN typo in SCU.
Quoted 10 lines · Joel Stanley
Quoted 3 lines · On Fri, Sep 30, 2016 at 7:27 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Fixed FUC -> FUN typo in SCU.
This lacks a signed off by as previously discussed.
You have not made a convincing argument for this change. I suggest you drop the patch from your series.
Are you against this change per se or just against it being in this patch series?
Quoted 123 lines
Cheers,
Joel
Quoted 2 lines
--- arch/arm/include/asm/arch-aspeed/regs-scu.h | 65+++++++++++++++--------------
Review
Quoted 4 lines
arch/arm/mach-aspeed/ast-scu.c | 2 +- 2 files changed, 34 insertions(+), 33 deletions(-)(quoted diff) +0
-0
b/arch/arm/include/asm/arch-aspeed/regs-scu.harch/arm/include/asm/arch-aspeed/regs-scu.h line 830
Quoted 5 lines
index b714fa9..aab032a 100644
arch/arm/include/asm/arch-aspeed/regs-scu.h +0
-0@@ -830,49 +830,50 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */
Quoted 71 lines
arch/arm/include/asm/arch-aspeed/regs-scu.h +30
-29#define SCU_FUN_PIN_SPICS1 (0x1 << 31)#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) -#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21) +#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3)) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUN_PIN_MII2_TX_DRIV (x) (x << 10) +#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUN_PIN_MII1_TX_DRIV (x) (x << 8) +#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)#define MII_NORMAL_DRIV 0x0#define MII_HIGH_DRIV 0x2 -#define SCU_FUC_PIN_UART6 (0x1 << 7) -#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) -#define SCU_FUC_PIN_DIGI_V_OUT (x) (x) -#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3) +#define SCU_FUN_PIN_UART6 (0x1 << 7) +#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUN_PIN_DIGI_V_OUT (x) (x) +#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)#define VIDEO_DISABLE 0x0#define VIDEO_12BITS 0x1#define VIDEO_24BITS 0x2//#define VIDEO_DISABLE 0x3 -#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) -#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3) +#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3)arch/arm/include/asm/arch-aspeed/regs-scu.h
Quoted 10 lines
arch/arm/include/asm/arch-aspeed/regs-scu.h +3
-3-#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) -#define SCU_FUC_PIN_SD2 (0x1 << 1) -#define SCU_FUC_PIN_SD1 (0x1 << 0) +#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUN_PIN_SD2 (0x1 << 1) +#define SCU_FUN_PIN_SD1 (0x1 << 0)/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/
arch/arm/mach-aspeed/ast-
Quoted 1 line
arch/arm/mach-aspeed/ast- renamed from arch/arm/mach-aspeed/ast-scu.c +0
-0
scu.cQuoted 19 lines
index 0cc0d67..280c421 100644
arch/arm/mach-aspeed/ast-scu.c +1
-2@@ -394,7 +394,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ; --2.8.0.rc3.226.g39d4020
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Signature · 1 line
*M*axim *S*loyko
Joel Stanley
maintainerRe: [PATCH 2/3] aspeed: Fixed FUC -> FUN typo in SCU.
Quoted 9 lines · Maxim Sloyko
Quoted 6 lines · Joel Stanley
Quoted 3 lines · On Fri, Sep 30, 2016 at 7:27 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Fixed FUC -> FUN typo in SCU.
Quoted 8 lines
Quoted 4 lines
This lacks a signed off by as previously discussed.
You have not made a convincing argument for this change. I suggest you drop the patch from your series.
Are you against this change per se or just against it being in this patch series?
In our tree at the moment.
We're happy to take drivers that are on their way to being upstream, or fixes for bugs that we're hitting.
Other than that our goal should be cleaning up the tree so we can submit it upstream. Once we submit upstream everyone has a common base to work from, which makes doing cleanups easier.
Cheers,
Joel
Re: [PATCH 2/3] aspeed: Fixed FUC -> FUN typo in SCU.
Hi Joel,
Sorry for long delay, I got distracted by other projects that needed immediate attention. I'll be sending new and updated patches soon.
Quoted 19 lines · Joel Stanley
Quoted 9 lines · Maxim Sloyko
Quoted 6 lines · Joel Stanley
Quoted 3 lines · On Fri, Sep 30, 2016 at 7:27 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Fixed FUC -> FUN typo in SCU.
Quoted 8 lines
Quoted 4 lines
This lacks a signed off by as previously discussed.
You have not made a convincing argument for this change. I suggest you drop the patch from your series.
Are you against this change per se or just against it being in this patch series?
Quoted 9 lines
In our tree at the moment.
We're happy to take drivers that are on their way to being upstream, or fixes for bugs that we're hitting.
Other than that our goal should be cleaning up the tree so we can submit it upstream. Once we submit upstream everyone has a common base to work from, which makes doing cleanups easier.
I still don't get it. Is this not a cleanup? I think having consistent naming is important. It would be understandable if this file was already in upstream tree and I would be touching parts that are in upstream version and parts that aren't, but
this file only exists in our tree.
What is the downside?
Quoted 5 lines
Cheers,
Joel
Signature · 1 line
*M*axim *S*loyko
PATCH 3/3 aspeed: SCU helper functions for I2C.
In reply to [email protected]From: Maxim Sloyko <[email protected]>
SCU helper functions for configuring I2C pins and accessing APB clock.
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 +++++++ arch/arm/mach-aspeed/ast-scu.c | 36 +++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+)
arch/arm/include/asm/arch-aspeed/ast_scu.h +6 -0
@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );
@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif
arch/arm/include/asm/arch-aspeed/regs-scu.h +8 -0
@@ -915,6 +915,11 @@#define SCU_FUN_PIN_ROMA4 (0x1 << 18)#define SCU_FUN_PIN_ROMA3 (0x1 << 17)#define SCU_FUN_PIN_ROMA2 (0x1 << 16) +/* AST2500 only */ +#define SCU_FUN_PIN_SDA2 (0x1 << 15) +#define SCU_FUN_PIN_SCL2 (0x1 << 14) +#define SCU_FUN_PIN_SDA1 (0x1 << 13) +#define SCU_FUN_PIN_SCL1 (0x1 << 12)/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */ #define SCU_FUN_PIN_ROMA21 (0x1 << 3)
@@ -950,4 +955,7 @@/* AST_SCU_BMC_CLASS 0x19C - BMC device class code and revision ID */ /* AST_SCU_BMC_DEV_ID 0x1A4 - BMC device ID */ +#define SCU_I2C_MIN_BUS_NUM (1) +#define SCU_I2C_MAX_BUS_NUM (14) +#endif
arch/arm/mach-aspeed/ast-scu.c +36 -0
@@ -318,6 +318,17 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +/* The formula for converting the bit pattern to divisor is +* (4 + 4 * DIV), according to datasheet +*/ +u32 apb_div =4 +4 *SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {
@@ -496,3 +507,28 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 bus_num) +{ +if (bus_num <SCU_I2C_MIN_BUS_NUM || bus_num >SCU_I2C_MAX_BUS_NUM ) { +debug ("%s: bus_num is out of range, must be [%d - %d]\n" , __func__, +SCU_I2C_MIN_BUS_NUM ,SCU_I2C_MAX_BUS_NUM ); +return ; + } + +/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (bus_num >=3 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 , +SCU_FUN_PIN_I2C (bus_num)); +#ifdef AST_SOC_G5 + }else if (bus_num ==1 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA1 |SCU_FUN_PIN_SCL1 ); + }else if (bus_num ==2 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA2 |SCU_FUN_PIN_SCL2 ); +#endif + } +}
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH 1/1 aspeed: SCU helper functions for I2C.
From: Maxim Sloyko <[email protected]>
SCU helper functions for configuring I2C pins and accessing APB clock.
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 ++++++ arch/arm/mach-aspeed/ast-scu.c | 38 +++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+)
arch/arm/include/asm/arch-aspeed/ast_scu.h +6 -0
@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );
@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif
arch/arm/include/asm/arch-aspeed/regs-scu.h +8 -0
@@ -915,6 +915,11 @@#define SCU_FUN_PIN_ROMA4 (0x1 << 18)#define SCU_FUN_PIN_ROMA3 (0x1 << 17)#define SCU_FUN_PIN_ROMA2 (0x1 << 16) +/* AST2500 only */ +#define SCU_FUN_PIN_SDA2 (0x1 << 15) +#define SCU_FUN_PIN_SCL2 (0x1 << 14) +#define SCU_FUN_PIN_SDA1 (0x1 << 13) +#define SCU_FUN_PIN_SCL1 (0x1 << 12)/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */ #define SCU_FUN_PIN_ROMA21 (0x1 << 3)
@@ -950,4 +955,7 @@/* AST_SCU_BMC_CLASS 0x19C - BMC device class code and revision ID */ /* AST_SCU_BMC_DEV_ID 0x1A4 - BMC device ID */ +#define SCU_I2C_MIN_BUS_NUM (1) +#define SCU_I2C_MAX_BUS_NUM (14) +#endif
arch/arm/mach-aspeed/ast-scu.c +38 -0
@@ -318,6 +318,17 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +/* The formula for converting the bit pattern to divisor is +* (4 + 4 * DIV), according to datasheet +*/ +u32 apb_div =4 +4 *SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {
@@ -496,3 +507,30 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 bus_num) +{ +if (bus_num <SCU_I2C_MIN_BUS_NUM || bus_num >SCU_I2C_MAX_BUS_NUM ) { +debug ("%s: bus_num is out of range, must be [%d - %d]\n" , __func__, +SCU_I2C_MIN_BUS_NUM ,SCU_I2C_MAX_BUS_NUM ); +return ; + } + +/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (bus_num >=3 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 , +SCU_FUN_PIN_I2C (bus_num)); +#ifdef AST_SOC_G5 +/* In AST2400 aka AST_SOC_G4 SDA{1,2}/SCL{1,2} are fixed function pins, + * so no need to change their function. */ + }else if (bus_num ==1 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA1 |SCU_FUN_PIN_SCL1 ); + }else if (bus_num ==2 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA2 |SCU_FUN_PIN_SCL2 ); +#endif + } +}
Signature · 1 line
2.8.0.rc3.226.g39d4020
Re: [PATCH] aspeed: SCU helper functions for I2C.
Ping
Quoted 124 lines · On Mon, Oct 3, 2016 at 11:55 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
SCU helper functions for configuring I2C pins and accessing APB clock.
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 ++++++ arch/arm/mach-aspeed/ast-scu.c | 38 +++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+)arch/arm/include/asm/arch-aspeed/ast_scu.h +6
-0@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif arch/arm/include/asm/arch-aspeed/regs-scu.h +5
-0@@ -915,6 +915,11 @@#define SCU_FUN_PIN_ROMA4 (0x1 << 18)#define SCU_FUN_PIN_ROMA3 (0x1 << 17)#define SCU_FUN_PIN_ROMA2 (0x1 << 16) +/* AST2500 only */ +#define SCU_FUN_PIN_SDA2 (0x1 << 15) +#define SCU_FUN_PIN_SCL2 (0x1 << 14) +#define SCU_FUN_PIN_SDA1 (0x1 << 13) +#define SCU_FUN_PIN_SCL1 (0x1 << 12)/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */
#defineSCU_FUN_PIN_ROMA21(0x1<< 3)arch/arm/include/asm/arch-aspeed/regs-scu.h +0
-0@@ -950,4 +955,7 @@/* AST_SCU_BMC_CLASS 0x19C - BMC device class code and revision ID */
/*AST_SCU_BMC_DEV_ID0x1A4- BMC device ID */arch/arm/include/asm/arch-aspeed/regs-scu.h +3
-0+#define SCU_I2C_MIN_BUS_NUM (1) +#define SCU_I2C_MAX_BUS_NUM (14) +#endif arch/arm/mach-aspeed/ast- renamed from arch/arm/mach-aspeed/ast-scu.c +0
-0
scu.c
index 280c421..1dbd667 100644arch/arm/mach-aspeed/ast-scu.c +15
-0@@ -318,6 +318,17 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +/* The formula for converting the bit pattern to divisor is +* (4 + 4 * DIV), according to datasheet +*/ +u32 apb_div =4 +4 *SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {@@ -496,3 +507,30 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c(u8 bus_num) +{ + if (bus_num < SCU_I2C_MIN_BUS_NUM || bus_num >
SCU_I2C_MAX_BUS_NUM) {
+ debug("%s:bus_numis out of range, must be [%d - %d]\n",__func__,arch/arm/mach-aspeed/ast-scu.c +12
-0+ SCU_I2C_MIN_BUS_NUM, SCU_I2C_MAX_BUS_NUM); +return ; + } + +/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (bus_num >=3 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 , +SCU_FUN_PIN_I2C (bus_num)); +#ifdef AST_SOC_G5 +/* In AST2400 aka AST_SOC_G4 SDA{1,2}/SCL{1,2} are fixed function pins,
arch/arm/mach-aspeed/ast-scu.c +4
-0+* so no need to change their function. */ + }else if (bus_num ==1 ) { + setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8, + SCU_FUN_PIN_SDA1 |
SCU_FUN_PIN_SCL1);arch/arm/mach-aspeed/ast-scu.c +3
-0+ }else if (bus_num ==2 ) { + setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8, + SCU_FUN_PIN_SDA2 |
SCU_FUN_PIN_SCL2);arch/arm/mach-aspeed/ast-scu.c +3
-1+#endif + } +} --2.8.0.rc3.226.g39d4020
Signature · 1 line
*M*axim *S*loyko
Joel Stanley
maintainerRe: [PATCH] aspeed: SCU helper functions for I2C.
In reply to [email protected]Quoted 3 lines · On Tue, Oct 4, 2016 at 5:55 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
SCU helper functions for configuring I2C pins and accessing APB clock.
This lacks a signed off by as previously discussed.
Please send two separate patches, one for the apb change and one for the unrelated scu change.
Make sure you send your patches with a version number for the series. It also helps to add a u-boot prefix so I know if the patch is for the kernel or u-boot.
git format-patch [email protected] [email protected] --subject-prefix "u-boot" -v 2 ....
Cheers,
Joel
Quoted 112 lines
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 +++++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 ++++++ arch/arm/mach-aspeed/ast-scu.c | 38 +++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+)arch/arm/include/asm/arch-aspeed/ast_scu.h +6
-0@@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );@@ -45,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif arch/arm/include/asm/arch-aspeed/regs-scu.h +8
-0@@ -915,6 +915,11 @@#define SCU_FUN_PIN_ROMA4 (0x1 << 18)#define SCU_FUN_PIN_ROMA3 (0x1 << 17)#define SCU_FUN_PIN_ROMA2 (0x1 << 16) +/* AST2500 only */ +#define SCU_FUN_PIN_SDA2 (0x1 << 15) +#define SCU_FUN_PIN_SCL2 (0x1 << 14) +#define SCU_FUN_PIN_SDA1 (0x1 << 13) +#define SCU_FUN_PIN_SCL1 (0x1 << 12)/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */ #define SCU_FUN_PIN_ROMA21 (0x1 << 3)@@ -950,4 +955,7 @@/* AST_SCU_BMC_CLASS 0x19C - BMC device class code and revision ID */ /* AST_SCU_BMC_DEV_ID 0x1A4 - BMC device ID */ +#define SCU_I2C_MIN_BUS_NUM (1) +#define SCU_I2C_MAX_BUS_NUM (14) +#endif arch/arm/mach-aspeed/ast-scu.c +38
-1@@ -318,6 +318,17 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +u32 h_pll =ast_get_h_pll_clk (); +/* The formula for converting the bit pattern to divisor is +* (4 + 4 * DIV), according to datasheet +*/ +u32 apb_div =4 +4 *SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {@@ -496,3 +507,30 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 bus_num) +{ +if (bus_num <SCU_I2C_MIN_BUS_NUM || bus_num >SCU_I2C_MAX_BUS_NUM ) { +debug ("%s: bus_num is out of range, must be [%d - %d]\n" , __func__, +SCU_I2C_MIN_BUS_NUM ,SCU_I2C_MAX_BUS_NUM ); +return ; + } + +/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + +if (bus_num >=3 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 , +SCU_FUN_PIN_I2C (bus_num)); +#ifdef AST_SOC_G5 +/* In AST2400 aka AST_SOC_G4 SDA{1,2}/SCL{1,2} are fixed function pins, + * so no need to change their function. */ + }else if (bus_num ==1 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA1 |SCU_FUN_PIN_SCL1 ); + }else if (bus_num ==2 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA2 |SCU_FUN_PIN_SCL2 ); +#endif + } +} --2.8.0.rc3.226.g39d4020
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PATCH 3/3 aspeed/g5: I2C driver.
In reply to [email protected]From: Maxim Sloyko <[email protected]>
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
--- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 155 +++++++++++++++++++++++++ 4 files changed, 468 insertions(+) create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h
drivers/i2c/Kconfig +6 -0
@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. +config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2C
drivers/i2c/Makefile +1 -0
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
drivers/i2c/ast_i2c.c new file +306 -0
306 lines not on this page · raw message
drivers/i2c/ast_i2c.h new file +155 -0
155 lines not on this page · raw message
Signature · 1 line
2.8.0.rc3.226.g39d4020
Joel Stanley
maintainerRe: [PATCH 3/3] aspeed/g5: I2C driver.
Quoted 5 lines · On Wed, Sep 28, 2016 at 3:13 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
Your subject string mentions g5, but I think this is a generic Aspeed i2c driver that will work on the g4 platforms as well.
Quoted 44 lines
--- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 155 +++++++++++++++++++++++++ 4 files changed, 468 insertions(+) create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.hdrivers/i2c/Kconfig +6
-0@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. +config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2Cdrivers/i2c/Makefile +1
-0@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.odrivers/i2c/ast_i2c.c new file +0
-0
drivers/i2c/ast_i2c.c line 2
Quoted 2 lines
drivers/i2c/ast_i2c.c new file +2
-0@@ -0,0 +1,306 @@ +/* +* Copyright (C) 2016 Google, Inc
The driver looks to be copied at least in part from the kernel one.
Quoted 23 lines
drivers/i2c/ast_i2c.c new file +23
-0+* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> + +#include <asm/arch/ast_scu.h> +#include <asm/arch/regs-scu.h> +#include <asm/io.h> + +#include "ast_i2c.h" + +#define I2C_TIMEOUT_US (100000) +#define I2C_SLEEP_STEP (20) +#define EI2C_TIMEOUT (1001) + +DECLARE_GLOBAL_DATA_PTR ; + +struct ast_i2c { +u32 id;
drivers/i2c/ast_i2c.c line 35
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+struct ast_i2c_regs *regs; +int speed; +}; + +#define RETURN_IF_ERROR (expr) do {\ + int err = (expr);\ + if (err < 0) {\ + return err;\ + }\ +} while (0)
u-boot upstream does not use macros like this.
drivers/i2c/ast_i2c.c line 37
Quoted 2 lines
drivers/i2c/ast_i2c.c new file +2
-0+ +static u32 __get_clk_reg_val (u32 divider_ratio)
Why the __ prefix? I think you should remove it.
Quoted 6 lines
drivers/i2c/ast_i2c.c new file +6
-0+{ +unsigned int inc =0 , div; +u32 scl_low, scl_high, data; + +for (div =0 ; divider_ratio >=16 ; div++) { + inc |= (divider_ratio &1 );
drivers/i2c/ast_i2c.c line 53
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ divider_ratio >>=1 ; + } + divider_ratio += inc; + scl_low = (divider_ratio >>1 ) -1 ; + scl_high = divider_ratio - scl_low -2 ; + data =0x77700300 | (scl_high <<16 ) | (scl_low <<12 ) | div; +return data; +} + +static inline void __ast_i2c_clear_interrupts (struct ast_i2c_regs *i2c_base)
Remove the __ prefix.
drivers/i2c/ast_i2c.c line 58
Quoted 5 lines
drivers/i2c/ast_i2c.c new file +5
-0+{ +writel (~0 , &i2c_base->isr); +} + +static int __ast_i2c_init_bus (struct ast_i2c *i2c_bus)
Remove the __ prefix.
Quoted 8 lines
drivers/i2c/ast_i2c.c new file +8
-0+{ +/* Reset device */ +writel (0 , &i2c_bus->regs->fcr); +/* Enable Master Mode. Assuming single-master. */ +debug ("Enable Master for %p\n" , i2c_bus->regs); +setbits_le32 (&i2c_bus->regs->fcr, +AST_I2CD_MASTER_EN + | AST_I2CD_M_SDA_LOCK_EN
drivers/i2c/ast_i2c.c line 76
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ | AST_I2CD_MULTI_MASTER_DIS | AST_I2CD_M_SCL_DRIVE_EN); +debug ("FCR: %p\n" , &i2c_bus->regs->fcr); +/* Enable Interrupts */ +writel (AST_I2CD_INTR_TX_ACK + |AST_I2CD_INTR_TX_NAK + |AST_I2CD_INTR_RX_DONE + |AST_I2CD_INTR_BUS_RECOVER_DONE + |AST_I2CD_INTR_NORMAL_STOP + |AST_I2CD_INTR_ABNORMAL , &i2c_bus->regs->icr); +return 0 ;
Change the return type to void if you're not using it.
Quoted 5 lines
drivers/i2c/ast_i2c.c new file +5
-0+} + +static int ast_i2c_probe (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev);
drivers/i2c/ast_i2c.c line 91
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ +debug ("Enabling I2C%u \n" , dev->seq); +ast_scu_enable_i2c (dev->seq); + + i2c_bus->id = dev->seq; +struct ast_i2c_regs *i2c_base = + (struct ast_i2c_regs *)dev_get_addr (dev); + i2c_bus->regs = i2c_base; + +return __ast_i2c_init_bus (i2c_bus);
__ast_i2c_init_bus always returns 0, so this can return void.
Quoted 39 lines
drivers/i2c/ast_i2c.c new file +39
-0+} + +static inline int __ast_i2c_wait_isr (struct ast_i2c_regs *i2c_base,u32 flag) +{ +int timeout =I2C_TIMEOUT_US ; +while (!(readl (&i2c_base->isr) & flag) && timeout >0 ) { +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +__ast_i2c_clear_interrupts (i2c_base); +if (timeout <=0 ) +return -EI2C_TIMEOUT ; +return 0 ; +} + +static inline int __ast_i2c_send_stop (struct ast_i2c_regs *i2c_base) +{ +writel (AST_I2CD_M_STOP_CMD , &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_isr + (i2c_base,AST_I2CD_INTR_NORMAL_STOP )); +return 0 ; +} + +static inline int __ast_i2c_wait_tx (struct ast_i2c_regs *i2c_base) +{ +int timeout =I2C_TIMEOUT_US ; +u32 flag =AST_I2CD_INTR_TX_ACK |AST_I2CD_INTR_TX_NAK ; +u32 status =readl (&i2c_base->isr) & flag; +while (!status && timeout >0 ) { + status =readl (&i2c_base->isr) & flag; +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +int ret =0 ; +if (status ==AST_I2CD_INTR_TX_NAK ) { + ret = -EREMOTEIO ; + }
drivers/i2c/ast_i2c.c line 140
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ +if (timeout <=0 ) { + ret = -EI2C_TIMEOUT ; + } + +__ast_i2c_clear_interrupts (i2c_base); +return ret; +} + +static inline int __ast_i2c_start_txn (struct ast_i2c_regs *i2c_base,u8 devaddr)
Remove the __ prefix.
What's the "n" mean after tx? Or does txn mean transaction?
drivers/i2c/ast_i2c.c line 150
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+{ +/* Start and Send Device Address */ +writel (devaddr, &i2c_base->trbbr); +writel (AST_I2CD_M_START_CMD |AST_I2CD_M_TX_CMD , &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_tx (i2c_base)); +return 0 ; +} + +static int __ast_i2c_read_data (struct ast_i2c *i2c_bus,u8 chip,u8 *buffer, +int len)
Remove the __ prefix.
What is chip in this case? I think it's the i2c slave's address. Make that clearer please.
len can be a size_t.
drivers/i2c/ast_i2c.c line 152
Quoted 2 lines
drivers/i2c/ast_i2c.c new file +2
-0+{ +int i2c_error =0 ;
No need to initialise this here.
drivers/i2c/ast_i2c.c line 155
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +3
-0+struct ast_i2c_regs *i2c_base = i2c_bus->regs; + + i2c_error =__ast_i2c_start_txn (i2c_base, (chip <<1 ) |I2C_M_RD );
Test for the error and return here to make it clear that no further processing occurs.
Quoted 5 lines
drivers/i2c/ast_i2c.c new file +5
-0+ +if (!i2c_error) { +u32 i2c_cmd =AST_I2CD_M_RX_CMD ; +for (; len >0 ; len--, buffer++) { +if (len ==1 ) {
drivers/i2c/ast_i2c.c line 170
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ i2c_cmd |=AST_I2CD_M_S_RX_CMD_LAST ; + } +writel (i2c_cmd, &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_isr + (i2c_base,AST_I2CD_INTR_RX_DONE )); + *buffer =AST_I2CD_RX_DATA_BUF_GET (readl (&i2c_base->trbbr)); + } +__ast_i2c_clear_interrupts (i2c_base); + } +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base));
I don't think your RETURN_IF_ERROR macro does anything for readability here. You're going to return regardless, so do:
return __ast_i2c_send_stop(i2c_base);
drivers/i2c/ast_i2c.c line 176
Quoted 6 lines
drivers/i2c/ast_i2c.c new file +6
-0+ +return i2c_error; +} + +static int __ast_i2c_write_data (struct ast_i2c *i2c_bus,u8 chip,u8 *buffer, +int len)
Similar comments as for read_data above.
Quoted 106 lines
drivers/i2c/ast_i2c.c new file +106
-0+{ +int i2c_error =0 ; +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + + i2c_error =__ast_i2c_start_txn (i2c_base, (chip <<1 )); +for (; len >0 &&0 == i2c_error; len--, buffer++) { +writel (*buffer, &i2c_base->trbbr); +writel (AST_I2CD_M_TX_CMD , &i2c_base->csr); + i2c_error =__ast_i2c_wait_tx (i2c_base); + } +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base)); +return i2c_error; +} + +static int ast_i2c_deblock (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +u32 csr =readl (&i2c_base->csr); +debug ("Bus hung (%x), attempting recovery\n" , csr); + +bool sda_high = csr &AST_I2CD_SDA_LINE_STS ; +bool scl_high = csr &AST_I2CD_SCL_LINE_STS ; +if (sda_high && scl_high) { +/* Bus is idle, no deblocking needed. */ +return 0 ; + }else if (sda_high) { +/* Send stop command */ +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base)); + }else if (scl_high) { +/* Possibly stuck slave */ +writel (AST_I2CD_BUS_RECOVER_CMD , &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_isr + (i2c_base,AST_I2CD_INTR_BUS_RECOVER_DONE )); + }else { +/* Just try to reinit the device. */ +RETURN_IF_ERROR (__ast_i2c_init_bus (i2c_bus)); + } + +return 0 ; +} + +static int ast_i2c_xfer (struct udevice *dev,struct i2c_msg *msg,int nmsgs) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +int ret; + +debug ("i2c_xfer: %d messages\n" , nmsgs); +for (; nmsgs >0 ; nmsgs--, msg++) { +/* TODO: use this for repeated start */ +bool next_is_read = nmsgs >1 && (msg[1 ].flags &I2C_M_RD ); + +if (msg->flags &I2C_M_RD ) { +debug ("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n" , + msg->addr, msg->len, msg->flags); + ret = +__ast_i2c_read_data (i2c_bus, msg->addr, msg->buf, + msg->len); + }else { +debug ("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n" , + msg->addr, msg->len, msg->flags); + ret = +__ast_i2c_write_data (i2c_bus, msg->addr, msg->buf, + msg->len); + } +if (ret) { +debug ("%s: error (%d)\n" , __func__, ret); +return -EREMOTEIO ; + } + } + +return 0 ; +} + +static int ast_i2c_set_speed (struct udevice *dev,unsigned int speed) +{ +debug ("Setting speed ofr I2C%d to <%u>\n" , dev->seq, speed); +if (!speed) { +debug ("No valid speed specified.\n" ); +return -EINVAL ; + } +struct ast_i2c *i2c_bus =dev_get_priv (dev); + + i2c_bus->speed = speed; +/* TODO: get this from device tree */ +u32 pclk =ast_get_apbclk (); +u32 divider = pclk / speed; + +struct ast_i2c_regs *i2c_base = i2c_bus->regs; +if (speed >400000 ) { +debug ("Enabling High Speed\n" ); +setbits_le32 (&i2c_base->fcr,AST_I2CD_M_HIGH_SPEED_EN + |AST_I2CD_M_SDA_DRIVE_1T_EN + |AST_I2CD_SDA_DRIVE_1T_EN ); +writel (0x3 , &i2c_base->cactcr2); +writel (__get_clk_reg_val (divider), &i2c_base->cactcr1); + }else { +debug ("Enabling Normal Speed\n" ); +writel (__get_clk_reg_val (divider), &i2c_base->cactcr1); +writel (AST_NO_TIMEOUT_CTRL , &i2c_base->cactcr2); + } + +__ast_i2c_clear_interrupts (i2c_base); +return 0 ; +}
drivers/i2c/ast_i2c.c line 292
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ +static const struct dm_i2c_ops ast_i2c_ops = { + .xfer = ast_i2c_xfer, + .set_bus_speed = ast_i2c_set_speed, + .deblock = ast_i2c_deblock, +}; + +static const struct udevice_id ast_i2c_ids[] = { + {.compatible ="aspeed,ast2400-i2c-controller" ,}, + {.compatible ="aspeed,ast2400-i2c-bus" ,},
Your subject says g5, but your compatible strings say g4.
Your probe function doesn't test for which string you're using. Why do you have both -controller and -bus?
Quoted 182 lines
drivers/i2c/ast_i2c.c new file +14
-0+ {}, +}; + +/* Tell GNU Indent to keep this as is: */ +/* *INDENT-OFF* */ +U_BOOT_DRIVER (i2c_aspeed) = { + .name ="i2c_aspeed" , + .id =UCLASS_I2C , + .of_match = ast_i2c_ids, + .probe = ast_i2c_probe, + .priv_auto_alloc_size =sizeof (struct ast_i2c ), + .ops = &ast_i2c_ops, +}; +/* *INDENT-ON* */ drivers/i2c/ast_i2c.h new file +155
-1@@ -0,0 +1,155 @@ +/* +* Copyright (C) 2016 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __AST_I2C_H_ +#define __AST_I2C_H_ + +struct ast_i2c_regs { +uint32_t fcr; +uint32_t cactcr1; +uint32_t cactcr2; +uint32_t icr; +uint32_t isr; +uint32_t csr; +uint32_t sdar; +uint32_t pbcr; +uint32_t trbbr; +#ifdef CONFIG_TARGET_AST_G5 +uint32_t dma_mbar; +uint32_t dma_tlr; +#endif +}; + +/* Device Register Definition */ +/* 0x00 : I2CD Function Control Register */ +#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) +#define AST_I2CD_BUFF_SEL (x) (x << 20) // page 0 ~ 7 +#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) +#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) +#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) +#define AST_I2CD_MSB_STS (0x1 << 9) +#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) +#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) +#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) +#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) +#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) +#define AST_I2CD_DEF_ARP_EN (0x1 << 3) +#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) +#define AST_I2CD_SLAVE_EN (0x1 << 1) +#define AST_I2CD_MASTER_EN (0x1 ) + +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ +#define AST_I2CD_tBUF (0x1 << 28) // 0~7 +#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7 +#define AST_I2CD_tACST (0x1 << 20) // 0~7 +#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7 +#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7 +#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7 +#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3 +#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf + +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ +#define AST_I2CD_tTIMEOUT (0x1 ) // 0~7 +#define AST_NO_TIMEOUT_CTRL 0x0 + +/* 0x0c : I2CD Interrupt Control Register & +* 0x10 : I2CD Interrupt Status Register +* +* These share bit definitions, so use the same values for the enable & +* status bits. +*/ +#define AST_I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) +#define AST_I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) +#define AST_I2CD_INTR_SMBUS_ALERT (0x1 << 12) +#define AST_I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) +#define AST_I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) +#define AST_I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) +#define AST_I2CD_INTR_GCALL_ADDR (0x1 << 8) +#define AST_I2CD_INTR_SLAVE_MATCH (0x1 << 7) +#define AST_I2CD_INTR_SCL_TIMEOUT (0x1 << 6) +#define AST_I2CD_INTR_ABNORMAL (0x1 << 5) +#define AST_I2CD_INTR_NORMAL_STOP (0x1 << 4) +#define AST_I2CD_INTR_ARBIT_LOSS (0x1 << 3) +#define AST_I2CD_INTR_RX_DONE (0x1 << 2) +#define AST_I2CD_INTR_TX_NAK (0x1 << 1) +#define AST_I2CD_INTR_TX_ACK (0x1 << 0) + +/* 0x14 : I2CD Command/Status Register */ +#define AST_I2CD_SDA_OE (0x1 << 28) +#define AST_I2CD_SDA_O (0x1 << 27) +#define AST_I2CD_SCL_OE (0x1 << 26) +#define AST_I2CD_SCL_O (0x1 << 25) +#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3 +#define AST_I2CD_TX_STATUS (0x1 << 23) + +// Tx State Machine +#define AST_I2CD_IDLE 0x0 +#define AST_I2CD_MACTIVE 0x8 +#define AST_I2CD_MSTART 0x9 +#define AST_I2CD_MSTARTR 0xa +#define AST_I2CD_MSTOP 0xb +#define AST_I2CD_MTXD 0xc +#define AST_I2CD_MRXACK 0xd +#define AST_I2CD_MRXD 0xe +#define AST_I2CD_MTXACK 0xf +#define AST_I2CD_SWAIT 0x1 +#define AST_I2CD_SRXD 0x4 +#define AST_I2CD_STXACK 0x5 +#define AST_I2CD_STXD 0x6 +#define AST_I2CD_SRXACK 0x7 +#define AST_I2CD_RECOVER 0x3 + +#define AST_I2CD_SCL_LINE_STS (0x1 << 18) +#define AST_I2CD_SDA_LINE_STS (0x1 << 17) +#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) +#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) +#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) +#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) +#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) +#define AST_I2CD_BUS_RECOVER_CMD (0x1 << 11) +#define AST_I2CD_S_ALT_EN (0x1 << 10) +// 0 : DMA Buffer, 1: Pool Buffer +//AST1070 DMA register +#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) +#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) + +/* Command Bit */ +#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) +#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) +#define AST_I2CD_M_STOP_CMD (0x1 << 5) +#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) +#define AST_I2CD_M_RX_CMD (0x1 << 3) +#define AST_I2CD_S_TX_CMD (0x1 << 2) +#define AST_I2CD_M_TX_CMD (0x1 << 1) +#define AST_I2CD_M_START_CMD (0x1 ) + +/* 0x18 : I2CD Slave Device Address Register */ + +/* 0x1C : I2CD Pool Buffer Control Register */ +#define AST_I2CD_RX_BUF_ADDR_GET (x) (((x) >> 24) & 0xff) +#define AST_I2CD_RX_BUF_END_ADDR_SET (x) ((x) << 16) +#define AST_I2CD_TX_DATA_BUF_END_SET (x) (((x) & 0xff) << 8) +#define AST_I2CD_RX_DATA_BUF_GET (x) (((x) >> 8) & 0xff) +#define AST_I2CD_BUF_BASE_ADDR_SET (x) ((x) & 0x3f) + +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ +#define AST_I2CD_GET_MODE (x) (((x) >> 8) & 0x1) + +#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8) +#define AST_I2CD_TX_BYTE_BUFFER (0xff ) + +//1. usage flag , 2 size, 3. request address +/* Use platform_data instead of module parameters */ +/* Fast Mode = 400 kHz, Standard = 100 kHz */ +//static int clock = 100; /* Default: 100 kHz */ + +#define AST_I2CD_CMDS (AST_I2CD_BUS_RECOVER_CMD_EN | \ + AST_I2CD_M_STOP_CMD | \ + AST_I2CD_M_S_RX_CMD_LAST | \ + AST_I2CD_M_RX_CMD | \ + AST_I2CD_M_TX_CMD | \ + AST_I2CD_M_START_CMD) + +#endif /* _ASPEED_REGS_I2C_H_ */ --2.8.0.rc3.226.g39d4020
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Re: [PATCH 3/3] aspeed/g5: I2C driver.
Quoted 10 lines · Joel Stanley
Quoted 5 lines · On Wed, Sep 28, 2016 at 3:13 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
Your subject string mentions g5, but I think this is a generic Aspeed i2c driver that will work on the g4 platforms as well.
I changed it to say g5/g4, but I haven't actually tested it on ast2400.
Quoted 43 lines
Quoted 5 lines
--- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 306 ++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/i2c/Kconfig config SYS_I2C_CADENCE · line 65
Quoted 11 lines
drivers/i2c/ast_i2c.h | 155 +++++++++++++++++++++++++ 4 files changed, 468 insertions(+) create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.hdrivers/i2c/Kconfig +0
-0@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. Thiscontroller is
Quoted 25 lines
drivers/i2c/Kconfig +6
-0e.g. used by Xilinx Zynq. +config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2Cdrivers/i2c/Makefile +1
-0@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.odrivers/i2c/ast_i2c.c new file +0
-0
Quoted 9 lines
drivers/i2c/ast_i2c.c line 2
Quoted 6 lines
index 0000000..c7bc199
drivers/i2c/ast_i2c.c new file +2
-0@@ -0,0 +1,306 @@ +/* +* Copyright (C) 2016 Google, Inc The driver looks to be copied at least in part from the kernel one.
Fixed.
Quoted 28 lines
Quoted 28 lines
drivers/i2c/ast_i2c.c new file +27
-0+* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> + +#include <asm/arch/ast_scu.h> +#include <asm/arch/regs-scu.h> +#include <asm/io.h> + +#include "ast_i2c.h" + +#define I2C_TIMEOUT_US (100000) +#define I2C_SLEEP_STEP (20) +#define EI2C_TIMEOUT (1001) + +DECLARE_GLOBAL_DATA_PTR ; + +struct ast_i2c { +u32 id; +struct ast_i2c_regs *regs; +int speed; +}; +
Quoted 9 lines
drivers/i2c/ast_i2c.c line 35
Quoted 6 lines
drivers/i2c/ast_i2c.c new file +6
-0+#define RETURN_IF_ERROR (expr) do {\ + int err = (expr);\ + if (err < 0) {\ + return err;\ + }\ +} while (0)u-boot upstream does not use macros like this.
Fixed.
Quoted 6 lines
drivers/i2c/ast_i2c.c line 37
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +2
-0+ +static u32 __get_clk_reg_val (u32 divider_ratio)Why the __ prefix? I think you should remove it.
Removed.
Quoted 49 lines
Quoted 7 lines
drivers/i2c/ast_i2c.c new file +6
-0+{ +unsigned int inc =0 , div; +u32 scl_low, scl_high, data; + +for (div =0 ; divider_ratio >=16 ; div++) { + inc |= (divider_ratio &1 );drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ divider_ratio >>=1 ; + } + divider_ratio += inc; + scl_low = (divider_ratio >>1 ) -1 ; + scl_high = divider_ratio - scl_low -2 ; + data =0x77700300 | (scl_high <<16 ) | (scl_low <<12 ) | div; +return data; +} + +static inline void __ast_i2c_clear_interrupts(struct ast_i2c_regs
*i2c_base)Remove the __ prefix.
drivers/i2c/ast_i2c.c line 58
Quoted 5 lines
drivers/i2c/ast_i2c.c new file +5
-0+{ +writel (~0 , &i2c_base->isr); +} + +static int __ast_i2c_init_bus (struct ast_i2c *i2c_bus)Remove the __ prefix.
drivers/i2c/ast_i2c.c
Quoted 9 lines
drivers/i2c/ast_i2c.c new file +9
-0+{ +/* Reset device */ +writel (0 , &i2c_bus->regs->fcr); +/* Enable Master Mode. Assuming single-master. */ +debug ("Enable Master for %p\n" , i2c_bus->regs); + setbits_le32(&i2c_bus->regs->fcr, + AST_I2CD_MASTER_EN + | AST_I2CD_M_SDA_LOCK_EN + | AST_I2CD_MULTI_MASTER_DIS |
AST_I2CD_M_SCL_DRIVE_EN);drivers/i2c/ast_i2c.c line 76
Quoted 9 lines
drivers/i2c/ast_i2c.c new file +9
-0+debug ("FCR: %p\n" , &i2c_bus->regs->fcr); +/* Enable Interrupts */ +writel (AST_I2CD_INTR_TX_ACK + |AST_I2CD_INTR_TX_NAK + |AST_I2CD_INTR_RX_DONE + |AST_I2CD_INTR_BUS_RECOVER_DONE + |AST_I2CD_INTR_NORMAL_STOP + |AST_I2CD_INTR_ABNORMAL , &i2c_bus->regs->icr); +return 0 ;
Quoted 2 lines
Change the return type to void if you're not using it.
Done.
Quoted 10 lines
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +9
-0+} + +static int ast_i2c_probe (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); + +debug ("Enabling I2C%u \n" , dev->seq); +ast_scu_enable_i2c (dev->seq); +
Quoted 9 lines
drivers/i2c/ast_i2c.c line 91
Quoted 6 lines
drivers/i2c/ast_i2c.c new file +6
-0+ i2c_bus->id = dev->seq; +struct ast_i2c_regs *i2c_base = + (struct ast_i2c_regs *)dev_get_addr (dev); + i2c_bus->regs = i2c_base; + +return __ast_i2c_init_bus (i2c_bus);
__ast_i2c_init_busalways returns 0, so this can return void.
It's part of driver's API, so has a fixed signature.
Quoted 53 lines
drivers/i2c/ast_i2c.c
Quoted 4 lines
drivers/i2c/ast_i2c.c new file +3
-0+} + +static inline int __ast_i2c_wait_isr(struct ast_i2c_regs *i2c_base, u32flag)
Quoted 36 lines
drivers/i2c/ast_i2c.c new file +36
-0+{ +int timeout =I2C_TIMEOUT_US ; +while (!(readl (&i2c_base->isr) & flag) && timeout >0 ) { +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +__ast_i2c_clear_interrupts (i2c_base); +if (timeout <=0 ) +return -EI2C_TIMEOUT ; +return 0 ; +} + +static inline int __ast_i2c_send_stop (struct ast_i2c_regs *i2c_base) +{ +writel (AST_I2CD_M_STOP_CMD , &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_isr + (i2c_base,AST_I2CD_INTR_NORMAL_STOP )); +return 0 ; +} + +static inline int __ast_i2c_wait_tx (struct ast_i2c_regs *i2c_base) +{ +int timeout =I2C_TIMEOUT_US ; +u32 flag =AST_I2CD_INTR_TX_ACK |AST_I2CD_INTR_TX_NAK ; +u32 status =readl (&i2c_base->isr) & flag; +while (!status && timeout >0 ) { + status =readl (&i2c_base->isr) & flag; +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +int ret =0 ; +if (status ==AST_I2CD_INTR_TX_NAK ) { + ret = -EREMOTEIO ; + }drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ +if (timeout <=0 ) { + ret = -EI2C_TIMEOUT ; + } + +__ast_i2c_clear_interrupts (i2c_base); +return ret; +} + +static inline int __ast_i2c_start_txn(struct ast_i2c_regs *i2c_base, u8devaddr)
Quoted 4 lines
Remove the __ prefix.
What's the "n" mean after tx? Or does txn mean transaction?
Yes, this means transaction.
Quoted 11 lines
drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +9
-0+{ +/* Start and Send Device Address */ +writel (devaddr, &i2c_base->trbbr); +writel (AST_I2CD_M_START_CMD |AST_I2CD_M_TX_CMD , &i2c_base->csr); +RETURN_IF_ERROR (__ast_i2c_wait_tx (i2c_base)); +return 0 ; +} + +static int __ast_i2c_read_data(struct ast_i2c *i2c_bus, u8 chip, u8*buffer,
Quoted 7 lines
drivers/i2c/ast_i2c.c line 150
Quoted 1 line
drivers/i2c/ast_i2c.c new file +1
-0+ int len)Remove the __ prefix.
What is chip in this case? I think it's the i2c slave's address. Make that clearer please.
Main drivers/i2c.h file uses names chip and chip_address for this purpose, so I just picked one.
Quoted 175 lines
len can be a
size_t.drivers/i2c/ast_i2c.c line 152
Quoted 2 lines
drivers/i2c/ast_i2c.c new file +2
-0+{ +int i2c_error =0 ;No need to initialise this here.
drivers/i2c/ast_i2c.c
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +3
-0+struct ast_i2c_regs *i2c_base = i2c_bus->regs; + + i2c_error = __ast_i2c_start_txn(i2c_base, (chip << 1) |
I2C_M_RD);Test for the error and return here to make it clear that no further processing occurs.
drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ +if (!i2c_error) { +u32 i2c_cmd =AST_I2CD_M_RX_CMD ; +for (; len >0 ; len--, buffer++) { +if (len ==1 ) { + i2c_cmd |=AST_I2CD_M_S_RX_CMD_LAST ; + } +writel (i2c_cmd, &i2c_base->csr); + RETURN_IF_ERROR(__ast_i2c_wait_isr + (i2c_base,
AST_I2CD_INTR_RX_DONE));drivers/i2c/ast_i2c.c line 166
Quoted 1 line
drivers/i2c/ast_i2c.c new file +1
-0+ *buffer = AST_I2CD_RX_DATA_BUF_GET(
readl(&i2c_base->trbbr));drivers/i2c/ast_i2c.c line 170
Quoted 4 lines
drivers/i2c/ast_i2c.c new file +4
-0+ } +__ast_i2c_clear_interrupts (i2c_base); + } +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base));I don't think your
RETURN_IF_ERRORmacro does anything for readability here. You're going to return regardless, so do:return
__ast_i2c_send_stop(i2c_base);drivers/i2c/ast_i2c.c
Quoted 5 lines
drivers/i2c/ast_i2c.c new file +5
-0+ +return i2c_error; +} + +static int __ast_i2c_write_data(struct ast_i2c *i2c_bus, u8 chip, u8*buffer,
drivers/i2c/ast_i2c.c line 176
Quoted 1 line
drivers/i2c/ast_i2c.c new file +1
-0+ int len)Similar comments as for
read_dataabove.Quoted 25 lines
drivers/i2c/ast_i2c.c new file +25
-0+{ +int i2c_error =0 ; +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + + i2c_error =__ast_i2c_start_txn (i2c_base, (chip <<1 )); +for (; len >0 &&0 == i2c_error; len--, buffer++) { +writel (*buffer, &i2c_base->trbbr); +writel (AST_I2CD_M_TX_CMD , &i2c_base->csr); + i2c_error =__ast_i2c_wait_tx (i2c_base); + } +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base)); +return i2c_error; +} + +static int ast_i2c_deblock (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +u32 csr =readl (&i2c_base->csr); +debug ("Bus hung (%x), attempting recovery\n" , csr); + +bool sda_high = csr &AST_I2CD_SDA_LINE_STS ; +bool scl_high = csr &AST_I2CD_SCL_LINE_STS ; +if (sda_high && scl_high) {drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+/* Bus is idle, no deblocking needed. */ +return 0 ; + }else if (sda_high) { +/* Send stop command */ +RETURN_IF_ERROR (__ast_i2c_send_stop (i2c_base)); + }else if (scl_high) { +/* Possibly stuck slave */ +writel (AST_I2CD_BUS_RECOVER_CMD , &i2c_base->csr); + RETURN_IF_ERROR(__ast_i2c_wait_isr + (i2c_base, AST_I2CD_INTR_BUS_RECOVER_DONE));
drivers/i2c/ast_i2c.c
Quoted 9 lines
drivers/i2c/ast_i2c.c new file +9
-0+ }else { +/* Just try to reinit the device. */ +RETURN_IF_ERROR (__ast_i2c_init_bus (i2c_bus)); + } + +return 0 ; +} + +static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, intnmsgs)
drivers/i2c/ast_i2c.c
Quoted 8 lines
drivers/i2c/ast_i2c.c new file +8
-0+{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +int ret; + +debug ("i2c_xfer: %d messages\n" , nmsgs); +for (; nmsgs >0 ; nmsgs--, msg++) { +/* TODO: use this for repeated start */ + bool next_is_read = nmsgs > 1 && (msg[1].flags &
I2C_M_RD);drivers/i2c/ast_i2c.c
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +3
-0+ +if (msg->flags &I2C_M_RD ) { + debug("i2c_read: chip=0x%x, len=0x%x,flags=0x%x\n",
drivers/i2c/ast_i2c.c
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +3
-0+ msg->addr, msg->len, msg->flags); + ret = + __ast_i2c_read_data(i2c_bus, msg->addr,
msg->buf,drivers/i2c/ast_i2c.c
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +3
-0+ msg->len); + }else { + debug("i2c_write: chip=0x%x, len=0x%x,flags=0x%x\n",
drivers/i2c/ast_i2c.c
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +3
-0+ msg->addr, msg->len, msg->flags); + ret = + __ast_i2c_write_data(i2c_bus, msg->addr,
msg->buf,Quoted 42 lines
drivers/i2c/ast_i2c.c new file +42
-0+ msg->len); + } +if (ret) { +debug ("%s: error (%d)\n" , __func__, ret); +return -EREMOTEIO ; + } + } + +return 0 ; +} + +static int ast_i2c_set_speed (struct udevice *dev,unsigned int speed) +{ +debug ("Setting speed ofr I2C%d to <%u>\n" , dev->seq, speed); +if (!speed) { +debug ("No valid speed specified.\n" ); +return -EINVAL ; + } +struct ast_i2c *i2c_bus =dev_get_priv (dev); + + i2c_bus->speed = speed; +/* TODO: get this from device tree */ +u32 pclk =ast_get_apbclk (); +u32 divider = pclk / speed; + +struct ast_i2c_regs *i2c_base = i2c_bus->regs; +if (speed >400000 ) { +debug ("Enabling High Speed\n" ); +setbits_le32 (&i2c_base->fcr,AST_I2CD_M_HIGH_SPEED_EN + |AST_I2CD_M_SDA_DRIVE_1T_EN + |AST_I2CD_SDA_DRIVE_1T_EN ); +writel (0x3 , &i2c_base->cactcr2); +writel (__get_clk_reg_val (divider), &i2c_base->cactcr1); + }else { +debug ("Enabling Normal Speed\n" ); +writel (__get_clk_reg_val (divider), &i2c_base->cactcr1); +writel (AST_NO_TIMEOUT_CTRL , &i2c_base->cactcr2); + } + +__ast_i2c_clear_interrupts (i2c_base); +return 0 ; +}drivers/i2c/ast_i2c.c line 292
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ +static const struct dm_i2c_ops ast_i2c_ops = { + .xfer = ast_i2c_xfer, + .set_bus_speed = ast_i2c_set_speed, + .deblock = ast_i2c_deblock, +}; + +static const struct udevice_id ast_i2c_ids[] = { + {.compatible ="aspeed,ast2400-i2c-controller" ,}, + {.compatible ="aspeed,ast2400-i2c-bus" ,},Your subject says g5, but your compatible strings say g4.
Quoted 3 lines
Your probe function doesn't test for which string you're using. Why do you have both -controller and -bus?
I think this has something to do with how the device tree is processed, but it seems that because i2c buses are specified under a single controller node, if I don't specify compatibility with -controller, it does not match -bus nodes.
Quoted 214 lines
Quoted 39 lines
drivers/i2c/ast_i2c.c new file +14
-0+ {}, +}; + +/* Tell GNU Indent to keep this as is: */ +/* *INDENT-OFF* */ +U_BOOT_DRIVER (i2c_aspeed) = { + .name ="i2c_aspeed" , + .id =UCLASS_I2C , + .of_match = ast_i2c_ids, + .probe = ast_i2c_probe, + .priv_auto_alloc_size =sizeof (struct ast_i2c ), + .ops = &ast_i2c_ops, +}; +/* *INDENT-ON* */ drivers/i2c/ast_i2c.h new file +18
-0@@ -0,0 +1,155 @@ +/* +* Copyright (C) 2016 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __AST_I2C_H_ +#define __AST_I2C_H_ + +struct ast_i2c_regs { + uint32_t fcr; + uint32_t cactcr1; + uint32_t cactcr2; + uint32_t icr; + uint32_t isr; + uint32_t csr; + uint32_t sdar; + uint32_t pbcr; + uint32_t trbbr;drivers/i2c/ast_i2c.h line 28
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#ifdef CONFIG_TARGET_AST_G5 +uint32_t dma_mbar; +uint32_t dma_tlr; +#endif +}; + +/* Device Register Definition */ +/* 0x00 : I2CD Function Control Register */ +#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) +#define AST_I2CD_BUFF_SEL (x) (x << 20)// page 0 ~ 7
drivers/i2c/ast_i2c.h
Quoted 4 lines
drivers/i2c/ast_i2c.h new file +4
-0+#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) +#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) +#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) +#define AST_I2CD_MSB_STS (0x1 <<9)
drivers/i2c/ast_i2c.h
Quoted 6 lines
drivers/i2c/ast_i2c.h new file +6
-0+#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) +#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) +#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) +#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) +#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) +#define AST_I2CD_DEF_ARP_EN (0x1 <<3)
drivers/i2c/ast_i2c.h line 40
Quoted 2 lines
drivers/i2c/ast_i2c.h new file +2
-0+#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) +#define AST_I2CD_SLAVE_EN (0x1 <<1)
drivers/i2c/ast_i2c.h
Quoted 4 lines
drivers/i2c/ast_i2c.h new file +4
-0+#define AST_I2CD_MASTER_EN (0x1 ) + +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ +#define AST_I2CD_tBUF (0x1 <<28) // 0~7
drivers/i2c/ast_i2c.h line 45
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tHDSTA(
0x1<< 24) // 0~7drivers/i2c/ast_i2c.h line 46
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tACST (0x1 <<20) // 0~7
drivers/i2c/ast_i2c.h line 47
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tCKHIGH (0x1 <<16) // 0~7
drivers/i2c/ast_i2c.h line 48
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tCKLOW(
0x1<< 12) // 0~7drivers/i2c/ast_i2c.h line 49
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tHDDAT(
0x1<< 10) // 0~7drivers/i2c/ast_i2c.h line 50
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8)// 0~3
drivers/i2c/ast_i2c.h
Quoted 4 lines
drivers/i2c/ast_i2c.h new file +4
-0+#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf + +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ +#define AST_I2CD_tTIMEOUT (0x1 )// 0~7
Quoted 16 lines
drivers/i2c/ast_i2c.h new file +16
-0+#define AST_NO_TIMEOUT_CTRL 0x0 + +/* 0x0c : I2CD Interrupt Control Register & +* 0x10 : I2CD Interrupt Status Register +* +* These share bit definitions, so use the same values for the enable & +* status bits. +*/ +#define AST_I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) +#define AST_I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) +#define AST_I2CD_INTR_SMBUS_ALERT (0x1 << 12) +#define AST_I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) +#define AST_I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) +#define AST_I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) +#define AST_I2CD_INTR_GCALL_ADDR (0x1 << 8) +#define AST_I2CD_INTR_SLAVE_MATCH (0x1 << 7)drivers/i2c/ast_i2c.h
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#define AST_I2CD_INTR_SCL_TIMEOUT (0x1 << 6) +#define AST_I2CD_INTR_ABNORMAL (0x1 << 5) +#define AST_I2CD_INTR_NORMAL_STOP (0x1 << 4) +#define AST_I2CD_INTR_ARBIT_LOSS (0x1 << 3) +#define AST_I2CD_INTR_RX_DONE (0x1 << 2) +#define AST_I2CD_INTR_TX_NAK (0x1 << 1) +#define AST_I2CD_INTR_TX_ACK (0x1 << 0) + +/* 0x14 : I2CD Command/Status Register */ +#define AST_I2CD_SDA_OE (0x1 <<28)
drivers/i2c/ast_i2c.h line 82
Quoted 2 lines
drivers/i2c/ast_i2c.h new file +2
-0+#define AST_I2CD_SDA_O (0x1 << 27) +#define AST_I2CD_SCL_OE (0x1 <<26)
drivers/i2c/ast_i2c.h line 84
Quoted 2 lines
drivers/i2c/ast_i2c.h new file +2
-0+#define AST_I2CD_SCL_O (0x1 << 25) +#define AST_I2CD_TX_TIMING (0x1 << 24)// 0 ~3
Quoted 13 lines
drivers/i2c/ast_i2c.h new file +13
-0+#define AST_I2CD_TX_STATUS (0x1 << 23) + +// Tx State Machine +#define AST_I2CD_IDLE 0x0 +#define AST_I2CD_MACTIVE 0x8 +#define AST_I2CD_MSTART 0x9 +#define AST_I2CD_MSTARTR 0xa +#define AST_I2CD_MSTOP 0xb +#define AST_I2CD_MTXD 0xc +#define AST_I2CD_MRXACK 0xd +#define AST_I2CD_MRXD 0xe +#define AST_I2CD_MTXACK 0xf +#define AST_I2CD_SWAIT 0x1drivers/i2c/ast_i2c.h
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#define AST_I2CD_SRXD 0x4 +#define AST_I2CD_STXACK 0x5 +#define AST_I2CD_STXD 0x6 +#define AST_I2CD_SRXACK 0x7 +#define AST_I2CD_RECOVER 0x3 + +#define AST_I2CD_SCL_LINE_STS (0x1 << 18) +#define AST_I2CD_SDA_LINE_STS (0x1 << 17) +#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) +#define AST_I2CD_SDA_OE_OUT_DIR (0x1 <<15)
drivers/i2c/ast_i2c.h line 109
Quoted 2 lines
drivers/i2c/ast_i2c.h new file +2
-0+#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) +#define AST_I2CD_SCL_OE_OUT_DIR (0x1 <<13)
drivers/i2c/ast_i2c.h
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) +#define AST_I2CD_BUS_RECOVER_CMD (0x1 << 11) +#define AST_I2CD_S_ALT_EN (0x1 << 10) +// 0 : DMA Buffer, 1: Pool Buffer +//AST1070 DMA register +#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) +#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) + +/* Command Bit */ +#define AST_I2CD_RX_BUFF_ENABLE (0x1 <<7)
drivers/i2c/ast_i2c.h line 120
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_TX_BUFF_ENABLE (0x1 <<6)
drivers/i2c/ast_i2c.h line 121
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_M_STOP_CMD (0x1 <<5)
drivers/i2c/ast_i2c.h line 123
Quoted 2 lines
drivers/i2c/ast_i2c.h new file +2
-0+#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) +#define AST_I2CD_M_RX_CMD (0x1 <<3)
drivers/i2c/ast_i2c.h line 124
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_S_TX_CMD (0x1 <<2)
drivers/i2c/ast_i2c.h line 125
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_M_TX_CMD (0x1 <<1)
drivers/i2c/ast_i2c.h
Quoted 6 lines
drivers/i2c/ast_i2c.h new file +6
-0+#define AST_I2CD_M_START_CMD (0x1 ) + +/* 0x18 : I2CD Slave Device Address Register */ + +/* 0x1C : I2CD Pool Buffer Control Register */ +#define AST_I2CD_RX_BUF_ADDR_GET (x) (((x) >>24) &
0xff)drivers/i2c/ast_i2c.h line 132
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_RX_BUF_END_ADDR_SET (x) ((x) <<16)
drivers/i2c/ast_i2c.h line 133
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_TX_DATA_BUF_END_SET (x) (((x) &
0xff) << 8)drivers/i2c/ast_i2c.h line 134
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_RX_DATA_BUF_GET (x) (((x) >> 8) &
0xff)drivers/i2c/ast_i2c.h
Quoted 4 lines
drivers/i2c/ast_i2c.h new file +4
-0+#define AST_I2CD_BUF_BASE_ADDR_SET (x) ((x) & 0x3f) + +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ +#define AST_I2CD_GET_MODE (x) (((x) >>8) &
0x1)drivers/i2c/ast_i2c.h line 140
Quoted 2 lines
drivers/i2c/ast_i2c.h new file +2
-0+ +#define AST_I2CD_RX_BYTE_BUFFER (
0xff<< 8)drivers/i2c/ast_i2c.h line 141
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_TX_BYTE_BUFFER (
0xff)Quoted 21 lines
drivers/i2c/ast_i2c.h new file +14
-1+ +//1. usage flag , 2 size, 3. request address +/* Use platform_data instead of module parameters */ +/* Fast Mode = 400 kHz, Standard = 100 kHz */ +//static int clock = 100; /* Default: 100 kHz */ + +#define AST_I2CD_CMDS (AST_I2CD_BUS_RECOVER_CMD_EN | \ + AST_I2CD_M_STOP_CMD | \ + AST_I2CD_M_S_RX_CMD_LAST | \ + AST_I2CD_M_RX_CMD | \ + AST_I2CD_M_TX_CMD | \ + AST_I2CD_M_START_CMD) + +#endif /* _ASPEED_REGS_I2C_H_ */ --2.8.0.rc3.226.g39d4020
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Signature · 1 line
*M*axim *S*loyko
Joel Stanley
maintainerRe: [PATCH 3/3] aspeed/g5: I2C driver.
Quoted 7 lines · Maxim Sloyko
Quoted 7 lines
drivers/i2c/ast_i2c.c line 292
Quoted 4 lines
drivers/i2c/ast_i2c.c new file +4
-0+ +static const struct udevice_id ast_i2c_ids[] = { + {.compatible ="aspeed,ast2400-i2c-controller" ,}, + {.compatible ="aspeed,ast2400-i2c-bus" ,},Your subject says g5, but your compatible strings say g4.
Quoted 8 lines
Quoted 2 lines
Your probe function doesn't test for which string you're using. Why do you have both -controller and -bus?
I think this has something to do with how the device tree is processed, but it seems that because i2c buses are specified under a single controller node, if I don't specify compatibility with -controller, it does not match -bus nodes.
I don't follow?
The hardware has a few registers that are common across many busses. The device tree describes them in the controller node, with the buses being children of this node.
Cheers,
Joel
Re: [PATCH 3/3] aspeed/g5: I2C driver.
Quoted 21 lines · Joel Stanley
Quoted 7 lines · Maxim Sloyko
Quoted 7 lines
drivers/i2c/ast_i2c.c line 292
Quoted 4 lines
drivers/i2c/ast_i2c.c new file +4
-0+ +static const struct udevice_id ast_i2c_ids[] = { + {.compatible ="aspeed,ast2400-i2c-controller" ,}, + {.compatible ="aspeed,ast2400-i2c-bus" ,},Your subject says g5, but your compatible strings say g4.
Quoted 5 lines
Quoted 2 lines
Your probe function doesn't test for which string you're using. Why do you have both -controller and -bus?
I think this has something to do with how the device tree is processed,
but
Quoted 2 lines
it seems that because i2c buses are specified under a single controller node, if I don't specify compatibility with -controller, it does not
match
Quoted 1 line
-bus nodes.
I don't follow?
Quoted 8 lines
The hardware has a few registers that are common across many busses. The device tree describes them in the controller node, with the buses being children of this node.
Cheers,
Joel
I don't use them in this driver. At least not directly.
What are you proposing?
Signature · 1 line
*M*axim *S*loyko
PATCH 1/1 aspeed/g5,g4: I2C driver.
In reply to [email protected]From: Maxim Sloyko <[email protected]>
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
--- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 301 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 157 ++++++++++++++++++++++++++ 4 files changed, 465 insertions(+) create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h
drivers/i2c/Kconfig +6 -0
@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. +config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2C
drivers/i2c/Makefile +1 -0
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
drivers/i2c/ast_i2c.c new file +301 -0
301 lines not on this page · raw message
drivers/i2c/ast_i2c.h new file +157 -0
157 lines not on this page · raw message
Signature · 1 line
2.8.0.rc3.226.g39d4020
Re: [PATCH] aspeed/g5,g4: I2C driver.
Hello Maxim,
Quoted 5 lines · On 10/03/2016 10:42 PM, [email protected] wrote:
From: Maxim Sloyko <[email protected]>
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
I don't think this is a problem for the moment.
You should add your SoB here :
Quoted 14 lines
--- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 301 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 157 ++++++++++++++++++++++++++ 4 files changed, 465 insertions(+) create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.hdrivers/i2c/Kconfig +0
-0
drivers/i2c/Kconfig config SYS_I2C_CADENCE · line 73
Quoted 9 lines
drivers/i2c/Kconfig +6
-0@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. +config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. +
You need a little more description here to make checkpatch happy.
It would be nice to include the other CONFIG the patch need to compile, that is DM and DM_I2C I think.
Using DM is a good idea, this is the way to go for mainline. There are a few other drivers that need a conversion.
Quoted 89 lines
drivers/i2c/Kconfig +0
-0config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2Cdrivers/i2c/Makefile +1
-0@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.odrivers/i2c/ast_i2c.c new file +68
-0@@ -0,0 +1,301 @@ +/* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* Copyright 2016 IBM Corporation +* Copyright 2016 Google, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> + +#include <asm/arch/ast_scu.h> +#include <asm/arch/regs-scu.h> +#include <asm/io.h> + +#include "ast_i2c.h" + +#define I2C_TIMEOUT_US (100000) +#define I2C_SLEEP_STEP (20) +#define EI2C_TIMEOUT (1001) + +DECLARE_GLOBAL_DATA_PTR ; + +struct ast_i2c { +u32 id; +struct ast_i2c_regs *regs; +int speed; +}; + +static u32 get_clk_reg_val (u32 divider_ratio) +{ +unsigned int inc =0 , div; +u32 scl_low, scl_high, data; + +for (div =0 ; divider_ratio >=16 ; div++) { + inc |= (divider_ratio &1 ); + divider_ratio >>=1 ; + } + divider_ratio += inc; + scl_low = (divider_ratio >>1 ) -1 ; + scl_high = divider_ratio - scl_low -2 ; + data =0x77700300 | (scl_high <<16 ) | (scl_low <<12 ) | div; +return data; +} + +static inline void ast_i2c_clear_interrupts (struct ast_i2c_regs *i2c_base) +{ +writel (~0 , &i2c_base->isr); +} + +static void ast_i2c_init_bus (struct ast_i2c *i2c_bus) +{ +/* Reset device */ +writel (0 , &i2c_bus->regs->fcr); +/* Enable Master Mode. Assuming single-master. */ +debug ("Enable Master for %p\n" , i2c_bus->regs); +setbits_le32 (&i2c_bus->regs->fcr, +AST_I2CD_MASTER_EN + |AST_I2CD_M_SDA_LOCK_EN + |AST_I2CD_MULTI_MASTER_DIS |AST_I2CD_M_SCL_DRIVE_EN ); +debug ("FCR: %p\n" , &i2c_bus->regs->fcr); +/* Enable Interrupts */ +writel (AST_I2CD_INTR_TX_ACK + |AST_I2CD_INTR_TX_NAK + |AST_I2CD_INTR_RX_DONE + | AST_I2CD_INTR_BUS_RECOVER_DONE
drivers/i2c/ast_i2c.c line 78
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ | AST_I2CD_INTR_NORMAL_STOP + | AST_I2CD_INTR_ABNORMAL, &i2c_bus->regs->icr); +} + +static int ast_i2c_probe (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); + +debug ("Enabling I2C%u \n" , dev->seq); +ast_scu_enable_i2c (dev->seq);
I don't see that routine in the u-boot openbmc uses. Which version are you on ?
Quoted 160 lines
drivers/i2c/ast_i2c.c new file +160
-0+ i2c_bus->id = dev->seq; +struct ast_i2c_regs *i2c_base = + (struct ast_i2c_regs *)dev_get_addr (dev); + i2c_bus->regs = i2c_base; + +ast_i2c_init_bus (i2c_bus); +return 0 ; +} + +static inline int ast_i2c_wait_isr (struct ast_i2c_regs *i2c_base,u32 flag) +{ +int timeout =I2C_TIMEOUT_US ; +while (!(readl (&i2c_base->isr) & flag) && timeout >0 ) { +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +ast_i2c_clear_interrupts (i2c_base); +if (timeout <=0 ) +return -EI2C_TIMEOUT ; +return 0 ; +} + +static inline int ast_i2c_send_stop (struct ast_i2c_regs *i2c_base) +{ +writel (AST_I2CD_M_STOP_CMD , &i2c_base->csr); +return ast_i2c_wait_isr (i2c_base,AST_I2CD_INTR_NORMAL_STOP ); +} + +static inline int ast_i2c_wait_tx (struct ast_i2c_regs *i2c_base) +{ +int timeout =I2C_TIMEOUT_US ; +u32 flag =AST_I2CD_INTR_TX_ACK |AST_I2CD_INTR_TX_NAK ; +u32 status =readl (&i2c_base->isr) & flag; +while (!status && timeout >0 ) { + status =readl (&i2c_base->isr) & flag; +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +int ret =0 ; +if (status ==AST_I2CD_INTR_TX_NAK ) { + ret = -EREMOTEIO ; + } + +if (timeout <=0 ) { + ret = -EI2C_TIMEOUT ; + } + +ast_i2c_clear_interrupts (i2c_base); +return ret; +} + +static inline int ast_i2c_start_txn (struct ast_i2c_regs *i2c_base,u8 devaddr) +{ +/* Start and Send Device Address */ +writel (devaddr, &i2c_base->trbbr); +writel (AST_I2CD_M_START_CMD |AST_I2CD_M_TX_CMD , &i2c_base->csr); +return ast_i2c_wait_tx (i2c_base); +} + +static int ast_i2c_read_data (struct ast_i2c *i2c_bus,u8 chip_addr,u8 *buffer, +size_t len) +{ +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +int i2c_error =ast_i2c_start_txn (i2c_base, (chip_addr <<1 ) |I2C_M_RD ); +if (i2c_error <0 ) { +return i2c_error; + } + +u32 i2c_cmd =AST_I2CD_M_RX_CMD ; +for (; len >0 ; len--, buffer++) { +if (len ==1 ) { + i2c_cmd |=AST_I2CD_M_S_RX_CMD_LAST ; + } +writel (i2c_cmd, &i2c_base->csr); + i2c_error =ast_i2c_wait_isr (i2c_base,AST_I2CD_INTR_RX_DONE ); +if (i2c_error <0 ) { +return i2c_error; + } + *buffer =AST_I2CD_RX_DATA_BUF_GET (readl (&i2c_base->trbbr)); + } +ast_i2c_clear_interrupts (i2c_base); +return ast_i2c_send_stop (i2c_base); +} + +static int ast_i2c_write_data (struct ast_i2c *i2c_bus,u8 chip_addr,u8 + *buffer,size_t len) +{ +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +int i2c_error =ast_i2c_start_txn (i2c_base, (chip_addr <<1 )); +if (i2c_error <0 ) { +return i2c_error; + } + +for (; len >0 ; len--, buffer++) { +writel (*buffer, &i2c_base->trbbr); +writel (AST_I2CD_M_TX_CMD , &i2c_base->csr); + i2c_error =ast_i2c_wait_tx (i2c_base); +if (i2c_error <0 ) { +return i2c_error; + } + } +return ast_i2c_send_stop (i2c_base); +} + +static int ast_i2c_deblock (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +u32 csr =readl (&i2c_base->csr); +debug ("Bus hung (%x), attempting recovery\n" , csr); + +int deblock_error =0 ; +bool sda_high = csr &AST_I2CD_SDA_LINE_STS ; +bool scl_high = csr &AST_I2CD_SCL_LINE_STS ; +if (sda_high && scl_high) { +/* Bus is idle, no deblocking needed. */ +return 0 ; + }else if (sda_high) { +/* Send stop command */ + deblock_error =ast_i2c_send_stop (i2c_base); + }else if (scl_high) { +/* Possibly stuck slave */ +writel (AST_I2CD_BUS_RECOVER_CMD , &i2c_base->csr); + deblock_error =ast_i2c_wait_isr (i2c_base, +AST_I2CD_INTR_BUS_RECOVER_DONE ); + }else { +/* Just try to reinit the device. */ +ast_i2c_init_bus (i2c_bus); + } + +return deblock_error; +} + +static int ast_i2c_xfer (struct udevice *dev,struct i2c_msg *msg,int nmsgs) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +int ret; + +debug ("i2c_xfer: %d messages\n" , nmsgs); +for (; nmsgs >0 ; nmsgs--, msg++) { +if (msg->flags &I2C_M_RD ) { +debug ("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n" , + msg->addr, msg->len, msg->flags); + ret = +ast_i2c_read_data (i2c_bus, msg->addr, msg->buf, + msg->len); + }else { +debug ("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n" , + msg->addr, msg->len, msg->flags); + ret = +ast_i2c_write_data (i2c_bus, msg->addr, msg->buf, + msg->len); + } +if (ret) { +debug ("%s: error (%d)\n" , __func__, ret);
drivers/i2c/ast_i2c.c line 249
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+return -EREMOTEIO ; + } + } + +return 0 ; +} + +static int ast_i2c_set_speed (struct udevice *dev,unsigned int speed) +{ +debug ("Setting speed ofr I2C%d to <%u>\n" , dev->seq, speed);
typo
drivers/i2c/ast_i2c.c line 258
Quoted 9 lines
drivers/i2c/ast_i2c.c new file +9
-0+if (!speed) { +debug ("No valid speed specified.\n" ); +return -EINVAL ; + } +struct ast_i2c *i2c_bus =dev_get_priv (dev); + + i2c_bus->speed = speed; +/* TODO: get this from device tree */ +u32 pclk =ast_get_apbclk ();
that routine is unknown also.
Thanks,
C.
Quoted 207 lines
drivers/i2c/ast_i2c.c new file +43
-0+u32 divider = pclk / speed; + +struct ast_i2c_regs *i2c_base = i2c_bus->regs; +if (speed >400000 ) { +debug ("Enabling High Speed\n" ); +setbits_le32 (&i2c_base->fcr,AST_I2CD_M_HIGH_SPEED_EN + |AST_I2CD_M_SDA_DRIVE_1T_EN + |AST_I2CD_SDA_DRIVE_1T_EN ); +writel (0x3 , &i2c_base->cactcr2); +writel (get_clk_reg_val (divider), &i2c_base->cactcr1); + }else { +debug ("Enabling Normal Speed\n" ); +writel (get_clk_reg_val (divider), &i2c_base->cactcr1); +writel (AST_NO_TIMEOUT_CTRL , &i2c_base->cactcr2); + } + +ast_i2c_clear_interrupts (i2c_base); +return 0 ; +} + +static const struct dm_i2c_ops ast_i2c_ops = { + .xfer = ast_i2c_xfer, + .set_bus_speed = ast_i2c_set_speed, + .deblock = ast_i2c_deblock, +}; + +static const struct udevice_id ast_i2c_ids[] = { + {.compatible ="aspeed,ast2400-i2c-controller" ,}, + {.compatible ="aspeed,ast2400-i2c-bus" ,}, + {}, +}; + +/* Tell GNU Indent to keep this as is: */ +/* *INDENT-OFF* */ +U_BOOT_DRIVER (i2c_aspeed) = { + .name ="i2c_aspeed" , + .id =UCLASS_I2C , + .of_match = ast_i2c_ids, + .probe = ast_i2c_probe, + .priv_auto_alloc_size =sizeof (struct ast_i2c ), + .ops = &ast_i2c_ops, +}; +/* *INDENT-ON* */ drivers/i2c/ast_i2c.h new file +157
-0@@ -0,0 +1,157 @@ +/* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* Copyright 2016 IBM Corporation +* Copyright 2016 Google, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __AST_I2C_H_ +#define __AST_I2C_H_ + +struct ast_i2c_regs { +uint32_t fcr; +uint32_t cactcr1; +uint32_t cactcr2; +uint32_t icr; +uint32_t isr; +uint32_t csr; +uint32_t sdar; +uint32_t pbcr; +uint32_t trbbr; +#ifdef CONFIG_TARGET_AST_G5 +uint32_t dma_mbar; +uint32_t dma_tlr; +#endif +}; + +/* Device Register Definition */ +/* 0x00 : I2CD Function Control Register */ +#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) +#define AST_I2CD_BUFF_SEL (x) (x << 20) // page 0 ~ 7 +#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) +#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) +#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) +#define AST_I2CD_MSB_STS (0x1 << 9) +#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) +#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) +#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) +#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) +#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) +#define AST_I2CD_DEF_ARP_EN (0x1 << 3) +#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) +#define AST_I2CD_SLAVE_EN (0x1 << 1) +#define AST_I2CD_MASTER_EN (0x1 ) + +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ +#define AST_I2CD_tBUF (0x1 << 28) // 0~7 +#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7 +#define AST_I2CD_tACST (0x1 << 20) // 0~7 +#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7 +#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7 +#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7 +#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3 +#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf + +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ +#define AST_I2CD_tTIMEOUT (0x1 ) // 0~7 +#define AST_NO_TIMEOUT_CTRL 0x0 + +/* 0x0c : I2CD Interrupt Control Register & +* 0x10 : I2CD Interrupt Status Register +* +* These share bit definitions, so use the same values for the enable & +* status bits. +*/ +#define AST_I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) +#define AST_I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) +#define AST_I2CD_INTR_SMBUS_ALERT (0x1 << 12) +#define AST_I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) +#define AST_I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) +#define AST_I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) +#define AST_I2CD_INTR_GCALL_ADDR (0x1 << 8) +#define AST_I2CD_INTR_SLAVE_MATCH (0x1 << 7) +#define AST_I2CD_INTR_SCL_TIMEOUT (0x1 << 6) +#define AST_I2CD_INTR_ABNORMAL (0x1 << 5) +#define AST_I2CD_INTR_NORMAL_STOP (0x1 << 4) +#define AST_I2CD_INTR_ARBIT_LOSS (0x1 << 3) +#define AST_I2CD_INTR_RX_DONE (0x1 << 2) +#define AST_I2CD_INTR_TX_NAK (0x1 << 1) +#define AST_I2CD_INTR_TX_ACK (0x1 << 0) + +/* 0x14 : I2CD Command/Status Register */ +#define AST_I2CD_SDA_OE (0x1 << 28) +#define AST_I2CD_SDA_O (0x1 << 27) +#define AST_I2CD_SCL_OE (0x1 << 26) +#define AST_I2CD_SCL_O (0x1 << 25) +#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3 +#define AST_I2CD_TX_STATUS (0x1 << 23) + +// Tx State Machine +#define AST_I2CD_IDLE 0x0 +#define AST_I2CD_MACTIVE 0x8 +#define AST_I2CD_MSTART 0x9 +#define AST_I2CD_MSTARTR 0xa +#define AST_I2CD_MSTOP 0xb +#define AST_I2CD_MTXD 0xc +#define AST_I2CD_MRXACK 0xd +#define AST_I2CD_MRXD 0xe +#define AST_I2CD_MTXACK 0xf +#define AST_I2CD_SWAIT 0x1 +#define AST_I2CD_SRXD 0x4 +#define AST_I2CD_STXACK 0x5 +#define AST_I2CD_STXD 0x6 +#define AST_I2CD_SRXACK 0x7 +#define AST_I2CD_RECOVER 0x3 + +#define AST_I2CD_SCL_LINE_STS (0x1 << 18) +#define AST_I2CD_SDA_LINE_STS (0x1 << 17) +#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) +#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) +#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) +#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) +#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) +#define AST_I2CD_BUS_RECOVER_CMD (0x1 << 11) +#define AST_I2CD_S_ALT_EN (0x1 << 10) +// 0 : DMA Buffer, 1: Pool Buffer +//AST1070 DMA register +#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) +#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) + +/* Command Bit */ +#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) +#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) +#define AST_I2CD_M_STOP_CMD (0x1 << 5) +#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) +#define AST_I2CD_M_RX_CMD (0x1 << 3) +#define AST_I2CD_S_TX_CMD (0x1 << 2) +#define AST_I2CD_M_TX_CMD (0x1 << 1) +#define AST_I2CD_M_START_CMD (0x1 ) + +/* 0x18 : I2CD Slave Device Address Register */ + +/* 0x1C : I2CD Pool Buffer Control Register */ +#define AST_I2CD_RX_BUF_ADDR_GET (x) (((x) >> 24) & 0xff) +#define AST_I2CD_RX_BUF_END_ADDR_SET (x) ((x) << 16) +#define AST_I2CD_TX_DATA_BUF_END_SET (x) (((x) & 0xff) << 8) +#define AST_I2CD_RX_DATA_BUF_GET (x) (((x) >> 8) & 0xff) +#define AST_I2CD_BUF_BASE_ADDR_SET (x) ((x) & 0x3f) + +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ +#define AST_I2CD_GET_MODE (x) (((x) >> 8) & 0x1) + +#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8) +#define AST_I2CD_TX_BYTE_BUFFER (0xff ) + +//1. usage flag , 2 size, 3. request address +/* Use platform_data instead of module parameters */ +/* Fast Mode = 400 kHz, Standard = 100 kHz */ +//static int clock = 100; /* Default: 100 kHz */ + +#define AST_I2CD_CMDS (AST_I2CD_BUS_RECOVER_CMD_EN | \ + AST_I2CD_M_STOP_CMD | \ + AST_I2CD_M_S_RX_CMD_LAST | \ + AST_I2CD_M_RX_CMD | \ + AST_I2CD_M_TX_CMD | \ + AST_I2CD_M_START_CMD) + +#endif /* _ASPEED_REGS_I2C_H_ */
Re: [PATCH] aspeed/g5,g4: I2C driver.
Hi Cedric,
Quoted 5 lines · Cédric Le Goater
Hello Maxim,
Quoted 2 lines · On 10/03/2016 10:42 PM, [email protected] wrote:
From: Maxim Sloyko <[email protected]>
Quoted 8 lines
Quoted 3 lines
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
I don't think this is a problem for the moment.
You should add your SoB here :
What is SoB?
Quoted 133 lines
Quoted 5 lines
--- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 301 ++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/i2c/Kconfig config SYS_I2C_CADENCE · line 65
Quoted 11 lines
drivers/i2c/ast_i2c.h | 157 ++++++++++++++++++++++++++ 4 files changed, 465 insertions(+) create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.hdrivers/i2c/Kconfig +0
-0@@ -65,6 +65,12 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. Thiscontroller is
drivers/i2c/Kconfig config SYS_I2C_CADENCE · line 73
Quoted 8 lines
drivers/i2c/Kconfig +6
-0e.g. used by Xilinx Zynq. +config SYS_I2C_AST + tristate "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. +You need a little more description here to make checkpatch happy.
It would be nice to include the other CONFIG the patch need to compile, that is DM and
DM_I2CI think.Using DM is a good idea, this is the way to go for mainline. There are a few other drivers that need a conversion.
Quoted 59 lines
drivers/i2c/Kconfig +0
-0config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2Cdrivers/i2c/Makefile +1
-0@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.odrivers/i2c/ast_i2c.c new file +38
-0@@ -0,0 +1,301 @@ +/* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* Copyright 2016 IBM Corporation +* Copyright 2016 Google, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> + +#include <asm/arch/ast_scu.h> +#include <asm/arch/regs-scu.h> +#include <asm/io.h> + +#include "ast_i2c.h" + +#define I2C_TIMEOUT_US (100000) +#define I2C_SLEEP_STEP (20) +#define EI2C_TIMEOUT (1001) + +DECLARE_GLOBAL_DATA_PTR ; + +struct ast_i2c { +u32 id; +struct ast_i2c_regs *regs; +int speed; +}; + +static u32 get_clk_reg_val (u32 divider_ratio) +{ +unsigned int inc =0 , div; +u32 scl_low, scl_high, data; + +for (div =0 ; divider_ratio >=16 ; div++) { + inc |= (divider_ratio &1 );drivers/i2c/ast_i2c.c line 48
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ divider_ratio >>=1 ; + } + divider_ratio += inc; + scl_low = (divider_ratio >>1 ) -1 ; + scl_high = divider_ratio - scl_low -2 ; + data =0x77700300 | (scl_high <<16 ) | (scl_low <<12 ) | div; +return data; +} + +static inline void ast_i2c_clear_interrupts(struct ast_i2c_regs
*i2c_base)Quoted 4 lines
drivers/i2c/ast_i2c.c new file +4
-0+{ +writel (~0 , &i2c_base->isr); +} +drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+static void ast_i2c_init_bus (struct ast_i2c *i2c_bus) +{ +/* Reset device */ +writel (0 , &i2c_bus->regs->fcr); +/* Enable Master Mode. Assuming single-master. */ +debug ("Enable Master for %p\n" , i2c_bus->regs); + setbits_le32(&i2c_bus->regs->fcr, + AST_I2CD_MASTER_EN + | AST_I2CD_M_SDA_LOCK_EN + | AST_I2CD_MULTI_MASTER_DIS |
AST_I2CD_M_SCL_DRIVE_EN);Quoted 12 lines
drivers/i2c/ast_i2c.c new file +12
-0+debug ("FCR: %p\n" , &i2c_bus->regs->fcr); +/* Enable Interrupts */ +writel (AST_I2CD_INTR_TX_ACK + |AST_I2CD_INTR_TX_NAK + |AST_I2CD_INTR_RX_DONE + |AST_I2CD_INTR_BUS_RECOVER_DONE + |AST_I2CD_INTR_NORMAL_STOP + |AST_I2CD_INTR_ABNORMAL , &i2c_bus->regs->icr); +} + +static int ast_i2c_probe (struct udevice *dev) +{
Quoted 9 lines
drivers/i2c/ast_i2c.c line 78
Quoted 4 lines
drivers/i2c/ast_i2c.c new file +4
-0+struct ast_i2c *i2c_bus =dev_get_priv (dev); + +debug ("Enabling I2C%u \n" , dev->seq); +ast_scu_enable_i2c (dev->seq);I don't see that routine in the u-boot openbmc uses. Which version are you on ?
It's in another patch that is also under review. SCU helper functions or something like that.
Quoted 195 lines
drivers/i2c/ast_i2c.c
Quoted 11 lines
drivers/i2c/ast_i2c.c new file +10
-0+ i2c_bus->id = dev->seq; +struct ast_i2c_regs *i2c_base = + (struct ast_i2c_regs *)dev_get_addr (dev); + i2c_bus->regs = i2c_base; + +ast_i2c_init_bus (i2c_bus); +return 0 ; +} + +static inline int ast_i2c_wait_isr(struct ast_i2c_regs *i2c_base, u32flag)
Quoted 34 lines
drivers/i2c/ast_i2c.c new file +34
-0+{ +int timeout =I2C_TIMEOUT_US ; +while (!(readl (&i2c_base->isr) & flag) && timeout >0 ) { +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +ast_i2c_clear_interrupts (i2c_base); +if (timeout <=0 ) +return -EI2C_TIMEOUT ; +return 0 ; +} + +static inline int ast_i2c_send_stop (struct ast_i2c_regs *i2c_base) +{ +writel (AST_I2CD_M_STOP_CMD , &i2c_base->csr); +return ast_i2c_wait_isr (i2c_base,AST_I2CD_INTR_NORMAL_STOP ); +} + +static inline int ast_i2c_wait_tx (struct ast_i2c_regs *i2c_base) +{ +int timeout =I2C_TIMEOUT_US ; +u32 flag =AST_I2CD_INTR_TX_ACK |AST_I2CD_INTR_TX_NAK ; +u32 status =readl (&i2c_base->isr) & flag; +while (!status && timeout >0 ) { + status =readl (&i2c_base->isr) & flag; +udelay (I2C_SLEEP_STEP ); + timeout -=I2C_SLEEP_STEP ; + } + +int ret =0 ; +if (status ==AST_I2CD_INTR_TX_NAK ) { + ret = -EREMOTEIO ; + }drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+ +if (timeout <=0 ) { + ret = -EI2C_TIMEOUT ; + } + +ast_i2c_clear_interrupts (i2c_base); +return ret; +} + +static inline int ast_i2c_start_txn(struct ast_i2c_regs *i2c_base, u8devaddr)
drivers/i2c/ast_i2c.c
Quoted 8 lines
drivers/i2c/ast_i2c.c new file +8
-0+{ +/* Start and Send Device Address */ +writel (devaddr, &i2c_base->trbbr); +writel (AST_I2CD_M_START_CMD |AST_I2CD_M_TX_CMD , &i2c_base->csr); +return ast_i2c_wait_tx (i2c_base); +} + +static int ast_i2c_read_data(struct ast_i2c *i2c_bus, u8 chip_addr, u8*buffer,
drivers/i2c/ast_i2c.c
Quoted 5 lines
drivers/i2c/ast_i2c.c new file +5
-0+ size_t len) +{ +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + + int i2c_error = ast_i2c_start_txn(i2c_base, (chip_addr << 1) |
I2C_M_RD);drivers/i2c/ast_i2c.c
Quoted 11 lines
drivers/i2c/ast_i2c.c new file +11
-0+if (i2c_error <0 ) { +return i2c_error; + } + +u32 i2c_cmd =AST_I2CD_M_RX_CMD ; +for (; len >0 ; len--, buffer++) { +if (len ==1 ) { + i2c_cmd |=AST_I2CD_M_S_RX_CMD_LAST ; + } +writel (i2c_cmd, &i2c_base->csr); + i2c_error = ast_i2c_wait_isr(i2c_base,
AST_I2CD_INTR_RX_DONE);drivers/i2c/ast_i2c.c
Quoted 4 lines
drivers/i2c/ast_i2c.c new file +4
-0+if (i2c_error <0 ) { +return i2c_error; + } + *buffer = AST_I2CD_RX_DATA_BUF_GET(
readl(&i2c_base->trbbr));Quoted 38 lines
drivers/i2c/ast_i2c.c new file +38
-0+ } +ast_i2c_clear_interrupts (i2c_base); +return ast_i2c_send_stop (i2c_base); +} + +static int ast_i2c_write_data (struct ast_i2c *i2c_bus,u8 chip_addr,u8 + *buffer,size_t len) +{ +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +int i2c_error =ast_i2c_start_txn (i2c_base, (chip_addr <<1 )); +if (i2c_error <0 ) { +return i2c_error; + } + +for (; len >0 ; len--, buffer++) { +writel (*buffer, &i2c_base->trbbr); +writel (AST_I2CD_M_TX_CMD , &i2c_base->csr); + i2c_error =ast_i2c_wait_tx (i2c_base); +if (i2c_error <0 ) { +return i2c_error; + } + } +return ast_i2c_send_stop (i2c_base); +} + +static int ast_i2c_deblock (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +struct ast_i2c_regs *i2c_base = i2c_bus->regs; + +u32 csr =readl (&i2c_base->csr); +debug ("Bus hung (%x), attempting recovery\n" , csr); + +int deblock_error =0 ; +bool sda_high = csr &AST_I2CD_SDA_LINE_STS ; +bool scl_high = csr &AST_I2CD_SCL_LINE_STS ; +if (sda_high && scl_high) {drivers/i2c/ast_i2c.c
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+/* Bus is idle, no deblocking needed. */ +return 0 ; + }else if (sda_high) { +/* Send stop command */ + deblock_error =ast_i2c_send_stop (i2c_base); + }else if (scl_high) { +/* Possibly stuck slave */ +writel (AST_I2CD_BUS_RECOVER_CMD , &i2c_base->csr); + deblock_error =ast_i2c_wait_isr (i2c_base, + AST_I2CD_INTR_BUS_RECOVER_DONE);
drivers/i2c/ast_i2c.c
Quoted 9 lines
drivers/i2c/ast_i2c.c new file +9
-0+ }else { +/* Just try to reinit the device. */ +ast_i2c_init_bus (i2c_bus); + } + +return deblock_error; +} + +static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, intnmsgs)
drivers/i2c/ast_i2c.c
Quoted 8 lines
drivers/i2c/ast_i2c.c new file +8
-0+{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); +int ret; + +debug ("i2c_xfer: %d messages\n" , nmsgs); +for (; nmsgs >0 ; nmsgs--, msg++) { +if (msg->flags &I2C_M_RD ) { + debug("i2c_read: chip=0x%x, len=0x%x,flags=0x%x\n",
drivers/i2c/ast_i2c.c
Quoted 6 lines
drivers/i2c/ast_i2c.c new file +6
-0+ msg->addr, msg->len, msg->flags); + ret = +ast_i2c_read_data (i2c_bus, msg->addr, msg->buf, + msg->len); + }else { + debug("i2c_write: chip=0x%x, len=0x%x,flags=0x%x\n",
drivers/i2c/ast_i2c.c
Quoted 3 lines
drivers/i2c/ast_i2c.c new file +3
-0+ msg->addr, msg->len, msg->flags); + ret = + ast_i2c_write_data(i2c_bus, msg->addr,
msg->buf,Quoted 4 lines
drivers/i2c/ast_i2c.c new file +4
-0+ msg->len); + } +if (ret) { +debug ("%s: error (%d)\n" , __func__, ret);drivers/i2c/ast_i2c.c line 249
Quoted 10 lines
drivers/i2c/ast_i2c.c new file +10
-0+return -EREMOTEIO ; + } + } + +return 0 ; +} + +static int ast_i2c_set_speed (struct udevice *dev,unsigned int speed) +{ +debug ("Setting speed ofr I2C%d to <%u>\n" , dev->seq, speed);typo
drivers/i2c/ast_i2c.c line 258
Quoted 9 lines
drivers/i2c/ast_i2c.c new file +9
-0+if (!speed) { +debug ("No valid speed specified.\n" ); +return -EINVAL ; + } +struct ast_i2c *i2c_bus =dev_get_priv (dev); + + i2c_bus->speed = speed; +/* TODO: get this from device tree */ +u32 pclk =ast_get_apbclk ();
Quoted 2 lines
that routine is unknown also.
This one too.
Quoted 231 lines
Thanks,
C.
Quoted 69 lines
drivers/i2c/ast_i2c.c new file +43
-0+u32 divider = pclk / speed; + +struct ast_i2c_regs *i2c_base = i2c_bus->regs; +if (speed >400000 ) { +debug ("Enabling High Speed\n" ); +setbits_le32 (&i2c_base->fcr,AST_I2CD_M_HIGH_SPEED_EN + |AST_I2CD_M_SDA_DRIVE_1T_EN + |AST_I2CD_SDA_DRIVE_1T_EN ); +writel (0x3 , &i2c_base->cactcr2); +writel (get_clk_reg_val (divider), &i2c_base->cactcr1); + }else { +debug ("Enabling Normal Speed\n" ); +writel (get_clk_reg_val (divider), &i2c_base->cactcr1); +writel (AST_NO_TIMEOUT_CTRL , &i2c_base->cactcr2); + } + +ast_i2c_clear_interrupts (i2c_base); +return 0 ; +} + +static const struct dm_i2c_ops ast_i2c_ops = { + .xfer = ast_i2c_xfer, + .set_bus_speed = ast_i2c_set_speed, + .deblock = ast_i2c_deblock, +}; + +static const struct udevice_id ast_i2c_ids[] = { + {.compatible ="aspeed,ast2400-i2c-controller" ,}, + {.compatible ="aspeed,ast2400-i2c-bus" ,}, + {}, +}; + +/* Tell GNU Indent to keep this as is: */ +/* *INDENT-OFF* */ +U_BOOT_DRIVER (i2c_aspeed) = { + .name ="i2c_aspeed" , + .id =UCLASS_I2C , + .of_match = ast_i2c_ids, + .probe = ast_i2c_probe, + .priv_auto_alloc_size =sizeof (struct ast_i2c ), + .ops = &ast_i2c_ops, +}; +/* *INDENT-ON* */ drivers/i2c/ast_i2c.h new file +20
-0@@ -0,0 +1,157 @@ +/* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* Copyright 2016 IBM Corporation +* Copyright 2016 Google, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __AST_I2C_H_ +#define __AST_I2C_H_ + +struct ast_i2c_regs { + uint32_t fcr; + uint32_t cactcr1; + uint32_t cactcr2; + uint32_t icr; + uint32_t isr; + uint32_t csr; + uint32_t sdar; + uint32_t pbcr; + uint32_t trbbr;drivers/i2c/ast_i2c.h line 30
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#ifdef CONFIG_TARGET_AST_G5 +uint32_t dma_mbar; +uint32_t dma_tlr; +#endif +}; + +/* Device Register Definition */ +/* 0x00 : I2CD Function Control Register */ +#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) +#define AST_I2CD_BUFF_SEL (x) (x << 20)// page 0 ~ 7Quoted 6 lines
drivers/i2c/ast_i2c.h new file +6
-0+#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) +#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) +#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) +#define AST_I2CD_MSB_STS (0x1 << 9) +#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) +#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)drivers/i2c/ast_i2c.h
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) +#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) +#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) +#define AST_I2CD_DEF_ARP_EN (0x1 << 3) +#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) +#define AST_I2CD_SLAVE_EN (0x1 << 1) +#define AST_I2CD_MASTER_EN (0x1 ) + +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ +#define AST_I2CD_tBUF(
0x1<< 28) // 0~7drivers/i2c/ast_i2c.h line 47
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tHDSTA(
0x1<< 24) // 0~7drivers/i2c/ast_i2c.h line 48
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tACST(
0x1<< 20) // 0~7drivers/i2c/ast_i2c.h line 49
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tCKHIGH (0x1 <<16) // 0~7
drivers/i2c/ast_i2c.h line 50
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drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tCKLOW(
0x1<< 12) // 0~7drivers/i2c/ast_i2c.h line 51
Quoted 1 line
drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_tHDDAT(
0x1<< 10) // 0~7drivers/i2c/ast_i2c.h line 52
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drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) //0~3
drivers/i2c/ast_i2c.h line 53
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drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_CLK_BASE_DIV (0x1 ) //0~0xf
drivers/i2c/ast_i2c.h
Quoted 3 lines
drivers/i2c/ast_i2c.h new file +3
-0+ +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ +#define AST_I2CD_tTIMEOUT (0x1 ) //0~7
Quoted 20 lines
drivers/i2c/ast_i2c.h new file +20
-0+#define AST_NO_TIMEOUT_CTRL 0x0 + +/* 0x0c : I2CD Interrupt Control Register & +* 0x10 : I2CD Interrupt Status Register +* +* These share bit definitions, so use the same values for the enable & +* status bits. +*/ +#define AST_I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) +#define AST_I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) +#define AST_I2CD_INTR_SMBUS_ALERT (0x1 << 12) +#define AST_I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) +#define AST_I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) +#define AST_I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) +#define AST_I2CD_INTR_GCALL_ADDR (0x1 << 8) +#define AST_I2CD_INTR_SLAVE_MATCH (0x1 << 7) +#define AST_I2CD_INTR_SCL_TIMEOUT (0x1 << 6) +#define AST_I2CD_INTR_ABNORMAL (0x1 << 5) +#define AST_I2CD_INTR_NORMAL_STOP (0x1 << 4) +#define AST_I2CD_INTR_ARBIT_LOSS (0x1 << 3)drivers/i2c/ast_i2c.h
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#define AST_I2CD_INTR_RX_DONE (0x1 << 2) +#define AST_I2CD_INTR_TX_NAK (0x1 << 1) +#define AST_I2CD_INTR_TX_ACK (0x1 << 0) + +/* 0x14 : I2CD Command/Status Register */ +#define AST_I2CD_SDA_OE (0x1 << 28) +#define AST_I2CD_SDA_O (0x1 << 27) +#define AST_I2CD_SCL_OE (0x1 << 26) +#define AST_I2CD_SCL_O (0x1 << 25) +#define AST_I2CD_TX_TIMING (0x1 << 24) //0 ~3
Quoted 37 lines
drivers/i2c/ast_i2c.h new file +37
-0+#define AST_I2CD_TX_STATUS (0x1 << 23) + +// Tx State Machine +#define AST_I2CD_IDLE 0x0 +#define AST_I2CD_MACTIVE 0x8 +#define AST_I2CD_MSTART 0x9 +#define AST_I2CD_MSTARTR 0xa +#define AST_I2CD_MSTOP 0xb +#define AST_I2CD_MTXD 0xc +#define AST_I2CD_MRXACK 0xd +#define AST_I2CD_MRXD 0xe +#define AST_I2CD_MTXACK 0xf +#define AST_I2CD_SWAIT 0x1 +#define AST_I2CD_SRXD 0x4 +#define AST_I2CD_STXACK 0x5 +#define AST_I2CD_STXD 0x6 +#define AST_I2CD_SRXACK 0x7 +#define AST_I2CD_RECOVER 0x3 + +#define AST_I2CD_SCL_LINE_STS (0x1 << 18) +#define AST_I2CD_SDA_LINE_STS (0x1 << 17) +#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) +#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) +#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) +#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) +#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) +#define AST_I2CD_BUS_RECOVER_CMD (0x1 << 11) +#define AST_I2CD_S_ALT_EN (0x1 << 10) +// 0 : DMA Buffer, 1: Pool Buffer +//AST1070 DMA register +#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) +#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) + +/* Command Bit */ +#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) +#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) +#define AST_I2CD_M_STOP_CMD (0x1 << 5)drivers/i2c/ast_i2c.h
Quoted 10 lines
drivers/i2c/ast_i2c.h new file +10
-0+#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) +#define AST_I2CD_M_RX_CMD (0x1 << 3) +#define AST_I2CD_S_TX_CMD (0x1 << 2) +#define AST_I2CD_M_TX_CMD (0x1 << 1) +#define AST_I2CD_M_START_CMD (0x1 ) + +/* 0x18 : I2CD Slave Device Address Register */ + +/* 0x1C : I2CD Pool Buffer Control Register */ +#define AST_I2CD_RX_BUF_ADDR_GET (x) (((x) >>24) &
0xff)drivers/i2c/ast_i2c.h line 134
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drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_RX_BUF_END_ADDR_SET (x) ((x) <<16)
drivers/i2c/ast_i2c.h line 135
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drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_TX_DATA_BUF_END_SET (x) (((x) &
0xff) << 8)drivers/i2c/ast_i2c.h line 137
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drivers/i2c/ast_i2c.h new file +2
-0+#define AST_I2CD_RX_DATA_BUF_GET (x) (((x) >> 8) & 0xff) +#define AST_I2CD_BUF_BASE_ADDR_SET (x) ((x) &
0x3f)drivers/i2c/ast_i2c.h
Quoted 3 lines
drivers/i2c/ast_i2c.h new file +3
-0+ +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ +#define AST_I2CD_GET_MODE (x) (((x) >>8) &
0x1)drivers/i2c/ast_i2c.h line 142
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drivers/i2c/ast_i2c.h new file +2
-0+ +#define AST_I2CD_RX_BYTE_BUFFER (
0xff<< 8)drivers/i2c/ast_i2c.h line 143
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drivers/i2c/ast_i2c.h new file +1
-0+#define AST_I2CD_TX_BYTE_BUFFER (
0xff)Quoted 15 lines
drivers/i2c/ast_i2c.h new file +14
-0+ +//1. usage flag , 2 size, 3. request address +/* Use platform_data instead of module parameters */ +/* Fast Mode = 400 kHz, Standard = 100 kHz */ +//static int clock = 100; /* Default: 100 kHz */ + +#define AST_I2CD_CMDS (AST_I2CD_BUS_RECOVER_CMD_EN | \ + AST_I2CD_M_STOP_CMD | \ + AST_I2CD_M_S_RX_CMD_LAST | \ + AST_I2CD_M_RX_CMD | \ + AST_I2CD_M_TX_CMD | \ + AST_I2CD_M_START_CMD) + +#endif /* _ASPEED_REGS_I2C_H_ */
Signature · 1 line
*M*axim *S*loyko
Joel Stanley
maintainerRe: [PATCH] aspeed/g5,g4: I2C driver.
Quoted 7 lines · Maxim Sloyko
Quoted 7 lines · On 10/03/2016 10:42 PM, [email protected] wrote:
Quoted 5 lines
From: Maxim Sloyko <[email protected]>
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
Quoted 6 lines
Quoted 3 lines
I don't think this is a problem for the moment.
You should add your SoB here :
What is SoB?
Signed-off-by. You can read more about it here:
I recommend having a read of the SubmittingPatches as well as
http://www.denx.de/wiki/U-Boot/Patches. While every rule has it's exception, it's good background for what is expected.
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/SubmittingPatches
http://www.denx.de/wiki/U-Boot/Patches
http://www.denx.de/wiki/U-Boot/CodingStyle
Quoted 13 lines
Quoted 11 lines
drivers/i2c/ast_i2c.c line 78
Quoted 7 lines
drivers/i2c/ast_i2c.c new file +7
-0+ +static int ast_i2c_probe (struct udevice *dev) +{ +struct ast_i2c *i2c_bus =dev_get_priv (dev); + +debug ("Enabling I2C%u \n" , dev->seq); +ast_scu_enable_i2c (dev->seq);I don't see that routine in the u-boot openbmc uses. Which version are you on ?
Quoted 2 lines
It's in another patch that is also under review. SCU helper functions or something like that.
You can make it clear by sending these patches as part of a series. Make them sequential commits in your local git branch, and then use git-format-patch to create a sequence of patches.
Your sequence should be bisectable, that is, at each point in history the tree should build (and hopefully boot). You can check this by using git rebase interactive's executable flag.
Cheers,
Joel
Re: [PATCH] aspeed/g5,g4: I2C driver.
In reply to Maxim SloykoHi Maxim,
Quoted 10 lines · Maxim Sloyko
Hi Cedric,
Quoted 5 lines · Cédric Le Goater
Hello Maxim,
Quoted 2 lines · On 10/03/2016 10:42 PM, [email protected] wrote:
From: Maxim Sloyko <[email protected]>
Quoted 8 lines
Quoted 7 lines
Quoted 3 lines
The driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
I don't think this is a problem for the moment.
You should add your SoB here :
What is SoB?
I expect Cédric means "Signed-off-by" in this case. U-boot requires it per:
http://www.denx.de/wiki/U-Boot/Patches#Attributing_Code_Copyrights_Sign
Also see the kernel's documentation on the tag for an explanation of what it's about:
A number of projects (e.g. u-boot) have adopted the same idea.
Cheers,
Andrew
Joel Stanley
maintainerRe: [PATCH 1/3] aspeed/g5: Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
In reply to [email protected]Quoted 6 lines · On Wed, Sep 28, 2016 at 3:13 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Fixed the bug in board initialization, which caused failures during boot with device tree.
The flags are used to modify malloc behaviour after relocation, resetting the flag caused it to fail.
This unrelated to the device tree additions and therefore should be in a separate patch.
The device tree additions look okay.
Quoted 622 lines
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 +++++++++++++++++++++++++++++++++++++++++ board/aspeed/ast-g5/ast-g5.c | 1 - 4 files changed, 571 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsiarch/arm/dts/Makefile +2
-0@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags herearch/arm/dts/aspeed-g5-evb.dts new file +28
-0@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};arch/arm/dts/aspeed-g5.dtsi new file +541
-0@@ -0,0 +1,541 @@ +/* The device tree is copied from + * https://github.com/openbmc/linux/blob/9ec9d09/arch/arm/boot/dts/aspeed-g5.dtsi + */ +#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + no-hw-checksum; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl@1e6e2000 { + compatible = "aspeed,g5-pinctrl"; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid1_default: gpid1_default { + function = "GPID1"; + groups = "GPID1"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + }; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers only one + // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + ibt: ibt@1e789140 { + compatible = "aspeed,bt-host"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x1c>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + vuart: vuart@1e787000 { + compatible = "aspeed,vuart"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + i2c: i2c@1e78a000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + compatible = "aspeed,ast2400-i2c-controller"; + reg = <0x1e78a000 0x40>; + ranges = <0 0x1e78a000 0x1000>; + interrupts = <12>; + clocks = <&clk_apb>; + clock-ranges; + interrupt-controller; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <0>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <0>; + interrupt-parent = <&i2c>; + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <1>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <1>; + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xC0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <2>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <3>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x140 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <4>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <5>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1C0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <6>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <7>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x340 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <8>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <9>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <9>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <10>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <10>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <11>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <11>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x440 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <12>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <12>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + bus = <13>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + }; + + }; + + }; + }; +};board/aspeed/ast-g5/ast-g5.c +0
-2@@ -52,7 +52,6 @@ int board_init(void) {/* adress of boot parameters */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ; - gd->flags =0 ;return 0 ; } --2.8.0.rc3.226.g39d4020
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Re: [PATCH 1/3] aspeed/g5: Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
Quoted 11 lines · Joel Stanley
Quoted 6 lines · On Wed, Sep 28, 2016 at 3:13 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Fixed the bug in board initialization, which caused failures during boot with device tree.
The flags are used to modify malloc behaviour after relocation, resetting the flag caused it to fail.This unrelated to the device tree additions and therefore should be in a separate patch.
This is related, because the device tree can't be used without this fix.
Quoted 685 lines
The device tree additions look okay.
Quoted 4 lines
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 +++++++++++++++++++++++++++++++++++++++++
Review
Quoted 19 lines
board/aspeed/ast-g5/ast-g5.c | 1 - 4 files changed, 571 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsiarch/arm/dts/Makefile +2
-0@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here(quoted diff) +0
-0
b/arch/arm/dts/aspeed-g5-evb.dtsQuoted 39 lines
new file mode 100644
index 0000000..95dc77aarch/arm/dts/aspeed-g5-evb.dts new file +28
-0@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};arch/arm/dts/aspeed-g5.dtsi new file +0
-0arch/arm/dts/aspeed-g5.dtsi line 2
Quoted 2 lines
arch/arm/dts/aspeed-g5.dtsi new file +2
-0@@ -0,0 +1,541 @@ +/* The device tree is copied from + * https://github.com/openbmc/linux/blob/9ec9d09/arch/arm/
boot/dts/aspeed-g5.dtsiQuoted 55 lines
arch/arm/dts/aspeed-g5.dtsi new file +55
-0+ */ +#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + no-hw-checksum; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>;arch/arm/dts/aspeed-g5.dtsi
Quoted 10 lines
arch/arm/dts/aspeed-g5.dtsi new file +10
-0+ ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,g5-scu", "syscon","simple-mfd";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl@1e6e2000 { + compatible = "aspeed,g5-pinctrl"; + + pinctrl_i2c9_default:
i2c9_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i2c10_default:
i2c10_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default:
i2c11_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default:
i2c12_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default:
i2c13_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_gpid0_default:
gpid0_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid1_default:
gpid1_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "GPID1"; + groups = "GPID1"; + }; + + pinctrl_sd1_default: sd1_default{
arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "SD1"; + groups = "SD1"; + }; + + pinctrl_i2c5_default:
i2c5_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default:
i2c6_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default:
i2c7_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default:
i2c8_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_pwm0_default:
pwm0_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default:
pwm1_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default:
pwm2_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default:
pwm3_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default:
pwm4_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default:
pwm5_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default:
pwm6_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default:
pwm7_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_i2c3_default:
i2c3_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default:
i2c4_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c14_default:
i2c14_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_rgmii1_default:
rgmii1_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rmii1_default:
rmii1_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rgmii2_default:
rgmii2_default{arch/arm/dts/aspeed-g5.dtsi
Quoted 5 lines
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii2_default:
rmii2_default{Quoted 41 lines
arch/arm/dts/aspeed-g5.dtsi new file +41
-0+ function = "RMII2"; + groups = "RMII2"; + }; + }; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller;arch/arm/dts/aspeed-g5.dtsi
Quoted 10 lines
arch/arm/dts/aspeed-g5.dtsi new file +10
-0+ compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registersonly one
Quoted 86 lines
arch/arm/dts/aspeed-g5.dtsi new file +86
-0+ // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + ibt: ibt@1e789140 { + compatible = "aspeed,bt-host"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x1c>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + vuart: vuart@1e787000 { + compatible = "aspeed,vuart"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&clk_uart>;arch/arm/dts/aspeed-g5.dtsi
Quoted 10 lines
arch/arm/dts/aspeed-g5.dtsi new file +10
-0+ no-loopback-test; + status = "disabled"; + }; + + i2c: i2c@1e78a000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + compatible = "aspeed,ast2400-i2c-controller";
arch/arm/dts/aspeed-g5.dtsi
Quoted 12 lines
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ reg = <0x1e78a000 0x40>; + ranges = <0 0x1e78a000 0x1000>; + interrupts = <12>; + clocks = <&clk_apb>; + clock-ranges; + interrupt-controller; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 12 lines
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <0>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <0>; + interrupt-parent = <&i2c>; + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 11 lines
arch/arm/dts/aspeed-g5.dtsi new file +11
-0+ bus = <1>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <1>; + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xC0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <2>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <2>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c3_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <3>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <3>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c4_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x140 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <4>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <4>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c5_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <5>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <5>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c6_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1C0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <6>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <6>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c7_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <7>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <7>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c8_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x340 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <8>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <8>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c9_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <9>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <9>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c10_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3c0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <10>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <10>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c11_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <11>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <11>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c12_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x440 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <12>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <12>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c13_default>;arch/arm/dts/aspeed-g5.dtsi
Quoted 7 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi
Quoted 6 lines
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <13>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <13>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c14_default>;Quoted 26 lines
arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + }; + + }; + }; +};board/aspeed/ast-g5/ast-g5.c +0
-2@@ -52,7 +52,6 @@ int board_init(void) {/* adress of boot parameters */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ; - gd->flags =0 ;return 0 ; } --2.8.0.rc3.226.g39d4020
_______________________________________________
openbmc mailing list
[email protected]
https://lists.ozlabs.org/listinfo/openbmc
Signature · 1 line
*M*axim *S*loyko
PATCH 1/1 aspeed/g5: Device Tree for ast2500
In reply to [email protected]From: Maxim Sloyko <[email protected]>
Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 571 insertions(+) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsi
arch/arm/dts/Makefile +2 -0
@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here
arch/arm/dts/aspeed-g5-evb.dts new file +28 -0
@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};
arch/arm/dts/aspeed-g5.dtsi new file +541 -0
541 lines not on this page · raw message
Signature · 1 line
2.8.0.rc3.226.g39d4020
Re: [PATCH] aspeed/g5: Device Tree for ast2500
Ping
Quoted 668 lines · On Thu, Sep 29, 2016 at 11:32 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 ++++++++++++++++++++++++++++++ +++++++++++ 3 files changed, 571 insertions(+) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsiarch/arm/dts/Makefile +2
-0@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags herearch/arm/dts/aspeed-g5-evb. renamed from arch/arm/dts/aspeed-g5-evb.dts +0
-0dts
new file mode 100644
index 0000000..95dc77aarch/arm/dts/aspeed-g5-evb.dts new file +28
-0@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};arch/arm/dts/aspeed-g5.dtsi new file +2
-0@@ -0,0 +1,541 @@ +/* The device tree is copied from + * https://github.com/openbmc/linux/blob/9ec9d09/arch/arm/
boot/dts/aspeed-g5.dtsi
+ */arch/arm/dts/aspeed-g5.dtsi new file +64
-0+#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + no-hw-checksum; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,g5-scu", "syscon","simple-mfd";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl@1e6e2000 { + compatible = "aspeed,g5-pinctrl"; + + pinctrl_i2c9_default: i2c9_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i2c10_default:
i2c10_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default:
i2c11_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default:
i2c12_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default:
i2c13_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_gpid0_default:
gpid0_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid1_default:
gpid1_default{arch/arm/dts/aspeed-g5.dtsi new file +10
-0+ function = "GPID1"; + groups = "GPID1"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_i2c5_default: i2c5_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_pwm0_default: pwm0_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_i2c3_default: i2c3_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c14_default:
i2c14_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_rgmii1_default:
rgmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rmii1_default:
rmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rgmii2_default:
rgmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii2_default:
rmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +51
-0+ function = "RMII2"; + groups = "RMII2"; + }; + }; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers onlyone
arch/arm/dts/aspeed-g5.dtsi new file +96
-0+ // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + ibt: ibt@1e789140 { + compatible = "aspeed,bt-host"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x1c>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + vuart: vuart@1e787000 { + compatible = "aspeed,vuart"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + i2c: i2c@1e78a000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + compatible = "aspeed,ast2400-i2c-controller";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ reg = <0x1e78a000 0x40>; + ranges = <0 0x1e78a000 0x1000>; + interrupts = <12>; + clocks = <&clk_apb>; + clock-ranges; + interrupt-controller; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <0>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <0>; + interrupt-parent = <&i2c>; + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +11
-0+ bus = <1>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <1>; + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xC0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <2>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <2>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c3_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <3>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <3>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c4_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x140 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <4>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <4>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c5_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <5>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <5>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c6_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1C0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <6>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <6>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c7_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <7>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <7>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c8_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x340 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <8>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <8>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c9_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <9>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <9>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c10_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3c0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <10>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <10>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c11_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <11>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <11>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c12_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x440 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <12>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <12>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c13_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <13>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <13>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c14_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-1+ }; + + }; + + }; + }; +}; --2.8.0.rc3.226.g39d4020
Signature · 1 line
*M*axim *S*loyko
Re: [PATCH] aspeed/g5: Device Tree for ast2500
Ping
Quoted 677 lines · Maxim Sloyko
Ping
Quoted 665 lines · On Thu, Sep 29, 2016 at 11:32 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 ++++++++++++++++++++++++++++++ +++++++++++ 3 files changed, 571 insertions(+) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsiarch/arm/dts/Makefile +2
-0@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags herearch/arm/dts/aspeed-g5-evb.dts new file +28
-0@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};arch/arm/dts/aspeed-g5.dtsi new file +2
-0@@ -0,0 +1,541 @@ +/* The device tree is copied from + * https://github.com/openbmc/linux/blob/9ec9d09/arch/arm/boot/
dts/aspeed-g5.dtsi
+ */arch/arm/dts/aspeed-g5.dtsi new file +64
-0+#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + no-hw-checksum; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,g5-scu", "syscon","simple-mfd";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl@1e6e2000 { + compatible = "aspeed,g5-pinctrl"; + + pinctrl_i2c9_default:
i2c9_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i2c10_default:
i2c10_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default:
i2c11_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default:
i2c12_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default:
i2c13_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_gpid0_default:
gpid0_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid1_default:
gpid1_default{arch/arm/dts/aspeed-g5.dtsi new file +10
-0+ function = "GPID1"; + groups = "GPID1"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_i2c5_default:
i2c5_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default:
i2c6_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default:
i2c7_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default:
i2c8_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_pwm0_default:
pwm0_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default:
pwm1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default:
pwm2_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default:
pwm3_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default:
pwm4_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default:
pwm5_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default:
pwm6_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default:
pwm7_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_i2c3_default:
i2c3_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default:
i2c4_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c14_default:
i2c14_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_rgmii1_default:
rgmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rmii1_default:
rmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rgmii2_default:
rgmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii2_default:
rmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +51
-0+ function = "RMII2"; + groups = "RMII2"; + }; + }; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers onlyone
arch/arm/dts/aspeed-g5.dtsi new file +96
-0+ // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + ibt: ibt@1e789140 { + compatible = "aspeed,bt-host"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x1c>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + vuart: vuart@1e787000 { + compatible = "aspeed,vuart"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + i2c: i2c@1e78a000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + compatible ="aspeed,ast2400-i2c-controller";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ reg = <0x1e78a000 0x40>; + ranges = <0 0x1e78a000 0x1000>; + interrupts = <12>; + clocks = <&clk_apb>; + clock-ranges; + interrupt-controller; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <0>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <0>; + interrupt-parent = <&i2c>; + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +11
-0+ bus = <1>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <1>; + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xC0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <2>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <2>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c3_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <3>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <3>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c4_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x140 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <4>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <4>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c5_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <5>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <5>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c6_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1C0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <6>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <6>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c7_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <7>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <7>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c8_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x340 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <8>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <8>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c9_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <9>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <9>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c10_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3c0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <10>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <10>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c11_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <11>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <11>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c12_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x440 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <12>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <12>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c13_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <13>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <13>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c14_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-1+ }; + + }; + + }; + }; +}; --Quoted 3 lines
2.8.0.rc3.226.g39d4020
--
*M*axim *S*loyko
Signature · 1 line
*M*axim *S*loyko
Joel Stanley
maintainerRe: [PATCH] aspeed/g5: Device Tree for ast2500
Hi Maxim.
Quoted 1 line · Maxim Sloyko
Ping
I can see your sense of urgency in getting these reviewed. May I suggest in the future a few tips for making that happen:
You can make sure you address all of the comments from previous reviews. It makes your reviewers feel like you're ignoring them, and they're wasting their time, when you're asked to fix something and subsequent versions do not have the changes made or a discussion as to why you chose not to.
Make sure you address the patches to your intended audience. Cedric and myself have hacked on our u-boot, and I'm sure you have some peers from your project team could help out too. You can put those you want to review in the 'to' field when creating the patch.
You can help out by providing review for other patches on the list. This helps you understand the best practices and code base, which in turn helps you write better patches. It also shows you're here to collaborate and assist instead of only caring about your own tasks.
I look forward to working with you as we clean up u-boot and implement the features that we require!
Cheers,
Joel
Quoted 692 lines · Maxim Sloyko
Quoted 670 lines
Ping
Quoted 666 lines · On Thu, Sep 29, 2016 at 11:32 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 571 insertions(+) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsiarch/arm/dts/Makefile +2
-0@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags herearch/arm/dts/aspeed-g5-evb.dts new file +28
-0@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};arch/arm/dts/aspeed-g5.dtsi new file +2
-0@@ -0,0 +1,541 @@ +/* The device tree is copied from + *https://github.com/openbmc/linux/blob/9ec9d09/arch/arm/boot/dts/aspeed-g5.dtsi
+ */arch/arm/dts/aspeed-g5.dtsi new file +64
-0+#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + no-hw-checksum; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,g5-scu", "syscon","simple-mfd";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl@1e6e2000 { + compatible = "aspeed,g5-pinctrl"; + + pinctrl_i2c9_default:
i2c9_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i2c10_default:
i2c10_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default:
i2c11_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default:
i2c12_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default:
i2c13_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_gpid0_default:
gpid0_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid1_default:
gpid1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "GPID1"; + groups = "GPID1"; + }; + + pinctrl_sd1_default: sd1_default{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "SD1"; + groups = "SD1"; + }; + + pinctrl_i2c5_default:
i2c5_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default:
i2c6_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default:
i2c7_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default:
i2c8_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_pwm0_default:
pwm0_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default:
pwm1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default:
pwm2_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default:
pwm3_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default:
pwm4_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default:
pwm5_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default:
pwm6_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default:
pwm7_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_i2c3_default:
i2c3_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default:
i2c4_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c14_default:
i2c14_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_rgmii1_default:
rgmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rmii1_default:
rmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rgmii2_default:
rgmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii2_default:
rmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +51
-0+ function = "RMII2"; + groups = "RMII2"; + }; + }; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers onlyone
arch/arm/dts/aspeed-g5.dtsi new file +96
-0+ // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + ibt: ibt@1e789140 { + compatible = "aspeed,bt-host"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x1c>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + vuart: vuart@1e787000 { + compatible = "aspeed,vuart"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + i2c: i2c@1e78a000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + compatible ="aspeed,ast2400-i2c-controller";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ reg = <0x1e78a000 0x40>; + ranges = <0 0x1e78a000 0x1000>; + interrupts = <12>; + clocks = <&clk_apb>; + clock-ranges; + interrupt-controller; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <0>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <0>; + interrupt-parent = <&i2c>; + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +11
-0+ bus = <1>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <1>; + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xC0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <2>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <2>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c3_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <3>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <3>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c4_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x140 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <4>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <4>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c5_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <5>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <5>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c6_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1C0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <6>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <6>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c7_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <7>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <7>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c8_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x340 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <8>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <8>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c9_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <9>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <9>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c10_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3c0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <10>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <10>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c11_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <11>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <11>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c12_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x440 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <12>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <12>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c13_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <13>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <13>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c14_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + }; + + }; + }; +};Quoted 8 lines
Quoted 3 lines
--
2.8.0.rc3.226.g39d4020--
Maxim Sloyko--
Maxim Sloyko_______________________________________________
openbmc mailing list
[email protected]
https://lists.ozlabs.org/listinfo/openbmc
Re: [PATCH] aspeed/g5: Device Tree for ast2500
Quoted 5 lines · Joel Stanley
Hi Maxim.
Quoted 1 line · Maxim Sloyko
Ping
Quoted 9 lines
I can see your sense of urgency in getting these reviewed. May I suggest in the future a few tips for making that happen:
You can make sure you address all of the comments from previous reviews. It makes your reviewers feel like you're ignoring them, and they're wasting their time, when you're asked to fix something and subsequent versions do not have the changes made or a discussion as to why you chose not to.
This is your reply from Sep 28 to the patch that contained same exact Device Tree:
---------------- 8 < --------------------- 8 <
------------------------------------
This unrelated to the device tree additions and therefore should be in a separate patch.
The device tree additions look okay.
--------------- 8 < --------------------- 8 < ------------------------------
--------
This is what I replied on Sep 29:
---------------- 8 < --------------------- 8 <
------------------------------------
Quoted 3 lines
This unrelated to the device tree additions and therefore should be in a separate patch.
This is related, because the device tree can't be used without this fix. ---------------- 8 < --------------------- 8 <
------------------------------------
However, later same day I sent the same patch without board file modifications (which is in this thread). Yes, I understand how this might have created some confusion, but I did not see any replies in either that thread or this one. So I sent the same patch again, but of course the device tree on the linux side has changed since the time I originally sent this, so that's no good anymore -- understandably so, it does not make it less frustrating.
Quoted 716 lines
Make sure you address the patches to your intended audience. Cedric and myself have hacked on our u-boot, and I'm sure you have some peers from your project team could help out too. You can put those you want to review in the 'to' field when creating the patch.
You can help out by providing review for other patches on the list. This helps you understand the best practices and code base, which in turn helps you write better patches. It also shows you're here to collaborate and assist instead of only caring about your own tasks.
I look forward to working with you as we clean up u-boot and implement the features that we require!
Cheers,
Joel
Quoted 69 lines · Maxim Sloyko
Quoted 67 lines
Ping
Quoted 63 lines · On Thu, Sep 29, 2016 at 11:32 AM, <[email protected]> wrote:
From: Maxim Sloyko <[email protected]>
Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 +++ arch/arm/dts/aspeed-g5.dtsi | 541 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 571 insertions(+) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsiarch/arm/dts/Makefile +2
-0@@ -233,6 +233,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags herearch/arm/dts/aspeed-g5-evb.dts new file +28
-0@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};arch/arm/dts/aspeed-g5.dtsi +0
-0Quoted 8 lines
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new file mode 100644
index 0000000..eb81a2earch/arm/dts/aspeed-g5.dtsi new file +2
-0@@ -0,0 +1,541 @@ +/* The device tree is copied from + *https://github.com/openbmc/linux/blob/9ec9d09/arch/arm/boot/
dts/aspeed-g5.dtsiQuoted 62 lines
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+ */
arch/arm/dts/aspeed-g5.dtsi new file +61
-0+#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + no-hw-checksum; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + };Quoted 8 lines
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arch/arm/dts/aspeed-g5.dtsi
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arch/arm/dts/aspeed-g5.dtsi new file +3
-0+ + syscon: syscon@1e6e2000 { + compatible = "aspeed,g5-scu", "syscon","simple-mfd";
arch/arm/dts/aspeed-g5.dtsi new file +4
-0+ reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl@1e6e2000 { + compatible ="aspeed,g5-pinctrl";
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arch/arm/dts/aspeed-g5.dtsi new file +2
-0+ + pinctrl_i2c9_default:
i2c9_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i2c10_default:
i2c10_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default:
i2c11_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default:
i2c12_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default:
i2c13_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_gpid0_default:
gpid0_default{arch/arm/dts/aspeed-g5.dtsi new file +3
-0+ function = "GPID0"; + groups = "GPID0"; + };Quoted 8 lines
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arch/arm/dts/aspeed-g5.dtsi
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arch/arm/dts/aspeed-g5.dtsi new file +2
-0+ + pinctrl_gpid1_default:
gpid1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "GPID1"; + groups = "GPID1"; + }; + + pinctrl_sd1_default:
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{
arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "SD1"; + groups = "SD1"; + }; + + pinctrl_i2c5_default:
i2c5_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default:
i2c6_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default:
i2c7_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default:
i2c8_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_pwm0_default:
pwm0_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default:
pwm1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default:
pwm2_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default:
pwm3_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default:
pwm4_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default:
pwm5_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default:
pwm6_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default:
pwm7_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_i2c3_default:
i2c3_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default:
i2c4_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c14_default:
i2c14_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_rgmii1_default:
rgmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rmii1_default:
rmii1_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rgmii2_default:
rgmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +5
-0+ function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii2_default:
rmii2_default{arch/arm/dts/aspeed-g5.dtsi new file +43
-0+ function = "RMII2"; + groups = "RMII2"; + }; + }; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>;Quoted 8 lines
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arch/arm/dts/aspeed-g5.dtsi
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arch/arm/dts/aspeed-g5.dtsi new file +8
-0+ interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registersonly
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one
+ // interrupt and assumes it's fortimer 1
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+ //interrupts = <16 17 18 35 36 37 38
39>;
Quoted 332 lines
Quoted 312 lines
Quoted 312 lines
arch/arm/dts/aspeed-g5.dtsi new file +94
-0+ interrupts = <16>; + clocks = <&clk_apb>; + }; + + ibt: ibt@1e789140 { + compatible = "aspeed,bt-host"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x1c>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + vuart: vuart@1e787000 { + compatible = "aspeed,vuart"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + i2c: i2c@1e78a000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + compatible ="aspeed,ast2400-i2c-controller";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ reg = <0x1e78a000 0x40>; + ranges = <0 0x1e78a000 0x1000>; + interrupts = <12>; + clocks = <&clk_apb>; + clock-ranges; + interrupt-controller; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +12
-0+ bus = <0>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <0>; + interrupt-parent = <&i2c>; + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +11
-0+ bus = <1>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <1>; + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xC0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <2>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <2>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c3_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <3>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <3>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c4_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x140 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <4>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <4>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c5_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <5>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <5>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c6_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1C0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <6>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <6>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c7_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <7>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <7>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c8_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x340 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <8>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <8>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c9_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <9>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <9>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c10_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3c0 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <10>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <10>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c11_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <11>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <11>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c12_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x440 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <12>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <12>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c13_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x40>; + compatible ="aspeed,ast2400-i2c-bus";
arch/arm/dts/aspeed-g5.dtsi new file +6
-0+ bus = <13>; + clock-frequency = <100000>; + status = "disabled"; + interrupts = <13>; + pinctrl-names = "default"; + pinctrl-0 =<
&pinctrl_i2c14_default>;arch/arm/dts/aspeed-g5.dtsi new file +7
-0+ }; + + }; + + }; + }; +};Quoted 8 lines
Quoted 3 lines
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2.8.0.rc3.226.g39d4020--
Maxim Sloyko--
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