ARM: dts: lpc32xx: set pwm1 & pwm2 default clock rate
Subsystems (2)
PATCH 1/1 ARM: dts: lpc32xx: set pwm1 & pwm2 default clock rate
From: Sylvain Lemieux <[email protected]>
Probably most of NXP LPC32xx boards have 13MHz main oscillator and therefore for HCLK PLL and ARM core clock rate default hardware setting of 16 * 13MHz = 208MHz and the AHB bus clock rate of 208MHz / 2 = 104MHz.
The change explicitly defines the peripheral PWM1/PWM2 default clock output rate of 104MHz. If needed it can be redefined in a board DTS file.
---
Note:
* There is a dependency on the following patch:
"ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2"
http://www.spinics.net/lists/arm-kernel/msg530277.html
* This patch should be apply after
"ARM: dts: lpc32xx: add pwm-cells to base dts file"
http://www.spinics.net/lists/arm-kernel/msg534050.html
- There is no dependency between the patches.
arch/arm/boot/dts/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/lpc32xx.dtsi +2 -0
@@ -471,6 +471,7 @@ clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + assigned-clock-rates = <104000000>; status = "disabled"; #pwm-cells = <2>; };
@@ -481,6 +482,7 @@ clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + assigned-clock-rates = <104000000>; status = "disabled"; #pwm-cells = <2>; };
Signature · 1 line
1.8.3.1
Vladimir Zapolskiy
maintainerPATCH 1/1 ARM: dts: lpc32xx: set pwm1 & pwm2 default clock rate
Hi Sylvain,
Quoted 30 lines · Sylvain Lemieux
From: Sylvain Lemieux <[email protected]>
Probably most of NXP LPC32xx boards have 13MHz main oscillator and therefore for HCLK PLL and ARM core clock rate default hardware setting of 16 * 13MHz = 208MHz and the AHB bus clock rate of 208MHz / 2 = 104MHz.
The change explicitly defines the peripheral PWM1/PWM2 default clock output rate of 104MHz. If needed it can be redefined in a board DTS file.
Signed-off-by Sylvain Lemieux <[email protected]>---
Note:
* There is a dependency on the following patch:
"ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2"
http://www.spinics.net/lists/arm-kernel/msg530277.html
* This patch should be apply after
"ARM: dts: lpc32xx: add pwm-cells to base dts file"
http://www.spinics.net/lists/arm-kernel/msg534050.html
- There is no dependency between the patches.arch/arm/boot/dts/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+)arch/arm/boot/dts/lpc32xx.dtsi +0
-0
arch/arm/boot/dts/lpc32xx.dtsi line 474
Quoted 4 lines
arch/arm/boot/dts/lpc32xx.dtsi +1
-0@@ -471,6 +471,7 @@ clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + assigned-clock-rates = <104000000>;
PWM controller clock source can be 32KHz or CLK_PERIPH, the latter is equal either to SYSCLK or HCLK PLL divided by HCLKDIV_CTRL[6:2].
Do you set the divider to 1? If yes, then I would say
1) this is very specific to your board, generally CLK_PERIPH
is set to be about 10-13MHz,
2) HCLKDIV or PERIPH clock configuration shall not be done in pwm device node.
104MHz is too high value to be set by default for PWM clock.
arch/arm/boot/dts/lpc32xx.dtsi line 488
Quoted 12 lines
arch/arm/boot/dts/lpc32xx.dtsi +1
-0status = "disabled"; #pwm-cells = <2>; };@@ -481,6 +482,7 @@ clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + assigned-clock-rates = <104000000>; status = "disabled"; #pwm-cells = <2>; };
--
With best wishes,
Vladimir
PATCH 1/1 ARM: dts: lpc32xx: set pwm1 & pwm2 default clock rate
Hi Vladimir,
Quoted 41 lines · Vladimir Zapolskiy
Hi Sylvain,
Quoted 30 lines · Sylvain Lemieux
From: Sylvain Lemieux <[email protected]>
Probably most of NXP LPC32xx boards have 13MHz main oscillator and therefore for HCLK PLL and ARM core clock rate default hardware setting of 16 * 13MHz = 208MHz and the AHB bus clock rate of 208MHz / 2 = 104MHz.
The change explicitly defines the peripheral PWM1/PWM2 default clock output rate of 104MHz. If needed it can be redefined in a board DTS file.
Signed-off-by Sylvain Lemieux <[email protected]>---
Note:
* There is a dependency on the following patch:
"ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2"
http://www.spinics.net/lists/arm-kernel/msg530277.html
* This patch should be apply after
"ARM: dts: lpc32xx: add pwm-cells to base dts file"
http://www.spinics.net/lists/arm-kernel/msg534050.html
- There is no dependency between the patches.arch/arm/boot/dts/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+)arch/arm/boot/dts/lpc32xx.dtsi +0
-0arch/arm/boot/dts/lpc32xx.dtsi line 474
Quoted 4 lines
arch/arm/boot/dts/lpc32xx.dtsi +1
-0@@ -471,6 +471,7 @@ clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + assigned-clock-rates = <104000000>;PWM controller clock source can be 32KHz or
CLK_PERIPH, the latter is equal either to SYSCLK or HCLK PLL divided by HCLKDIV_CTRL[6:2].
Quoted 8 lines
Do you set the divider to 1? If yes, then I would say
1) this is very specific to your board, generally
CLK_PERIPH
is set to be about 10-13MHz,
2) HCLKDIV or PERIPH clock configuration shall not be done in pwm device node.104MHz is too high value to be set by default for PWM clock.
This is a good catch; it was an error on my side. The purpose of the patch was to setup the output of the PWM clock to the default CLK_PERIPH value (13325000).
This change does not modify the HCLKDIV or the PERIPH clock.
I can submit a version 2 with the proper value and update the patch description to list the default peripheral clock setup of 13MHz.
This change is adding a default value for the PWM clock (setup to CLK_PERIPH) to the PWM device node, allowing the board specific DTS to only enable the PWM to get it work.
If the PWM clock output is not setup with a default value, only enabling the PWM in the board specific DTS file is not enough; the PWM divider will keep the default value of zero (i.e. PWM clock off).
Quoted 3 lines
--
With best wishes,
Vladimir
Sylvain
PATCH 1/1 ARM: dts: lpc32xx: set pwm1 & pwm2 default clock rate
Quoted 19 lines · Sylvain Lemieux
Hi Vladimir,
Quoted 16 lines · Vladimir Zapolskiy
Hi Sylvain,
Quoted 13 lines · Sylvain Lemieux
From: Sylvain Lemieux <[email protected]>
Probably most of NXP LPC32xx boards have 13MHz main oscillator and therefore for HCLK PLL and ARM core clock rate default hardware setting of 16 * 13MHz = 208MHz and the AHB bus clock rate of 208MHz / 2 = 104MHz.
The change explicitly defines the peripheral PWM1/PWM2 default clock output rate of 104MHz. If needed it can be redefined in a board DTS file.
Signed-off-by Sylvain Lemieux <[email protected]>---
[...]
Quoted 5 lines
I can submit a version 2 with the proper value and update the patch description to list the default peripheral clock setup of 13MHz.
Quoted 9 lines
This change is adding a default value for the PWM clock (setup to
CLK_PERIPH) to the PWM device node, allowing the board specific DTS to only enable the PWM to get it work.If the PWM clock output is not setup with a default value, only enabling the PWM in the board specific DTS file is not enough; the PWM divider will keep the default value of zero (i.e. PWM clock off).
This patch is no longer needed;
the following patch is handle the issue:
http://www.spinics.net/lists/arm-kernel/msg535313.html
The PWM clock will match the parent clock (i.e. update at initialization) if the PWM divider value was setup to 0 (i.e. gating functionality).
Quoted 7 lines
Quoted 3 lines
--
With best wishes,
VladimirSylvain