Patch "drm/i915: introduce intel_has_sagv()" has been added to the 4.8-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
drm/i915: introduce intel_has_sagv()
to the 4.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-introduce-intel_has_sagv.patch
and it can be found in the queue-4.8 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
6e7fdb873d6255ca3c999dd5c6c18962a769ed3eMon Sep 17 00:00:00 2001
From: Paulo Zanoni <[email protected]>
Date: Thu, 22 Sep 2016 18:00:28 -0300
Subject: drm/i915: introduce intel_has_sagv()
From: Paulo Zanoni <[email protected]>
commit 6e7fdb873d6255ca3c999dd5c6c18962a769ed3e upstream.
And use it to move knowledge about the SAGV-supporting platforms from the callers to the SAGV code.
We'll add more platforms to intel_has_sagv(), so IMHO it makes more sense to move all this to a single function instead of patching all the callers every time we add SAGV support to a new platform.
v2: Move I915_SAGV_NOT_CONTROLLED to the new function (Lyude).
--- drivers/gpu/drm/i915/intel_display.c | 5 ++--- drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++---- 2 files changed, 20 insertions(+), 7 deletions(-)
drivers/gpu/drm/i915/intel_display.c +2 -3
@@ -13891,7 +13891,7 @@ static void intel_atomic_commit_tail(str* SKL workaround: bspec recommends we disable the SAGV when we * have more then one pipe enabled */ -if (IS_SKYLAKE (dev_priv) && !intel_can_enable_sagv (state)) +if (!intel_can_enable_sagv (state))intel_disable_sagv (dev_priv);intel_modeset_verify_disabled (dev);
@@ -13949,8 +13949,7 @@ static void intel_atomic_commit_tail(strintel_modeset_verify_crtc (crtc, old_crtc_state, crtc->state); } -if (IS_SKYLAKE (dev_priv) && intel_state->modeset && -intel_can_enable_sagv (state)) +if (intel_state->modeset &&intel_can_enable_sagv (state))intel_enable_sagv (dev_priv);drm_atomic_helper_commit_hw_done (state);
drivers/gpu/drm/i915/intel_pm.c +18 -4
@@ -2878,6 +2878,13 @@ skl_wm_plane_id(const struct intel_plane } } +static bool +intel_has_sagv (struct drm_i915_private *dev_priv) +{ +return IS_SKYLAKE (dev_priv) && + dev_priv->sagv_status !=I915_SAGV_NOT_CONTROLLED ; +} +/* * SAGV dynamically adjusts the system agent voltage and clock frequencies * depending on power and performance requirements. The display engine access
@@ -2894,8 +2901,10 @@ intel_enable_sagv(struct drm_i915_privat {int ret; -if (dev_priv->sagv_status ==I915_SAGV_NOT_CONTROLLED || - dev_priv->sagv_status ==I915_SAGV_ENABLED ) +if (!intel_has_sagv (dev_priv)) +return 0 ; + +if (dev_priv->sagv_status ==I915_SAGV_ENABLED )return 0 ;DRM_DEBUG_KMS ("Enabling the SAGV\n" );
@@ -2943,8 +2952,10 @@ intel_disable_sagv(struct drm_i915_priva {int ret, result; -if (dev_priv->sagv_status ==I915_SAGV_NOT_CONTROLLED || - dev_priv->sagv_status ==I915_SAGV_DISABLED ) +if (!intel_has_sagv (dev_priv)) +return 0 ; + +if (dev_priv->sagv_status ==I915_SAGV_DISABLED )return 0 ;DRM_DEBUG_KMS ("Disabling the SAGV\n" );
@@ -2985,6 +2996,9 @@ bool intel_can_enable_sagv(struct drm_atenum pipe pipe;int level, plane; +if (!intel_has_sagv (dev_priv)) +return false; +/* * SKL workaround: bspec recommends we disable the SAGV when we have * more then one pipe enabled
Patches currently in stable-queue which might be from [email protected] are
queue-4.8/drm-i915-gen9-fix-the-watermark-res_blocks-value.patch queue-4.8/drm-i915-gen9-only-add-the-planes-actually-affected-by-ddb-changes.patch queue-4.8/drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch queue-4.8/drm-i915-introduce-intel_has_sagv.patch queue-4.8/drm-i915-gen9-fix-plane_blocks_per_line-on-watermarks-calculations.patch queue-4.8/drm-i915-kbl-kbl-also-needs-to-run-the-sagv-code.patch queue-4.8/drm-i915-gen9-minimum-scanlines-for-y-tile-is-not-always-4.patch queue-4.8/drm-i915-sagv-is-not-skl-only-so-rename-a-few-things.patch