FAILED: patch "[PATCH] drm/amdgpu/si_dpm: workaround for SI kickers" failed to apply to 4.8-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 4.8-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
Quoted 1 line
From
71451bdfc2f7bc67cf0b7a5d51bc1489aaa55701Mon Sep 17 00:00:00 2001
From: Alex Deucher <[email protected]>
Date: Wed, 26 Oct 2016 15:27:45 -0400
Subject: [PATCH] drm/amdgpu/si_dpm: workaround for SI kickers
Consolidate existing quirks. Fixes stability issues on some kickers.
Acked-by Huang Rui <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
drivers/gpu/drm/amd/amdgpu/si_dpm.c +43 -16
@@ -3477,6 +3477,49 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,int i;struct si_dpm_quirk *p = si_dpm_quirk_list; +/* limit all SI kickers */ +if (adev->asic_type ==CHIP_PITCAIRN ) { +if ((adev->pdev->revision ==0x81 ) || + (adev->pdev->device ==0x6810 ) || + (adev->pdev->device ==0x6811 ) || + (adev->pdev->device ==0x6816 ) || + (adev->pdev->device ==0x6817 ) || + (adev->pdev->device ==0x6806 )) + max_mclk =120000 ; + }else if (adev->asic_type ==CHIP_VERDE ) { +if ((adev->pdev->revision ==0x81 ) || + (adev->pdev->revision ==0x83 ) || + (adev->pdev->revision ==0x87 ) || + (adev->pdev->device ==0x6820 ) || + (adev->pdev->device ==0x6821 ) || + (adev->pdev->device ==0x6822 ) || + (adev->pdev->device ==0x6823 ) || + (adev->pdev->device ==0x682A ) || + (adev->pdev->device ==0x682B )) { + max_sclk =75000 ; + max_mclk =80000 ; + } + }else if (adev->asic_type ==CHIP_OLAND ) { +if ((adev->pdev->revision ==0xC7 ) || + (adev->pdev->revision ==0x80 ) || + (adev->pdev->revision ==0x81 ) || + (adev->pdev->revision ==0x83 ) || + (adev->pdev->device ==0x6604 ) || + (adev->pdev->device ==0x6605 )) { + max_sclk =75000 ; + max_mclk =80000 ; + } + }else if (adev->asic_type ==CHIP_HAINAN ) { +if ((adev->pdev->revision ==0x81 ) || + (adev->pdev->revision ==0x83 ) || + (adev->pdev->revision ==0xC3 ) || + (adev->pdev->device ==0x6664 ) || + (adev->pdev->device ==0x6665 ) || + (adev->pdev->device ==0x6667 )) { + max_sclk =75000 ; + max_mclk =80000 ; + } + }/* Apply dpm quirks */ while (p && p->chip_device !=0 ) { if (adev->pdev->vendor == p->chip_vendor &&
@@ -3489,22 +3532,6 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, } ++p; } -/* limit mclk on all R7 370 parts for stability */ -if (adev->pdev->device ==0x6811 && - adev->pdev->revision ==0x81 ) - max_mclk =120000 ; -/* limit sclk/mclk on Jet parts for stability */ -if (adev->pdev->device ==0x6665 && - adev->pdev->revision ==0xc3 ) { - max_sclk =75000 ; - max_mclk =80000 ; - } -/* Limit clocks for some HD8600 parts */ -if (adev->pdev->device ==0x6660 && - adev->pdev->revision ==0x83 ) { - max_sclk =75000 ; - max_mclk =80000 ; - }if (rps->vce_active) { rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;