openrisc: Misc fixes from backlog

Acked-by Jonas Bonn <[email protected]>

---
 arch/openrisc/include/asm/pgtable.h | 2 +-
 arch/openrisc/mm/init.c             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

arch/openrisc/include/asm/pgtable.h +1 -1

index 69c7df0..3567aa7 100644
@@ -69,7 +69,7 @@ extern void paging_init(void);
  */
 #define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-2))
 
-#define PTRS_PER_PGD	(1UL << (PAGE_SHIFT-2))
+#define PTRS_PER_PGD	(1UL << (32-PGDIR_SHIFT))
 
 /* calculate how many PGD entries a user-level program can use
  * the first mappable virtual address is 0

arch/openrisc/mm/init.c +1 -1

index 7f94652..b782ce9 100644
@@ -110,7 +110,7 @@ static void __init map_ram(void)
 			set_pmd(pme, __pmd(_KERNPG_TABLE + __pa(pte)));
 
 			/* Fill the newly allocated page with PTE'S */
-			for (j = 0; p < e && j < PTRS_PER_PGD;
+			for (j = 0; p < e && j < PTRS_PER_PTE;
 			     v += PAGE_SIZE, p += PAGE_SIZE, j++, pte++) {
 				if (v >= (u32) _e_kernel_ro ||
 				    v < (u32) _s_kernel_ro)

Signature · 1 line

2.7.4

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #2 lore raw

PATCH v2 2/9 openrisc: restore all regs on rt_sigreturn

From: Jonas Bonn <[email protected]>

Fix signal handling for when signals are handled as the result of timers or exceptions, previous code assumed syscalls. This was noticeable with X crashing where it uses SIGALRM.

This patch restores all regs before returning to userspace via _resume_userspace instead of via syscall return path.

The rt_sigreturn syscall is more like a context switch than a function call; it entails a return from one context (the signal handler) to another (the process in question). For a context switch like this there are effectively no call-saved regs that remain constant across the transition.

Reported-by Sebastian Macke <[email protected]>

Signed-off-by Jonas Bonn <[email protected]>

[shorne at gmail.com: Updated comment better reflect change and issue]

---
 arch/openrisc/kernel/entry.S | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

arch/openrisc/kernel/entry.S +9 -1

index fec8bf9..572d223 100644
@@ -1101,8 +1101,16 @@ ENTRY(__sys_fork)
 	 l.addi	r3,r1,0
 
 ENTRY(sys_rt_sigreturn)
-	l.j	_sys_rt_sigreturn
+	l.jal	_sys_rt_sigreturn
 	 l.addi	r3,r1,0
+	l.sfne	r30,r0
+	l.bnf	_no_syscall_trace
+	 l.nop
+	l.jal	do_syscall_trace_leave
+	 l.addi	r3,r1,0
+_no_syscall_trace:
+	l.j	_resume_userspace
+	 l.nop
 
 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
  * The functions takes a variable number of parameters depending on which

Signature · 1 line

2.7.4

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #3 lore raw

PATCH v2 3/9 openrisc: Add thread-local storage (TLS) support

From: Christian Svensson <[email protected]>

Historically OpenRISC GCC has reserved r10 which we now use to hold the thread pointer for thread-local storage (TLS).

Signed-off-by Christian Svensson <[email protected]>

Signed-off-by Stefan Kristiansson <[email protected]>

---
 arch/openrisc/kernel/process.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/openrisc/kernel/process.c +13 -0

index 7095dfe..277123b 100644
@@ -173,6 +173,19 @@ copy_thread(unsigned long clone_flags, unsigned long usp,
 
 		if (usp)
 			userregs->sp = usp;
+
+		/*
+		 * For CLONE_SETTLS set "tp" (r10) to the TLS pointer passed to sys_clone.
+		 *
+		 * The kernel entry is:
+		 *	int clone (long flags, void *child_stack, int *parent_tid,
+		 *		int *child_tid, struct void *tls)
+		 *
+		 * This makes the source r7 in the kernel registers.
+		 */
+		if (clone_flags & CLONE_SETTLS)
+			userregs->gpr[10] = userregs->gpr[7];
+
 		userregs->gpr[11] = 0;	/* Result from fork() */
 
 		kregs->gpr[20] = 0;	/* Userspace thread */

Signature · 1 line

2.7.4

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #4 lore raw

PATCH v2 4/9 openrisc: Support both old (or32) and new (or1k) toolchain

From: Guenter Roeck <[email protected]>

The output file format for or1k has changed from "elf32-or32" to "elf32-or1k". Select the correct output format automatically to be able to compile the kernel with both toolchain variants.

Signed-off-by Guenter Roeck <[email protected]>

---
 arch/openrisc/kernel/vmlinux.lds.S | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

arch/openrisc/kernel/vmlinux.lds.S +7 -1

index d68b9ed..ef31fc2 100644
@@ -30,7 +30,13 @@
 #include <asm/cache.h>
 #include <asm-generic/vmlinux.lds.h>
 
-OUTPUT_FORMAT("elf32-or32", "elf32-or32", "elf32-or32")
+#ifdef __OR1K__
+#define __OUTPUT_FORMAT        "elf32-or1k"
+#else
+#define __OUTPUT_FORMAT        "elf32-or32"
+#endif
+
+OUTPUT_FORMAT(__OUTPUT_FORMAT, __OUTPUT_FORMAT, __OUTPUT_FORMAT)
 jiffies = jiffies_64 + 4;
 
 SECTIONS

Signature · 1 line

2.7.4

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #5 lore raw

PATCH v2 5/9 openrisc: add NR_CPUS Kconfig default value

The build system now expects that NR_CPUS is defined.

Follow 4cbbbb4 ("microblaze: Fix missing NR_CPUS in menuconfig")

---
 arch/openrisc/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

arch/openrisc/Kconfig +3 -0

index 489e7f9..691e1af 100644
@@ -98,6 +98,9 @@ config OPENRISC_HAVE_INST_DIV
 	  Select this if your implementation has a hardware divide instruction
 endmenu
 
+config NR_CPUS
+	int
+	default "1"
 
 source kernel/Kconfig.hz
 source kernel/Kconfig.preempt

Signature · 1 line

2.7.4

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #6 lore raw

PATCH v2 6/9 openrisc: remove the redundant of_platform_populate

From: Rob Herring <[email protected]>

The of_platform_populate call in the openrisc arch code is now redundant as the DT core provides a default call. Openrisc has a NULL match table which means only top level nodes with compatible strings will have devices creates. The default version will also descend nodes in the match table such as "simple-bus" which should be fine as openrisc doesn't have any of these (though it is preferred that memory-mapped peripherals be grouped under a bus node(s)).

Signed-off-by Rob Herring <[email protected]>

Cc Jonas Bonn <[email protected]>

---
 arch/openrisc/kernel/setup.c | 10 ----------
 1 file changed, 10 deletions(-)

arch/openrisc/kernel/setup.c +0 ~~-10~~

index b4ed8b3..d2f78cf 100644
@@ -38,7 +38,6 @@
 #include <linux/of.h>
 #include <linux/memblock.h>
 #include <linux/device.h>
-#include <linux/of_platform.h>
 
 #include <asm/sections.h>
 #include <asm/segment.h>

@@ -219,15 +218,6 @@ void __init or32_early_setup(void *fdt)
 	early_init_devtree(fdt);
 }
 
-static int __init openrisc_device_probe(void)
-{
-	of_platform_populate(NULL, NULL, NULL, NULL);
-
-	return 0;
-}
-
-device_initcall(openrisc_device_probe);
-
 static inline unsigned long extract_value_bits(unsigned long reg,
 					       short bit_nr, short width)
 {

Signature · 1 line

2.7.4

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #7 lore raw

PATCH v2 7/9 openrisc: Consolidate setup to use memblock instead of bootmem

Clearing out one todo item. Use the memblock boot time memory which is the current standard.

Acked-by Jonas <[email protected]>

---
 arch/openrisc/Kconfig               |  1 +
 arch/openrisc/TODO.openrisc         |  3 ---
 arch/openrisc/include/asm/pgalloc.h |  1 -
 arch/openrisc/kernel/setup.c        | 36 ++++++++++++------------------------
 arch/openrisc/mm/init.c             |  2 +-
 arch/openrisc/mm/ioremap.c          |  4 ----
 6 files changed, 14 insertions(+), 33 deletions(-)

arch/openrisc/Kconfig +1 -0

index 691e1af..8d22015 100644
@@ -26,6 +26,7 @@ config OPENRISC
 	select HAVE_DEBUG_STACKOVERFLOW
 	select OR1K_PIC
 	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
+	select NO_BOOTMEM
 
 config MMU
 	def_bool y

arch/openrisc/TODO.openrisc +0 -3

index acfeef9..0eb04c8 100644
@@ -5,9 +5,6 @@ that are due for investigation shortly, i.e. our TODO list:
 
 -- Implement the rest of the DMA API... dma_map_sg, etc.
 
--- Consolidate usage of memblock and bootmem... move everything over to
-   memblock.
-
 -- Finish the renaming cleanup... there are references to or32 in the code
    which was an older name for the architecture.  The name we've settled on is
    or1k and this change is slowly trickling through the stack.  For the time

arch/openrisc/include/asm/pgalloc.h +0 -1

index 87eebd1..3e1a466 100644
@@ -23,7 +23,6 @@
 #include <linux/threads.h>
 #include <linux/mm.h>
 #include <linux/memblock.h>
-#include <linux/bootmem.h>
 
 extern int mem_init_done;

arch/openrisc/kernel/setup.c +12 ~~-24~~

index d2f78cf..6329d7a 100644
@@ -50,18 +50,16 @@
 
 #include "vmlinux.h"
 
-static unsigned long __init setup_memory(void)
+static void __init setup_memory(void)
 {
-	unsigned long bootmap_size;
 	unsigned long ram_start_pfn;
-	unsigned long free_ram_start_pfn;
 	unsigned long ram_end_pfn;
 	phys_addr_t memory_start, memory_end;
 	struct memblock_region *region;
 
 	memory_end = memory_start = 0;
 
-	/* Find main memory where is the kernel */
+	/* Find main memory where is the kernel, we assume its the only one */
 	for_each_memblock(memory, region) {
 		memory_start = region->base;
 		memory_end = region->base + region->size;

@@ -74,10 +72,11 @@ static unsigned long __init setup_memory(void)
 	}
 
 	ram_start_pfn = PFN_UP(memory_start);
-	/* free_ram_start_pfn is first page after kernel */
-	free_ram_start_pfn = PFN_UP(__pa(_end));
 	ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
 
+	/* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
+	min_low_pfn = ram_start_pfn;
+	max_low_pfn = ram_end_pfn;
 	max_pfn = ram_end_pfn;
 
 	/*

@@ -85,22 +84,13 @@ static unsigned long __init setup_memory(void)
 	 *
 	 * This makes the memory from the end of the kernel to the end of
 	 * RAM usable.
-	 * init_bootmem sets the global values min_low_pfn, max_low_pfn.
 	 */
-	bootmap_size = init_bootmem(free_ram_start_pfn,
-				    ram_end_pfn - ram_start_pfn);
-	free_bootmem(PFN_PHYS(free_ram_start_pfn),
-		     (ram_end_pfn - free_ram_start_pfn) << PAGE_SHIFT);
-	reserve_bootmem(PFN_PHYS(free_ram_start_pfn), bootmap_size,
-			BOOTMEM_DEFAULT);
-
-	for_each_memblock(reserved, region) {
-		printk(KERN_INFO "Reserved - 0x%08x-0x%08x\n",
-		       (u32) region->base, (u32) region->size);
-		reserve_bootmem(region->base, region->size, BOOTMEM_DEFAULT);
-	}
+	memblock_reserve(__pa(_stext), _end - _stext);
+
+	early_init_fdt_reserve_self();
+	early_init_fdt_scan_reserved_mem();
 
-	return ram_end_pfn;
+	memblock_dump_all();
 }
 
 struct cpuinfo cpuinfo;

@@ -272,8 +262,6 @@ void calibrate_delay(void)
 
 void __init setup_arch(char **cmdline_p)
 {
-	unsigned long max_low_pfn;
-
 	unflatten_and_copy_device_tree();
 
 	setup_cpuinfo();

@@ -294,8 +282,8 @@ void __init setup_arch(char **cmdline_p)
 	initrd_below_start_ok = 1;
 #endif
 
-	/* setup bootmem allocator */
-	max_low_pfn = setup_memory();
+	/* setup memblock allocator */
+	setup_memory();
 
 	/* paging_init() sets up the MMU and marks all pages as reserved */
 	paging_init();

arch/openrisc/mm/init.c +1 -1

index b782ce9..f67d82b 100644
@@ -106,7 +106,7 @@ static void __init map_ram(void)
 			}
 
 			/* Alloc one page for holding PTE's... */
-			pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
+			pte = (pte_t *) __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
 			set_pmd(pme, __pmd(_KERNPG_TABLE + __pa(pte)));
 
 			/* Fill the newly allocated page with PTE'S */

arch/openrisc/mm/ioremap.c +0 -4

index fa60b81..8705a46 100644
@@ -124,11 +124,7 @@ pte_t __ref *pte_alloc_one_kernel(struct mm_struct *mm,
 	if (likely(mem_init_done)) {
 		pte = (pte_t *) __get_free_page(GFP_KERNEL);
 	} else {
-		pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
-#if 0
-		/* FIXME: use memblock... */
 		pte = (pte_t *) __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
-#endif
 	}
 
 	if (pte)

Signature · 1 line

2.7.4

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #8 lore raw

PATCH v2 8/9 openrisc: Updates after openrisc.net has been lost

The openrisc.net domain expired and was taken over by squatters. These updates point documentation to the new domain, mailing lists and git repos.

Also, Jonas is not the main maintainer anylonger, he reviews changes but does not maintain a repo or sent pull requests. Updating this to add Stafford and Stefan who are the active maintainers.

---
 MAINTAINERS                   | 6 ++++--
 arch/openrisc/README.openrisc | 8 ++++----
 arch/openrisc/kernel/setup.c  | 2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)

MAINTAINERS +4 -2

index 851b89b..d84a585 100644
@@ -8958,9 +8958,11 @@ F:	drivers/of/resolver.c
 
 OPENRISC ARCHITECTURE
 M:	Jonas Bonn <[email protected]>
-W:	http://openrisc.net
+M:	Stefan Kristiansson <[email protected]>
+M:	Stafford Horne <[email protected]>
+L:	openrisc at lists.librecores.org
+W:	http://openrisc.io
 S:	Maintained
-T:	git git://openrisc.net/~jonas/linux
 F:	arch/openrisc/
 
 OPENVSWITCH

arch/openrisc/README.openrisc +4 -4

index c9f7edf..072069a 100644
@@ -6,7 +6,7 @@ target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
 
 For information about OpenRISC processors and ongoing development:
 
-	website		http://openrisc.net
+	website		http://openrisc.io
 
 For more information about Linux on OpenRISC, please contact South Pole AB.

@@ -24,17 +24,17 @@ In order to build and run Linux for OpenRISC, you'll need at least a basic
 toolchain and, perhaps, the architectural simulator.  Steps to get these bits
 in place are outlined here.
 
-1)  The toolchain can be obtained from openrisc.net.  Instructions for building
+1)  The toolchain can be obtained from openrisc.io.  Instructions for building
 a toolchain can be found at:
 
-http://openrisc.net/toolchain-build.html
+https://github.com/openrisc/tutorials
 
 2) or1ksim (optional)
 
 or1ksim is the architectural simulator which will allow you to actually run
 your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
 
-	git clone git://openrisc.net/jonas/or1ksim-svn
+	git clone https://github.com/openrisc/or1ksim.git
 
 	cd or1ksim
 	./configure --prefix=$OPENRISC_PREFIX

arch/openrisc/kernel/setup.c +1 -1

index 6329d7a..cb797a3 100644
@@ -295,7 +295,7 @@ void __init setup_arch(char **cmdline_p)
 
 	*cmdline_p = boot_command_line;
 
-	printk(KERN_INFO "OpenRISC Linux -- http://openrisc.net\n");
+	printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
 }
 
 static int show_cpuinfo(struct seq_file *m, void *v)

Signature · 1 line

2.7.4

Olof Kindgren

Acked-by on v2 8/9

2016-11-16 07:13 UTC #9 lore raw

Re: [OpenRISC] [PATCH v2 8/9] openrisc: Updates after openrisc.net has been lost

Quoted 83 lines · Stafford Horne

The openrisc.net domain expired and was taken over by squatters. These updates point documentation to the new domain, mailing lists and git repos.

Also, Jonas is not the main maintainer anylonger, he reviews changes but does not maintain a repo or sent pull requests. Updating this to add Stafford and Stefan who are the active maintainers.

---
 MAINTAINERS                   | 6 ++++--
 arch/openrisc/README.openrisc | 8 ++++----
 arch/openrisc/kernel/setup.c  | 2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)

MAINTAINERS +4 -2

index 851b89b..d84a585 100644
@@ -8958,9 +8958,11 @@ F:       drivers/of/resolver.c
 
 OPENRISC ARCHITECTURE
 M:     Jonas Bonn <[email protected]>
-W:     http://openrisc.net
+M:     Stefan Kristiansson <[email protected]>
+M:     Stafford Horne <[email protected]>
+L:     openrisc at lists.librecores.org
+W:     http://openrisc.io
 S:     Maintained
-T:     git git://openrisc.net/~jonas/linux
 F:     arch/openrisc/
 
 OPENVSWITCH

arch/openrisc/README.openrisc +4 -4

index c9f7edf..072069a 100644
@@ -6,7 +6,7 @@ target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
 
 For information about OpenRISC processors and ongoing development:
 
-       website         http://openrisc.net
+       website         http://openrisc.io
 
 For more information about Linux on OpenRISC, please contact South Pole AB.

@@ -24,17 +24,17 @@ In order to build and run Linux for OpenRISC, you'll need at least a basic
 toolchain and, perhaps, the architectural simulator.  Steps to get these bits
 in place are outlined here.
 
-1)  The toolchain can be obtained from openrisc.net.  Instructions for building
+1)  The toolchain can be obtained from openrisc.io.  Instructions for building
 a toolchain can be found at:
 
-http://openrisc.net/toolchain-build.html
+https://github.com/openrisc/tutorials
 
 2) or1ksim (optional)
 
 or1ksim is the architectural simulator which will allow you to actually run
 your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
 
-       git clone git://openrisc.net/jonas/or1ksim-svn
+       git clone https://github.com/openrisc/or1ksim.git
 
        cd or1ksim
        ./configure --prefix=$OPENRISC_PREFIX

arch/openrisc/kernel/setup.c +1 -2

index 6329d7a..cb797a3 100644
@@ -295,7 +295,7 @@ void __init setup_arch(char **cmdline_p)
 
        *cmdline_p = boot_command_line;
 
-       printk(KERN_INFO "OpenRISC Linux -- http://openrisc.net\n");
+       printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
 }
 
 static int show_cpuinfo(struct seq_file *m, void *v)
--

2.7.4

Quoted 4 lines

_______________________________________________
OpenRISC mailing list
OpenRISC at lists.librecores.org
https://lists.librecores.org/listinfo/openrisc

This looks all correct

Acked-by Olof Kindgren <[email protected]>

Geert Uytterhoeven

2016-12-14 08:57 UTC #10 lore raw

Re: [PATCH v2 8/9] openrisc: Updates after openrisc.net has been lost

Hi Stafford, Stefan,

Quoted 21 lines · Stafford Horne

The openrisc.net domain expired and was taken over by squatters. These updates point documentation to the new domain, mailing lists and git repos.
Also, Jonas is not the main maintainer anylonger, he reviews changes but does not maintain a repo or sent pull requests. Updating this to add Stafford and Stefan who are the active maintainers.
Signed-off-by Stafford Horne <[email protected]>
---
 MAINTAINERS                   | 6 ++++--
 arch/openrisc/README.openrisc | 8 ++++----
 arch/openrisc/kernel/setup.c  | 2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)
MAINTAINERS +0 -0
index 851b89b..d84a585 100644
@@ -8958,9 +8958,11 @@ F:       drivers/of/resolver.c
 

MAINTAINERS F: drivers/of/resolver.c · line 8966

Quoted 10 lines

MAINTAINERS +4 -2

 OPENRISC ARCHITECTURE
 M:     Jonas Bonn <[email protected]>
-W:     http://openrisc.net
+M:     Stefan Kristiansson <[email protected]>
+M:     Stafford Horne <[email protected]>
+L:     openrisc at lists.librecores.org
+W:     http://openrisc.io
 S:     Maintained
-T:     git git://openrisc.net/~jonas/linux
 F:     arch/openrisc/

It's great news to see new active maintainers for OpenRISC. Thanks a lot!

Somehow I seem to have missed the new mailing announcement. Subscribed ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Stafford Horne

author maintainer

2016-12-14 11:44 UTC #11 lore raw

Re: [PATCH v2 8/9] openrisc: Updates after openrisc.net has been lost

Hi Geert,

Quoted 38 lines · Geert Uytterhoeven

Hi Stafford, Stefan,
Quoted 21 lines · Stafford Horne
The openrisc.net domain expired and was taken over by squatters. These updates point documentation to the new domain, mailing lists and git repos.
Also, Jonas is not the main maintainer anylonger, he reviews changes but does not maintain a repo or sent pull requests. Updating this to add Stafford and Stefan who are the active maintainers.
Signed-off-by Stafford Horne <[email protected]>
---
 MAINTAINERS                   | 6 ++++--
 arch/openrisc/README.openrisc | 8 ++++----
 arch/openrisc/kernel/setup.c  | 2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)
MAINTAINERS +0 -0
index 851b89b..d84a585 100644
@@ -8958,9 +8958,11 @@ F:       drivers/of/resolver.c
 
MAINTAINERS F: drivers/of/resolver.c · line 8966
Quoted 10 lines
MAINTAINERS +4 -2
 OPENRISC ARCHITECTURE
 M:     Jonas Bonn <[email protected]>
-W:     http://openrisc.net
+M:     Stefan Kristiansson <[email protected]>
+M:     Stafford Horne <[email protected]>
+L:     openrisc at lists.librecores.org
+W:     http://openrisc.io
 S:     Maintained
-T:     git git://openrisc.net/~jonas/linux
 F:     arch/openrisc/
It's great news to see new active maintainers for OpenRISC. Thanks a lot!

Quoted 2 lines

Somehow I seem to have missed the new mailing announcement. Subscribed ;-)

I hope we can help out as much as possible. Let us know if you have any requests.

Just to give a bit of a preview of what we have in our backlog:
- Openrisc optimized memcpy memset routines
- Various opencores (now librecores?) IP drivers
- SMP support

I have been sorting through the patches and getting them ready (commit messages, code style etc). Everything will be reviewed on the openrisc and kernel list.

We cant promise quick progress but hopefully better than it has been in the recent past.

-Stafford

Stafford Horne

author maintainer

2016-11-14 13:30 UTC #12 lore raw

PATCH v2 9/9 openrisc: include l.swa in check for write data pagefault

From: Stefan Kristiansson <[email protected]>

During page fault handling we check the last instruction to understand if the fault was for a read or for a write. By default we fall back to read. New instructions were added to the openrisc 1.1 spec for an atomic load/store pair (l.lwa/l.swa).

This patch adds the opcode for l.swa (0x33) allowing it to be treated as a write operation.

Signed-off-by Stefan Kristiansson <[email protected]>

[shorne at gmail.com: expanded a bit on the comment]

---
 arch/openrisc/kernel/entry.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/openrisc/kernel/entry.S +1 -1

index 572d223..aac0bde 100644
@@ -264,7 +264,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
 	l.srli  r6,r6,26                   // check opcode for write access
 #endif
 
-	l.sfgeui r6,0x34		   // check opcode for write access
+	l.sfgeui r6,0x33		   // check opcode for write access
 	l.bnf   1f
 	l.sfleui r6,0x37
 	l.bnf   1f

Signature · 1 line

2.7.4

Guenter Roeck

2016-11-30 01:23 UTC #13 lore raw